While convoluted, this model matches as best we have found so far, the
alignment with scintilla. The spacing is character size for N-1 of the
characters in the 4-space tab stops. The final character is sized for
the actual space character in the stroke font (0.761905)
Fixes https://gitlab.com/kicad/code/kicad/issues/13791
Fixes#12580
Additionally does not export no_connect netlist annotation on pins
which are both connected to another pin and a NC item, unless all
connected pins are stacked at the symbol level.
Adds testing of pin types to netlist QA unit tests.
Some classes had been originally designed to be usable separate from wx,
but over time our uses of the classes have become entertwined with wx
features (e.g. colors), and various changes have also leaked wx into the
classes unguarded. So just remove the option to hide wx in those classes
to simplify the code.
Fixes#10926
Contains the following changes:
- Adds a new ERC_SCH_PIN_CONTEXT class which is used to provide deterministic
comparison between items causing ERC violations (e.g. pins) when associated
with a SCH_SHEET_PATH context.
- Adds association of SCH_SHEET_PATHs for ERC_ITEMs and the sub-schematic items
which caused an ERC violation. This allows correct display of markers on the
sheets of interest only, and allows correct naming resolution and cross-probing
from the ERC dialog.
- Adds a new ERC_TREE_MODEL class, derived from RC_TREE_MODEL, which correctly
resolves component references across heirarchical sheets using the associated
SCH_SHEET_PATHs. This allows sheet-specific component references to be displayed
correctly in the ERC results tree.
- Updates SCH_MARKER to only draw sheet-specific markers on the sheet causing
an ERC violation.
- Increments the schematic file version.
- When loading a schematic with legacy ERC exclusions, discards those of type
ERCE_PIN_TO_PIN_WARNING, ERCE_PIN_TO_PIN_ERROR, ERCE_HIERACHICAL_LABEL, and
ERCE_DIFFERENT_UNIT_NET as there is no safe way to automatically infer the
information which is now stored with these exclusions (sheet paths for error
location and related items). Requiring users to (once) re-add exclusions is
preferable to silently incorrectly matching new ERC issues to legacy exclusions.
When the designer asks to reset annotations, we reset all annotations
including power symbols. This may create additional churn in the files
but only when requested and is useful to fix schematic errors
Fixes https://gitlab.com/kicad/code/kicad/issues/13138
This iterated over all pins to find the pin after a given item. Because
out pattern is consistently to iterate in the outer loop, this means
that we were an O(n^2) loop for the pins just to find their names. This
affected very large parts (e.g. FPGAs) when switching sheets to display
Same pin name != same net name unless the pins are explicitly connected
Also add pin number to all unconnected pads ensuring they have unique
nets
Fixes https://gitlab.com/kicad/code/kicad/issues/13236
Jeff Young
Wayne Stambaugh
Seth Hillbrand
JamesJCode
Mike Williams
Ian McInerney
Fabien Corona
Marek Roszko
jean-pierre charras
Jon Evans
Roberto Fernandez Bautista
Tomasz Wlostowski