Also fixes a bug where all VDMOS instance parameters weren't marked as
instance parameters.
Also fixes a bug where VDMOS thermal models weren't supported (they
have two extra pins: Tj and Tcase).
The simulator has advanced considerably, and it is seeing lots of active
development, so make it a required part of KiCad. Additionally, the
build without the simulator has actually been broken for a while, so no
one clearly is building without ngspice right now.
Fixes#12580
Additionally does not export no_connect netlist annotation on pins
which are both connected to another pin and a NC item, unless all
connected pins are stacked at the symbol level.
Adds testing of pin types to netlist QA unit tests.
Fixes#10926
Contains the following changes:
- Adds a new ERC_SCH_PIN_CONTEXT class which is used to provide deterministic
comparison between items causing ERC violations (e.g. pins) when associated
with a SCH_SHEET_PATH context.
- Adds association of SCH_SHEET_PATHs for ERC_ITEMs and the sub-schematic items
which caused an ERC violation. This allows correct display of markers on the
sheets of interest only, and allows correct naming resolution and cross-probing
from the ERC dialog.
- Adds a new ERC_TREE_MODEL class, derived from RC_TREE_MODEL, which correctly
resolves component references across heirarchical sheets using the associated
SCH_SHEET_PATHs. This allows sheet-specific component references to be displayed
correctly in the ERC results tree.
- Updates SCH_MARKER to only draw sheet-specific markers on the sheet causing
an ERC violation.
- Increments the schematic file version.
- When loading a schematic with legacy ERC exclusions, discards those of type
ERCE_PIN_TO_PIN_WARNING, ERCE_PIN_TO_PIN_ERROR, ERCE_HIERACHICAL_LABEL, and
ERCE_DIFFERENT_UNIT_NET as there is no safe way to automatically infer the
information which is now stored with these exclusions (sheet paths for error
location and related items). Requiring users to (once) re-add exclusions is
preferable to silently incorrectly matching new ERC issues to legacy exclusions.
When the designer asks to reset annotations, we reset all annotations
including power symbols. This may create additional churn in the files
but only when requested and is useful to fix schematic errors
Fixes https://gitlab.com/kicad/code/kicad/issues/13138
This iterated over all pins to find the pin after a given item. Because
out pattern is consistently to iterate in the outer loop, this means
that we were an O(n^2) loop for the pins just to find their names. This
affected very large parts (e.g. FPGAs) when switching sheets to display
This moves some stuff to REPORTER APIs. Moving more stuff would be good,
but it probably too high-risk at present. We'll wait for 8.0 for that....
Fixes https://gitlab.com/kicad/code/kicad/issues/13359
1) if a legacy model references a library then we need to see if said
libraray exists and read model from it if so
2) legacy node ordering is by index, not pin name
3) we can't auto-generate a pin map when we don't know the pin names,
so don't try
Also moves passive RLC inference out from migration to just-in-time
creation for the simulator or netlisting.
Also fixes a version guard mismatch because the spice migration was
done inside UpdateSymbolInstances (which has its own version guard).
Also changed UpdateSymbolInstances to UpdateSymbolInstanceData so
someone else in the future doesn't think it's a general-purpose symbol
instance updater.
Wayne Stambaugh
Jeff Young
Ian McInerney
Roberto Fernandez Bautista
Ian McInerney
Mike Williams
JamesJCode
Fabien Corona
Marek Roszko
jean-pierre charras
Jon Evans
Seth Hillbrand
Barabas Raffai
Mikolaj Wielgus