- SEGVIA becomes VIA
- Drill size moved from TRACK to VIA
- Removed shape from TRACK, becomes ViaType in VIA
- GetTrace becomes GetTrack, for uniformity
- Some minor constification and typo fixes
Renamed BOARD_CONNECTED_ITEM::SetNet() -> SetNetCode()
Added BOARD_CONNECTED_ITEM::GetNet() for accessing NETINFO_ITEM* of a given item.
Fixed module editor crash when launched to edit a module from a PCB.
Replaced some BOARD::FindNet( item->GetNet() ) calls with BOARD_CONNECTED_ITEM::GetNet().
Renamed BOARD_CONNECTED_ITEM::SetNet() -> SetNetCode()
Added BOARD_CONNECTED_ITEM::GetNet() for accessing NETINFO_ITEM* of a given item.
Fixed module editor crash when launched to edit a module from a PCB.
Replaced some BOARD::FindNet( item->GetNet() ) calls with BOARD_CONNECTED_ITEM::GetNet().
Added DIMENSION::SetOrigin(), DIMENSION::SetEnd(), DIMENSION::GetOrigin(), DIMENSION::GetEnd(), DIMENSION::GetHeight().
Fixed flipping for DIMENSION class.
Added an information that helps to understand roles of the points in the DIMENSION class.
Some minor changes to PCB_PAINTER (mainly using const COLOR4D& for taking the result of GetColor() function).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
GetNet() refers to the net code stored in the NETINFO_ITEM. SetNet() finds an appropriate NETINFO_ITEM and uses it.
Removing GetNet() & SetNet() (and the whole net code idea) requires too many changes in the code (~250 references to the mentioned functions).
BOARD_CONNECTED_ITEMs by default get a pointer to NETINFO_ITEM that stores unconnected items. This requires for all BOARD_CONNECTED_ITEMs to have a parent (so BOARD* is accessible). The only orphaned item is BOARD_DESIGN_SETTINGS::m_Pad_Master, but it does not cause any issues so far.
Items that do not have access to a BOARD (do not have set parents) and therefore cannot get net assigned, by default get const static NETINFO_LIST::ORPHANED.
Performed tests:
- loaded .kicad_pcb, KiCad legacy board, Eagle 6.0 board, P-CAD board - all ok
- load a simple project, reload netlist after changing connections in eeschema - ok
- save & reload a board - ok, but still contain empty nets
- remove everything, restore with undo - ok
- remove everything, reload netlist - ok
- changing net names (all possibilites: empty->existing, empty->not existing, existing->empty, existing->not existing) - all ok
- zones: when net is changed to a net that does not have any nodes besides the zone itself, it does not get filled
- ZONE_CONTAINER::m_Netname field
- ZONE_CONTAINER::SetNetName()
- ZONE_CONTAINER::SetNet() [it uses the one in BOARD_CONNECTED_ITEM]
- ZONE_CONTAINER::GetNetName() [instead BOARD_CONNECTED_ITEM::GetNetname is used]
- ZONE_CONTAINER::SetNetNameFromNetCode()
Performed tests:
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
D_PAD::GetNetname() and D_PAD::GetShortNetname() were moved to BOARD_CONNECTED_ITEM. Now they use the net name stored in NETINFO_ITEM.
Moved some one-line functions from class_board_connected_item.cpp to class_board_connected_item.h.
Added a copyright notice, moved Doxygen comments from class_board_connected_item.cpp to class_board_connected_item.h.
I have some doubts if changes introduced pcbnew/dialogs/dialog_pad_properties.cpp do not break anything, but I could not find a test case that breaks the pcbnew.
Performed tests:
- changed pad's net name from empty to existent - ok, name was changed
- changed pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty
- changed pad's net name from existent to empty - ok, net name became empty
- changed pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed
- (re)reading netlists, including net changes - fine, changes are applied, but empty nets are still kept
- loaded pcbnew/pcad2kicadpcb_plugin/examples/CK1202_V1.pcb to test P-CAD import plugin - ok, net names are correct
- imported an Eagle 6.0 board (Arduino Uno; http://arduino.cc/en/uploads/Main/arduino_Uno_Rev3-02-TH.zip) then saved in .kicad_pcb format and reloaded - ok, net names are correct
- saved demos/video/video.kicad_pcb in legacy format and then loaded it again - ok, net names are correct
NETINFO_ITEM::m_Net and NETINFO_ITEM::m_Netname are const.
Changes to be verified:
- pcbnew/minimun_spanning_tree.cpp: It segfaults is m_Size == 0
- pcbnew/exporters/export_gencad.cpp: I removed the SetNetname() call, as it changes only the unconnected net and in the next line it returns if the net is unconnected. Still, I wonder if name for the unconnected net matters. What about tests that check if a net name is empty to decide if it is unconnected net or not.
* When loading footprint do not retest every footprint in cache. Only test
the footprint being loaded. Fixes long load times on libraries with a lot
of parts.
* Fix footprint name bug where file extension was added to the end of the
footprint name.
* Fix bug in path equivalence test due to Posix path separators in footprint
library table. Convert paths to native separator before comparison.
* Fix a bug in FOOTPRINT_VIEWER_FRAME::OnActivate() which cause the footprint
list to always get reloaded when using footprint library tables.
* Remove some unnecessary debugging messages.
* Add a few Doxygen comments to FP_CACHE in kicad_plugin.cpp.
* Use FPID instead of wxString in MODULE object.
* Use FPID instead of wxString when loading and saving files.
* Use FPID in COMPONENT object.
* Add wxString helper functions and comparison operators to FPID.
* Add fp_lib token to pcb and netlist file formats.
* Add code to load and save FPIDs to pcb file format.
* Fix segfault when deleting invalid footprint library tables in Pcbnew
in non footprint library table build.
* Fix bug when counting the number of mod files in
EDA_APP::SetFootprintLibTablePath();
*) add hotkey for setting the grid origin as 'S', in board editor, module editor.
*) re-position the function interface for cursor movement from BASE_SCREEN into
class EDA_DRAW_FRAME. This is a prelude to getting rid of BASE_SCREEN or
splitting it up.
This is limited to round tripping the lines of commented text in the
loading and saving to disk through PCBIO::Format() and PCBIO::Parse().
No editing of the comments is given.
* Fix a bug when full file name and path are passed to FOOTPRINT_INFO::
ReadFootprintFiles() which I created in bug fix lp:593989.
* Fix a wxString debug assertion in EDA_APP::InitEDA_Appl() when the KICAD
environment variable is defined as an empty string.
* Add error dialog when libraries cannot be found in system search path
when loading footprint using the select footprint dialog.
* Add footprint library name column to the EDA_LIST_DIALOG when selecting
footprints from the list.
* Allow reading all columns from the selected row in EDA_LIST_DIALOG.
* Remove redundant sort from EDA_LIST_DIALOG constructor
* Add library name member variable and accessors to FOOTPRINT_INFO.
* Make headers translatable for Eeschema select component from list dialog.
* Add some helper methods to FPID for identifying the FPID type and validity.
* Remove a bunch of trailing whitespace and add missing license comments.
* Complete encapsulation of the ZONE_CONTAINER class.
* Fixed a bug in the EDA_TEXT::Format() default effects behavior due to
improper conversion to internal units and missing test for default
thickness.
* Improved grammar of some Pcbnew context menu strings.
* Moved some more cleverly hidden BOARD object methods into class_board.cpp.
* Lots of coding policy and documentation fixes.
standard layer name support from BOARD::GetLayerName(). This function evolved
in a contorted direction over time, and was being asked to return one of 3
different kinds of layer names, even though it only took a boolean to control
that choice.
Users are better served by forcing them to get to know the concise new
English Standard layer names. This is because these concise names show up
in the "pretty" footprint/module files as the standard representation of
both feature and copper layers.
Change the name of BOARD::GetDefaultLayerName() to GetStandardLayerName().
Drop boolean argument to both BOARD::GetStandardLayerName() and
BOARD::GetLayerName().
* Complete encapsulation of the MODULE class.
* Complete encapsulation of the EDA_TEXT class.
* Encapsulate most of the ZONE_CONTAINER class.
* Add pcbcommon library as a dependency for reSWIGging the scripting
support. This should cover most dependency cases.
* Encapsulate most of the MODULE class.
* Start encapsulating the DIMENSION class.
* Lay some groundwork for EDA_TEXT encapsulation.
* Move cleverly hidden MODULE functions into class_module.cpp.
* Use std::swap to exchange TEXTE_PCB values for undo/redo.
* Remove unused members from MODULE class.
* The usual coding policy and documentation fixes.
* Add check for pad type and force drill size to zero if pad is surface
mount in PCB_PARSER.
* Modify the D_PAD SetAttribute method to clear drill size if pad type is
set to surface mount.
Segment Hit Test: enhanced detection near segment ends (noticeable for instance when clicking on short tracks in Pcbnew.
Remove duplicate code about segment hit test.
remove unused file.
This required the additional compiler command line option "-std=c++0x".
2) Switch to unique_ptr from auto_ptr which is C++ deprecated.
3) Change to new English layer names per mailing list discussion, see class_board.cpp.
4) When saving to *.kicad_pcb or *.kicad_mod, identify opportunities to use wildcard
layer sets, for pads so far.
5) Switch to two std::string hashtables in pcb_parser.cpp, away from one wxString based one
for layer names and layer sets mapping. One hashtable holds the mask, the other the index.
Layer sets are only in the mask table.
6) Move "LOCALE_IO toggle" into PCB_IO::Format() since it is a public API function and
caller should find it as convenient as possible to use. LOCALE_IO should handle
nesting OK in the case where public Format() is called from one of the Footprint*()
functions.
7) Drop support for "export module to new library". Creating new libraries will have to
be handled in concert with library table entries, and we've talked recently about
creating a better footprint library manager, one that resides in a DLL/DSO. So
this kind of functionality needs to be handled in there in the near future.
8) Change name of exported PCB_IO module/footprint to *.kicad_mod and not *.emp.
can be parsed, since they do not have an overriding layer name map
like a BOARD does.
Avoid doubly looking up hashtable entries in m_layerMap.
Minor code reformatting.
* Add footprint methods to PCB_IO.
* Add FP_CACHE and FP_CACHE_ITEM for handling new footprint library design.
* Add code to save legacy libraries in new format.
* Change behavior of BOARD_ITEM::GetLayerName() to return the default layer
name when the item does not have a BOARD as a parent.
* Minor changes to the module output formatter when writing to module library
files (no BOARD as parent).
* Add new (and some that I forgot along the way) CMake flags to
EDA_BASE_FRAME::CopyVersionInfoToClipboard().
* Add -Wno-narrowing to GCC flags to stop GCC 4.7 from complaining about
a conversion from int to unsigned in the Boost polygon library.
* Add INPUT_STREAM_READER to richio.cpp to allow using any object derived
from wxInputStream as a LINE_READER (needs to be validated).
This is *a work in progress*, so some features are missing, and/or could be modified.
Mainly keepout zones are not yet exported to autorouters, and pads are not taken in account.
Some code cleanup in polygon.*
When reading board files, the net 0 was stored twice.
It creates only log messges in debug mode, because the list of nets is rebuild after reading files.
Use now English layers names to build filenames in plot functions (for techical layers), because translated names create sometimes problems in filenames.
(should do not change anything for English users)
* Use index when saving layers to handle translated layer names.
* Add LOCALE_IO switcher when loading s-expression format.
* Make SEGVIA default to through hole to improve file size.
* Don't save default orientation of 0 degrees in TEXTE_MODULE and TEXTE_PCB.
* Don't save default zone configuration parameters.
* Save multiple zone corners on a single line.
* Fixed missing ( check in graphic and module arc parsers.
* Consistency improvements for DRAWSEGMENT and EDGE_MODULE objects.
* Minor tweaks to D_PAD formatting.
* Change save order of drawings to match legacy file format object order.
* Set end point of SEGVIA to start point so the round trip back to legacy
format is the same.
* Fixed bug saving and loading oval pad drill parameters.
* Fixed bug saving and loading rectangular pad deltas.
* Fixed missing layer for PCB_TARGET.
* Fixed EDA_TEXT italic bug. Thanks Dick!
* Remove some left over debug logging statements.
* Apply Dick's patch along with a few minor changes to fix some clashes with
changes in my branch. Thanks Dick!
* Added missing DRAWSEGMENT line angle.
* Fix thru hole pad layer mask issue.
* Add s-expression file parser object and keyword files.
* Fix minor issues with s-expression file formatting.
* Fix a minor bug the zone container fill state parsing in the legacy plugin.
* Move EDA_TEXT visibility definition to eda_text.h.
* Add minor BOARD_ITEM object improvements to support s-expression file
parser.
Maciej Suminski
Lorenzo Marcantonio
jean-pierre charras
Povilas Kanapickas
Wayne Stambaugh
Dick Hollenbeck
Andrey Fedorushkov