Commit Graph

24 Commits

Author SHA1 Message Date
Jeff Young a48867ea01 Solder mask integrity testing.
ADDED DRC test for solder mask aperture bridging copper from different
nets.
ADDED visualization of minimum web width processing for solder masks.
ADDED allow_soldermask_bridges property for footprints.

Fixes https://gitlab.com/kicad/code/kicad/issues/2183

Fixes https://gitlab.com/kicad/code/kicad/issues/1792
2021-12-23 22:31:14 +00:00
Jeff Young 0a609dd48d Add footprint library checking to DRC.
Fixes https://gitlab.com/kicad/code/kicad/issues/6821
2021-12-23 19:18:45 +00:00
Jeff Young 81fc710a5d Use consistent terminology.
Fixes https://gitlab.com/kicad/code/kicad/issues/8681
2021-06-26 10:11:41 +01:00
Jeff Young 4c3d78dec0 Break out separate holes-co-located violation.
Fixes https://gitlab.com/kicad/code/kicad/issues/8456
2021-05-20 10:36:56 +01:00
Sylwester Kocjan 31da3e7dc6 qa: merge unit_test_utils to qa_utils 2021-05-19 11:02:52 +00:00
Seth Hillbrand 9ed6cdd943 Remove GITHUB plugins
KiCad github downloads are no longer supported

Fixes https://gitlab.com/kicad/code/kicad/issues/6182
2020-10-29 16:45:04 -07:00
Jeff Young 42eecdfd3a Collapse silk constraints down to one.
Also updates the rule syntax help and code-completion with a bunch
of diff-pair and other stuff that hadn't been updated yet.
2020-10-11 13:19:23 +01:00
Tomasz Wlostowski bd27d38d9a DRAW_PANEL_GAL: added DebugOverlay() method, creating a temporary overlay for drawing debug graphics 2020-10-07 16:36:37 +02:00
Jeff Young 85c6cebd77 Rework silk-to-pad checker to handle all solder mask clipping of silk.
Fixes https://gitlab.com/kicad/code/kicad/issues/5851
2020-10-04 13:21:01 +01:00
Jeff Young bf67648562 Support optional location reporting in SHAPE collisions.
Also fixes a few bugs in the collision routines.
2020-09-28 23:28:33 +01:00
Jeff Young 8420fcc33b Cleanup. 2020-09-13 17:08:24 +01:00
Jeff Young ce2937a399 Move rest of DRC tests to kicad. 2020-09-11 23:14:12 +01:00
Jeff Young 5424d6fa09 Move new clearance tests into kicad. 2020-09-11 21:26:57 +01:00
Jeff Young cc86630f11 Start pulling new DRC engine into Kicad. 2020-09-11 16:04:11 +01:00
Roberto Fernandez Bautista 3b3af5327f CADSTAR PCB Archive Importer: Move code into common/plugins and pcbnew/plugins folders 2020-09-08 21:21:20 +00:00
Roberto Fernandez Bautista 4c2f38f1ad CADSTAR PCB Archive Importer: Parse LIBRARY section + code refactoring
code refactoring:
- Renamed CADSTAR_COMMON to CADSTAR_ARCHIVE_COMMON
- Renamed CPA_FILE to CADSTAR_PCB_ARCHIVE_PARSER
- Made CADSTAR_PCB_ARCHIVE_PARSER a derived class of CADSTAR_ARCHIVE_COMMON
- Moved all structures in cadstar_pcb_archive_parser.h/.cpp to be defined inside CADSTAR_PCB_ARCHIVE_PARSER class
2020-09-08 21:21:20 +00:00
Tomasz Wlostowski adbd94553d drc_proto: all tests now supported in drc_proto. Not tested yet! 2020-09-08 01:31:42 +02:00
Thomas Pointhuber a03fb7a9a8 Altium: Refactor and add initial structure for schematic importer
altium: move pcbnew/altium2kicadpcb_plugin -> pcbnew/plugins/altium

See: https://gitlab.com/kicad/code/kicad/-/issues/4412
2020-08-23 19:01:08 +00:00
Tomasz Wlostowski 35e45c5917 drc_proto: edge clearance wip 2020-08-13 14:50:59 +02:00
Seth Hillbrand 7c455f2357 First pass at DRC RTree functionality
This implements a copper-layer RTree with functions for iterating over
the elements in a copper layer and providing Nearest Neighbor returns
for BOARD_CONNECTED_ITEMS
2020-08-11 16:52:29 -07:00
Tomasz Wlostowski 128ae8b49e drc_proto: working on hole size/track width checker 2020-07-29 23:14:34 +02:00
Tomasz Wlostowski e9d37dd7ce drc_proto: implement QueryWorstConstraint 2020-07-05 22:44:38 +02:00
Tomasz Wlostowski 1cabc1bc0f qa/drc_proto: rework common clearance code into base class, start working on hole clearance test refactor 2020-07-05 22:44:38 +02:00
Tomasz Wlostowski 085698d17c drc_proto: wip 2020-07-05 22:44:38 +02:00