4f71260319
Fix micro via size incorrect when adding it in pns router
2015-06-18 20:22:23 +02:00
a16dd894d5
Show Place & Drill origin in GAL.
2015-06-18 17:51:54 +02:00
28a270a328
Refactored grid origin point drawing (GAL).
2015-06-18 17:51:53 +02:00
2ebacfa3c2
GAL sets appropriate top layer after loading a PCB.
2015-06-18 17:51:53 +02:00
fa3d074ca4
Find command zooms in found items (GAL).
2015-06-18 17:51:52 +02:00
8964ff8922
Hotkey lists displayed after pressing the Help button (GAL).
2015-06-18 17:51:52 +02:00
f63170ca84
Tools available under toolbar buttons: delete items, highlight net, set drill/place origin (GAL).
2015-06-18 17:51:51 +02:00
057bd1b886
PICKER_TOOL - generic tool for picking a point.
2015-06-18 17:51:51 +02:00
ac10ca40f8
Net highlighting is moved to a separate TOOL_ACTION.
2015-06-18 17:51:50 +02:00
c636c4e735
Fix to closing polylines in DXF imports.
...
The DXF format polylines and lwpolylines have a 'flags' field of which bit 0 indicates if the polyline/lwpolyline is to be closed or open.
This flags field is correctly read during the import but in the conversion to board segments, was previously not used.
2015-06-18 17:51:17 +02:00
1c8fd8b207
Eeschema: remove the run cvpcb menu entry from eeschema tools menu when running as stand alone.
...
Pcbnew: fixes a problem exporting to DSN where the layername for B_Cu provided to the *.DSN file was incorrect
2015-06-18 15:29:26 +02:00
6ff03b41fd
Vias, creation and editon: fix a bug in legacy mode when creating a micro-via (the drill diameter was the standard vias drill, not the micro-via drill).
...
Also in global vas edition, always set the via drill to the actual current netclass value (do not use anymore the 0 value as default), to avoid unwanted invisible drill change for existing vias when the netclass value is modified.
This is consistent with the via creation, in GAL mode
2015-06-18 15:20:32 +02:00
07d6cbaeb7
Vias, creation and editon: fix a bug in legacy mode when creating a micro-via (the drill diameter was the standard vias drill, not the micro-via drill).
...
Also in global vas edition, always set the via drill to the actual current netclass value (do not use anymore the 0 value as default), to avoid unwanted invisible drill change for existing vias when the netclass value is modified.
This is consistent with the via creation, in GAL mode
2015-06-18 15:19:30 +02:00
3a9dfe274b
Zoom to DRC error after double clicking an entry (GAL).
2015-06-18 11:35:02 +02:00
d3b31316ba
Fixed module text visibility settings (GAL).
2015-06-16 17:03:36 +02:00
12adb25a71
Fixed 'Edit in footprint editor' hotkey (GAL).
2015-06-16 15:27:59 +02:00
dd5275f6c6
Minor SELECTION_TOOL fixes.
2015-06-16 14:51:39 +02:00
b562cfb8bb
WX_HTML_REPORT_PANEL: a REPORTER widget on steroids.
2015-06-16 14:20:42 +02:00
d433a06d11
Fixed initialization for custom track/via size values (PNS). More meaningful error messages.
2015-06-15 17:54:58 +02:00
49fac351ab
Fix a few coverity warnings.
2015-06-15 16:01:43 +02:00
6d07e9a754
Fixed dialogs asserts.
2015-06-15 15:54:58 +02:00
db44fc3649
Removed debug messages from Footprint Library Wizard.
2015-06-15 14:53:40 +02:00
c70f4a0706
Pcbnew: Increase board thickness limit from 3mm to 10mm
2015-06-14 20:18:34 +02:00
dc9ebf30e5
A few minor fixes. Eeschema: add a workaround (not afix) to solve issue Bug #1464773 (Print bug with differently sized subsheets).
2015-06-14 19:58:57 +02:00
fc15404947
Fix a build issue in scripting mode (due to a no more existing method still declared in class_zone.h header)
2015-06-12 18:32:24 +02:00
eba3a55bb2
pcbnew: new zone filling algorithm using ClipperLib. Possibility to fall back to the old one
2015-06-12 17:13:18 +02:00
8b33bfc61b
Fix remaining invalid net ID bugs in board file parser.
2015-06-12 09:59:58 -04:00
0027bb14c5
Pcbnew: read netlist dialog: remove the .cmp file option. Use only the netlist to know the footprint associated to a component.
2015-06-12 14:46:41 +02:00
097c73b8eb
Fix crash when parsing a PCB file with an invalid net code.
2015-06-08 15:28:04 -04:00
8fb520249e
Use KiwayExpress messaging for CvPcb footprint assignment instead of *.cmp file.
...
* Remove global s_NetObjectslist.
* Separate out non-owning version of NETLIST_OBJECTS_LIST into NETLIST_OBJECTS.
* Fix double free pertaining to ~NETLIST_READER().
* Remove all file-io from CvPCB.
* Remove exe launcher cvpcb, retain only cvpcb.kiface, since cvpcb.kiface has no file i/o.
* Add void CVPCB_MAINFRAME::KiwayMailIn( KIWAY_EXPRESS& mail ) and teach it to use old
netlist loading code with a STRING_LINE_READER LINE_READER.
* Fix BEGIN_EVENT_TABLE( CVPCB_MAINFRAME, KIWAY_PLAYER )
2015-06-07 14:18:45 -04:00
aadcd93ab5
Removed a redundant field in RN_NODE class.
2015-06-05 17:49:01 +02:00
e86351b1b0
Fixed ratsnest for tracks with 0 length.
2015-06-05 17:49:01 +02:00
fa421f15d8
Clearer dynamic ratsnest (for moved items).
2015-06-05 17:49:00 +02:00
16db8e644b
Logical operators for ratsnest node filters.
2015-06-05 17:49:00 +02:00
6cc535f27f
Less significant changes to the ratsnest code (GAL).
2015-06-05 17:49:00 +02:00
f202e5318c
Fixed SELECTION_CONDITIONS::lessThanFunc().
2015-06-05 17:48:59 +02:00
16daa04518
Fix title capitalization in P&S router properties dialog.
2015-06-05 09:59:57 -04:00
209e630873
Disable net highlighting after loading a new board.
2015-06-04 14:54:08 +02:00
ce4b4f8221
Update ratsnest on zone refill (GAL).
2015-06-04 14:54:08 +02:00
c23adc47b7
Ratsnest algorithm distinguishes layers (GAL).
2015-06-04 14:54:08 +02:00
42215f2388
Moved GetLayerSet() to BOARD_ITEM.
2015-06-04 14:54:07 +02:00
a12ea29de8
Refactored the way zones are kept in ratsnest model (GAL).
2015-06-04 14:54:07 +02:00
a2b8ab6b41
Ratsnest fix (GAL).
2015-06-04 14:54:07 +02:00
0331d9958a
Minor optimization for ratsnest.
2015-06-04 14:54:06 +02:00
e81477704d
Make OK button default in P&S router properties dialog.
2015-06-04 08:21:30 -04:00
064e8a82e1
Fixed an assertion in arc drawing tool (GAL).
2015-06-02 20:16:55 +02:00
ba37f33bbb
Pcbnew: Use a better (i.e. more suitable to calculate clearance areas) algorithm to inflate/deflate zones outlines. It fixes bug#1459734.
...
Previously, acute angles (especially small angles) in zone outlines create incorrect shapes and sometimes strange shapes for clearance areas, when using generic algorithms.
This happens when zones outlines have "spikes", but not usually for smooth outlines.
2015-05-30 14:02:55 +02:00
2500976e31
Fix undefined MODULE dtor for auto_ptr in pcb_netlist.h which caused a memory leak. Thanks Simon Richter for finding this.
2015-05-28 20:21:38 -04:00
2db1b3adc8
Print out footprint texts placed on layers different than silkscreen.
2015-05-27 22:14:51 +02:00
cfeabde282
Grey out text in high-contrast mode.
2015-05-27 22:13:51 +02:00
jean-pierre charras
Maciej Suminski
unknown
unknown
Jon Neal
Tomasz Wlostowski
unknown
Chris Pavlina
Wayne Stambaugh
Simon Schubert