* Switched hashtables.h over to std::undordered_map from boost version.
* Added new macros DECL_VEC_FOR_SWIG() and DECL_MAP_FOR_SWIG() in macros.h.
These along with future DECL_HASH_FOR_SWIG() unify the declaration to swig
and C++ so that the resultant type name is common in both languages, and
the types AGREE.
* Fixed swigging of NETINFO_ITEM and NETINFO_LIST via magic.
* Newly exposed (python wrapped) are: D_PADS, TRACKS (was TRACK_PTRS),
NETNAME_MAP, NETCODE_MAP, wxString (without constructor purposely, read
comment in wx.i), MARKERS, ZONE_CONTAINERS, NETCLASSPTR, KICAD_T types.
* std::vector<SOMETHING*> tends to end up named SOMETHINGS in C++ and python.
Having the name consistent between like types is helpful, and between
languages. std::map<> ends up as SOMETHING_MAP.
* NETINFO_LIST::m_netNames and NETINFO_LIST::m_netCodes are now std::map
instead of hashtables, because swig does not yet support std::unordered_map.
* You can now get to any netclass or net info. NETNAMES_MAP and NETCODES_MAP
are traversable basically the same as a python dictionary using a python
string (not wsString) as the key! The wxString typemap converts python
string to wxString before the lookup happens. Iteration also works.
* Cleanup namespace in enum ZoneConnection in pcbnew/zones.h to self-explained names unification: PAD_ZONE_CONN_INHERITED, PAD_ZONE_CONN_NONE,PAD_ZONE_CONN_THERMAL,PAD_ZONE_CONN_FULL, PAD_ZONE_CONN_THT_THERMAL
added the example gen_gerber_and_drill_files_board.py in demos, which shows how to do that.
Fix a Printf format issue (shown in Debug mode) in Libedit (%d used for a size_t, changed in %zu)
*.i : fix coding style issues.
python method: add BOARD_ITEM Duplicate, which is a wrapper to Clone(). ( defined as Cast_to_BOARD_ITEM(selt.Clone()).Cast() )
update some .py examples.
pcbnew.py + doxygen-xml files, and build .i files with docstrings,
those .i files are included back again to build a pcbnew.py with
extended documentation from C++, finally we take the final pcbnew.py
to build the doxygen-python documentation
DLIST iterator code, now we can do:
for module in pcb.m_Modules:
print module.GetReference()
instead of:
module = pcb.m_Modules
while module:
print module.GetReference()
module = module.Next()
or even:
module_list = list(pcb.m_Modules)
Dick Hollenbeck
jean-pierre charras
Tomasz Wlostowski
unknown
Maciej Suminski
Build System
Lorenzo Marcantonio
Miguel Angel Ajo