[ADDED]: A panel to the schematic editor that allows quick access to all
of the items connected to the currently highlighted net.
This is an initial swag at implementing a full net navigator feature. For
now it only shows the currently highlighted net nodes. The incremental
net list advanced setting must be enabled in order to use this feature due
to performance reasons. There are still some issues with saving the panel
position which will be addressed in the future.
Initial code for serializing wxAuiPaneInfo settings to and from JSON have
be implemented.
The propagation is currently (maybe not needed) limited to the global
name that is the source of the change. We also need to propagate the
global name that is changed in case the global is set in a tree leaf and
not the root
Fixes https://gitlab.com/kicad/code/kicad/issues/14657
A sheetpath is required to correctly resolve text variables.
Depending on currentSheet is rife with bugs.
There are many places where we do *not* want to be prepending
field names to the field values, such as netlisting,
building PDF hypertext menus, etc.
Also, Find/Replace needs to work on unresolved text, as
that's what we're going to display (and if replace nuked
your variable references you wouldn't be happy).
Needs to be static, so keep the reference from the associated symbol and
not the SCH_SYMBOL instance. Both will likely have the same prefix,
which is all we care about here
This ensures that when bus elements or labels matching bus elements are
removed that the stale neighbor/parent references are similarly removed
Matching 7.0 commit 4cdf75dc72
- Ensure that critical paths (ERC/netlister) are fully-rechecked
- Handle symbol/pin distinction in change markers
- Fully connect hierarchical pins in one pass descending
Previously, almost all connectivity updates were full updates, meaning
that the entire connectivity graph would be rebuilt each time a change
was made to the schematic. This update modifies the update to only
correct the subgraphs that are directly affected by the change.
It uses the existing connection graph to find all affected subgraphs as
well as connections to the changes based on the visible schematic.
These elements are removed from the existing connectivity graph and
marked dirty. They then have a new connectivity graph built only around
their changes. The resulting graph is merged into the original.
Currently, this ability is behind an advanced config flag
`IncrementalConnectivity` while testing.
Fixes https://gitlab.com/kicad/code/kicad/issues/10846
Fixes https://gitlab.com/kicad/code/kicad/issues/1794
Previously, bus elements that were not instantiated as individual nets
could not connect to each other. This caused issues for complex
schematics where busses needed to connect to other busses with elements
that resolved to the same net names. Functionally, this means mixing
bus elements, which we will replace with first-class elements in version
8 but currently can only be accomplished either by using bus aliases and
this patch or by individually instantiating each bus element as a
local label
Fixes https://gitlab.com/kicad/code/kicad/issues/14300
(The real bug here is that CONNECTION_GRAPH::assignNetCodesToBus() was
growing the bus aliases members list because it used a non-const
reference to it as a local storage list. The const scoping of it will
prevent this type of error in future.)
Fixes https://gitlab.com/kicad/code/kicad/issues/14269
We don't need two functions to get driver names. The map should be
mutable to allow updates when needed. C++17 gives some extra syntactic
sugar for map manipulation
Fixes#10926
Contains the following changes:
- Adds a new ERC_SCH_PIN_CONTEXT class which is used to provide deterministic
comparison between items causing ERC violations (e.g. pins) when associated
with a SCH_SHEET_PATH context.
- Adds association of SCH_SHEET_PATHs for ERC_ITEMs and the sub-schematic items
which caused an ERC violation. This allows correct display of markers on the
sheets of interest only, and allows correct naming resolution and cross-probing
from the ERC dialog.
- Adds a new ERC_TREE_MODEL class, derived from RC_TREE_MODEL, which correctly
resolves component references across heirarchical sheets using the associated
SCH_SHEET_PATHs. This allows sheet-specific component references to be displayed
correctly in the ERC results tree.
- Updates SCH_MARKER to only draw sheet-specific markers on the sheet causing
an ERC violation.
- Increments the schematic file version.
- When loading a schematic with legacy ERC exclusions, discards those of type
ERCE_PIN_TO_PIN_WARNING, ERCE_PIN_TO_PIN_ERROR, ERCE_HIERACHICAL_LABEL, and
ERCE_DIFFERENT_UNIT_NET as there is no safe way to automatically infer the
information which is now stored with these exclusions (sheet paths for error
location and related items). Requiring users to (once) re-add exclusions is
preferable to silently incorrectly matching new ERC issues to legacy exclusions.
The pressure relief valve was not useful for common work patterns as it
forced the recalculation on many common actions such as bus expansion.
This caused it to actually feel slower than with the pressure relief
valve off.
For most schematics, realtime is now fast enough to not need the valve
and for those that are extremely complex, removing the valve helps this
run more predictably
The pins can exist on a different sheet from the no-connect. In this
case, we do not set the ERC for the current sheet to the remote pins,
instead only link the NC
label has 0 pins -> unconnected label warning
label has 1 pin -> OK only if also has a NC marker, otherwise unconnected pin warning
label has >1 pins -> OK only if has no NC marker, otherwise "NC is connected" warning
Thanks @craftyjon for helping work out the details
Fixes an issue with `wait_for_tasks()` and adds a lower-overhead
`push_loop` helper. We replace our usage of `parallelize_loop` with
`push_loop` as we didn't use the multi-future vector return and don't
need the extra overhead.
Elements such as zero-length lines might get into the connection map,
causing the system to process them twice. This can cause allocation
errors when both are performed at the same time
Fixes https://gitlab.com/kicad/code/kicad/issues/12278
All labels need to be attached to a net that has at least 2 pins in
order for this to be a valid net. To check for the existing pins, we
need to interate over all subgraphs in the net, counting pins
This is mostly to output the aliases sorted (for ease of VCS integration),
but also because a btree will be faster than hashing on a small dataset.
Fixes https://gitlab.com/kicad/code/kicad/issues/11890
To be connected, the label must have at least two pins on a subgraph
(or, in the case of a hierarchical label, two pins somewhere in its
connection)
Fixes https://gitlab.com/kicad/code/kicad/issues/7203
Wayne Stambaugh
jean-pierre charras
Seth Hillbrand
Jeff Young
Mike Williams
JamesJCode
Marek Roszko
Jon Evans