Commit Graph

57 Commits

Author SHA1 Message Date
Dick Hollenbeck 7434e68876 Pcbnew: improved track scripting support. 2016-07-19 16:34:09 -04:00
Dick Hollenbeck e24990146d Pcbnew: major swig fix.
* Switched hashtables.h over to std::undordered_map from boost version.

* Added new macros DECL_VEC_FOR_SWIG() and DECL_MAP_FOR_SWIG() in macros.h.
  These along with future DECL_HASH_FOR_SWIG() unify the declaration to swig
  and C++ so that the resultant type name is common in both languages, and
  the types AGREE.

* Fixed swigging of NETINFO_ITEM and NETINFO_LIST via magic.

* Newly exposed (python wrapped) are: D_PADS, TRACKS (was TRACK_PTRS),
  NETNAME_MAP, NETCODE_MAP, wxString (without constructor purposely, read
  comment in wx.i), MARKERS, ZONE_CONTAINERS, NETCLASSPTR, KICAD_T types.

* std::vector<SOMETHING*> tends to end up named SOMETHINGS in C++ and python.
  Having the name consistent between like types is helpful, and between
  languages.  std::map<> ends up as SOMETHING_MAP.

* NETINFO_LIST::m_netNames and NETINFO_LIST::m_netCodes are now std::map
  instead of hashtables, because swig does not yet support std::unordered_map.

* You can now get to any netclass or net info.   NETNAMES_MAP and NETCODES_MAP
  are traversable basically the same as a python dictionary using a python
  string (not wsString) as the key!  The wxString typemap converts python
  string to wxString before the lookup happens.  Iteration also works.
2016-07-18 13:23:09 -04:00
Jon Neal 1293d04a7a Fix a bunch of misspellings of length. 2016-07-10 23:09:18 -04:00
Tomasz Wlostowski ee3418e90b One-click PCB update improvements
- Fix repetitive undo/redo segfaults & assertions.
- Add Update menu entry on PCB side.
- Fix Python build error
- Add spread footprints after updating
2016-01-29 15:43:40 +01:00
Tomasz Wlostowski 5ef6001e06 pcbnew: support for removing NETINFO_ITEMS from BOARD for proper netlist undo 2016-01-29 11:29:56 +01:00
Tomasz Wlostowski 9e609acae3 made netlist entries and netlist update undoable 2016-01-29 11:21:13 +01:00
Dick Hollenbeck b27176f230 Pcbnew: fix segfault after deleting a pad from a footprint then performing a DRC action such as a via drag. 2015-09-23 19:02:40 -04:00
jean-pierre charras c519eea12b 3D viewer: fix (the fix is not perfect) a minor issue in zone rendering: copper thickness was not good when the option 'Show Holes in Zones" was OFF, and "Show Copper Thickness" ON.
Fix a few coverity minor warnings.
2015-04-12 19:44:46 +02:00
jean-pierre charras 39497b109e Pcbnew: fix Bug #1422093 (pcbnew crashes after editing a footprint cominng from the board with the fp editor and saving it on a librray and trying to load it to the board)
Some other very minor fixes.
2015-02-17 17:32:47 +01:00
jean-pierre charras ebb967c46f Pcbnew: fix issues and potential issues when reading board files and mainly old board files, and enhance the DRC tests and Delete Single Pad Net option when reading a netlist:
* Delete Single Pad Net option does not delete the net if a zone use this net (i.e. is attached to this pad).
* pcb_parser accept now negative netcodes in zones (can happen with old files, which previously could crash Pcbnew)
* pcb_parser accept now files with incorrect or missing net count  (can happen with old files, which previously could crash Pcbnew)
* if a zone has a non-existent net name it now keep this net name, and DRC detect it (previously, the net name was lost, and the DRC did not tected this issue).
* Drc test: now detect a "dead" net, i.e. a net with 0 pads, but still used by a zone. It happens easily after a schematic modification, when a net disappears or is renamed.
2015-01-22 13:06:34 +01:00
Maciej Suminski fa846932c1 bugfix 1325375: pcbnew crash while append a board 2014-06-02 11:41:54 +02:00
Maciej Suminski f31f92e45e Fixes the bug that causes pcbnew crash, when there are multiple net classes and the plot dialog was opened.
Changed NETCLASS* to boost::shared_ptr<NETCLASS>.
2014-05-20 11:29:37 +02:00
jean-pierre charras 9c1f6b7307 Pcbnew: fix Bug #1304418 . Fix also a related issue which crashes Pcbnew in some corner cases.
(for instance, when a footprint from the currently edited board is loaded in the footprint editor, and when the board is cleared or reloaded)
In footprint editor, the net names are no more shown od modifiable (becuase the footprint editor does not know anything about net names.
This change should allow the changes planned in pcbnew.
2014-04-24 20:54:49 +02:00
Maciej Suminski 55f9aaabd7 Workarounded SWIG problems (does not support nested C++ classes, more on the subject: http://www.swig.org/Doc1.3/SWIGPlus.html#SWIGPlus_nested_classes). 2014-03-12 14:58:49 +01:00
Maciej Suminski 75026d8754 Renamed BOARD_CONNECTED_ITEM::GetNet() -> GetNetCode()
Renamed BOARD_CONNECTED_ITEM::SetNet() -> SetNetCode()
Added BOARD_CONNECTED_ITEM::GetNet() for accessing NETINFO_ITEM* of a given item.
Fixed module editor crash when launched to edit a module from a PCB.
Replaced some BOARD::FindNet( item->GetNet() ) calls with BOARD_CONNECTED_ITEM::GetNet().
2014-02-25 11:40:34 +01:00
Maciej Suminski 15b8d3d20a Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).

Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.

- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).

- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.

- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok

Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 10:19:51 +01:00
Maciej Suminski 441e03172c Added iterators for NETINFO_LIST (as net codes for existing net codes may be not consecutive). 2014-01-16 16:47:31 +01:00
Maciej Suminski 8a4e723504 NETINFO_ITEMs are not stored in a vector anymore, instead they are held in a unordered_map. Now, the net codes may be not consecutive. There is another way for assigning net codes (using a static int that holds a possible empty net code and a function that makes sure it is not used [getFreeNetCode()]).
Removed some unused fields (NETINFO_ITEM::m_NbNodes, m_NbLink, m_NbNoconn, m_Flag).
2014-01-16 14:20:51 +01:00
Maciej Suminski d62b47a0df BOARD_CONNECTED_ITEMs do not store net code anymore (m_NetCode field), instead net info is stored using a pointer to NETINFO_ITEM.
GetNet() refers to the net code stored in the NETINFO_ITEM. SetNet() finds an appropriate NETINFO_ITEM and uses it.
Removing GetNet() & SetNet() (and the whole net code idea) requires too many changes in the code (~250 references to the mentioned functions).
BOARD_CONNECTED_ITEMs by default get a pointer to NETINFO_ITEM that stores unconnected items. This requires for all BOARD_CONNECTED_ITEMs to have a parent (so BOARD* is accessible). The only orphaned item is BOARD_DESIGN_SETTINGS::m_Pad_Master, but it does not cause any issues so far.
Items that do not have access to a BOARD (do not have set parents) and therefore cannot get net assigned, by default get const static NETINFO_LIST::ORPHANED.

Performed tests:
- loaded .kicad_pcb, KiCad legacy board, Eagle 6.0 board, P-CAD board - all ok
- load a simple project, reload netlist after changing connections in eeschema - ok
- save & reload a board - ok, but still contain empty nets
- remove everything, restore with undo - ok
- remove everything, reload netlist - ok
- changing net names (all possibilites: empty->existing, empty->not existing, existing->empty, existing->not existing) - all ok
- zones: when net is changed to a net that does not have any nodes besides the zone itself, it does not get filled
2014-01-15 18:03:06 +01:00
Maciej Suminski 3017b61711 Added NETINFO_LIST::UNCONNECTED constant. 2014-01-15 09:34:16 +01:00
Maciej Suminski bf80cc770e Changed the way of looking up NETINFO_ITEM using net names (using boost::unordered_map). Added a hash function (wxString) for that. Introduced NETINFO_ITEM::GetNetItem( wxString ). BOARD::FindNet() uses the map.
Net codes are updated upon net list update. (BOARD::ReplaceNetlist())
Added in some places (mostly class_board.cpp) pad->SetNet() calls to synchronize net codes.
On creation of NETINFO_LIST, the first NETINFO_ITEM is added (the unconnected items net).
Removed COMPONENT_NET::m_netNumber, as it was not used anywhere.
Added an assert to D_PAD::GetNetname(), checking if net code and net name is consistent for unconnected pads. Added an assert for NETINFO_LIST::AppendNet() to assure that appended nets are unique.

It seems that at this point:
- Updating net lists works fine. The only difference between the file ouput is that after changes it contains empty nets as well.
- Nets are not saved in the lexical order. Still, net names and net codes are properly assigned to all items in the .kicad_pcb file. It is going to be addressed in the next commit. I believe it should not create any problems, as pads are sorted by their net names anyway (NETINFO_LIST::buildPadsFullList())

Performed tests:
- Created a blank PCB, saved as pic_programmer.kicad_pcb (from demos folder). Updated net lists. .kicad_pcb file (comparing to the results from master branch) differ with net order (as mentioned before), net codes and timestamps.
- Removed some of components from the above .kicad_pcb file and updated net lists. Modules reappeared. .kicad_pcb file differs in the same way as described above.
- Trying to change a pad net name (via properties dialog) results in assert being fired. It is done on purpose (as there is a call to GetNetname() and net name and net code do not match). This will not happen after the next commit.
- Prepared a simple project (starting with schematics). Imported net list, changed schematic, reimported net list - changes are applied.
- Eagle & KiCad legacy boards seem to load without any problem.
2014-01-10 18:04:07 +01:00
Maciej Suminski 487b609e76 Removed NETINFO_ITEM::SetNet() and NETINFO_ITEM::SetNetname() methods.
NETINFO_ITEM::m_Net and NETINFO_ITEM::m_Netname are const.

Changes to be verified:
- pcbnew/minimun_spanning_tree.cpp: It segfaults is m_Size == 0
- pcbnew/exporters/export_gencad.cpp: I removed the SetNetname() call, as it changes only the unconnected net and in the next line it returns if the net is unconnected. Still, I wonder if name for the unconnected net matters. What about tests that check if a net name is empty to decide if it is unconnected net or not.
2014-01-09 15:51:47 +01:00
jean-pierre charras 8cca89ffbe Pcbnew: read netlist enhancements: add option to remove single pads nets, add enforce tests to report non existing netnames in zones.
Fix also some very minor errors in comments.
2013-08-24 10:08:55 +02:00
Wayne Stambaugh 61b4f8a9eb Pcbnew NETLIST_READER improvements.
* Create separate NETLIST object to hold contents of netlist files.
* Read entire netlist and footprint link files before making applying
  changes to board.
* Add BOARD::ReplaceNetlist() function to eliminate the calls between the
  NETLIST_READER, PCB_EDIT_FRAME, and BOARD objects.
* Change placement of new components below the center of the current board
  or in the center of the page if the BOARD is empty.
* Add dry run option to netlist dialog to print changes to message control
  without making changes.
* Add button to netlist dialog to allow saving contents of message control
  to a file.
* Eliminate the need to compile netlist_reader_*.cpp in both CvPcb and Pcbnew.
* Add netlist_reader_*.cpp to the pcbcommon library.
* Remove redundant load component link file code from CvPcb.
* Modify CvPcb new to work with the new NETLIST_READER object.
* Add compare() function and < and == operators to FPID object.
* Add REPORTER class to hide an underlying string writing implementation for
  use in low level objects.  Thank you Dick for the idea.
* Lots of minor coding policy, Doxygen comment, and missing license fixes.
2013-04-25 12:29:35 -04:00
Dick Hollenbeck 76e21c28a4 EAGLE_PLUGIN now establishes (trace_min), (via_min_size), (via_min_drill), and Default Net's (clearance)
by groking the eagle *.brd info.  This makes it more probable that fewer DRC errors come about on first 
DRC attempt.
2013-03-14 17:54:47 -05:00
Wayne Stambaugh f8a56d446f Base object decoupling improvements.
* Improve MSG_PANEL_ITEM to handle message panel information.
* Create containers for passing message panel items between objects and
  the message panel.
* Rename EDA_ITEM::DisplayInfo to EDA_ITEM::GetMsgPanelInfo.
* Remove all direct manipulation of EDA_DRAW_FRAME from all objects derived
  from EDA_ITEM.
2013-01-12 12:32:24 -05:00
Lorenzo Marcantonio 082d901d60 Encapsulated drawmode as an enum for type checking 2012-09-01 15:38:27 +02:00
Dick Hollenbeck cb210042b8 fix bug added two revisions ago by me 2012-05-21 13:50:46 -05:00
Dick Hollenbeck 5cda6bc1a6 eagle plugin first work 2012-05-20 08:14:46 -05:00
Dick Hollenbeck 3341669fc6 more footprint support for LEGACY_PLUGIN 2012-04-16 20:35:43 -05:00
Dick Hollenbeck b8a0ab4c52 switch to <> for includes from "" per conversation with Jean-Pierre and Wayne, adjust search paths 2012-01-22 22:33:36 -06:00
jean-pierre charras 2c150e4817 All: fix compatibility issues with wxWidgets 2.9.3
Minor cosmetic enhancements.
Pcbnew: more workd abput connection algorithms (work in progress)
2011-12-17 22:21:03 +01:00
Dick Hollenbeck 4c2a1dd5d1 more kicad_plugin work, make BOARD::m_NetInfo private 2011-12-09 23:33:24 -06:00
jean-pierre charras 4221c3619a Eeschema: bug 880132 : partial fix.
Pcbnew: remove useless code.
Doc: remobe obsolete reference to MINIZIP (which do not exist now)
2011-11-11 08:00:51 +01:00
Wayne Stambaugh 4b853dedb4 Application name capitalization fixes.
* Correct all user strings and comments for the correct capitalization of
  application names according to JP.  They are KiCad, Pcbnew, CvPcb,
  Eeschema, and GerbView.
* Add a note the the user interface policy about the correct capitalization.
2011-09-30 14:15:37 -04:00
Wayne Stambaugh de96452c41 Minor common PCB library code fixes.
* More common header file compiler fixes.
* Translate French code naming and comments.
* Remove global variable ScreenPcb.
* Dead code removal.
2011-09-24 14:33:28 -04:00
jean-pierre charras 8db19bbd6a Preparing hotkeys/shortcuts changes in place menu. 2011-09-23 22:00:30 +02:00
Wayne Stambaugh edd35b4e90 PCB common library header rationalization.
* All header files used to create the PCB common library now compile as
  stand alone code.  This prevents the need to define them in a specific
  order to make source code compile properly.  It should also now be
  possible to relocate the source code to build the common PCB library
  to a separate folder.
2011-09-23 09:57:12 -04:00
Wayne Stambaugh 73e38ce98c EESchema code refactoring and coding policy naming fixes.
* Move schematic wire and bus break code into schematic screen object.
* Move schematic test for dangling ends into schematic screen object.
* Remove left over debugging output in schematic screen object.
* Remove unused file eeschema/cleanup.cpp.
* Fix bug in schematic line object hit test algorithm.
* Fix a string concatenation compile error added in r2752.
* Rename class WinEDA_BasicFrame to EDA_BASE_FRAME.
* Rename class WinEDA_DrawFrame to EDA_DRAW_FRAME.
* Rename class WinEDA_DrawPanel to EDA_DRAW_PANEL.
2011-01-21 14:30:59 -05:00
Marco Mattila e79b596308 Add FILTER_READER class. Introduce FILE_LINE_READER into pcbnew. 2011-01-14 19:43:30 +02:00
jean-pierre charras a9010796e0 Doxygen comment warning fixes. 2010-12-29 18:47:32 +01:00
Wayne Stambaugh c79077c9a2 Minor fixes and lots of coding policy changes. 2010-12-08 15:12:46 -05:00
Dick Hollenbeck 845d61acc5 coding standards consistency updates 2010-11-12 09:17:10 -06:00
charras a46cd46d9d pcbnew: More about work on color selection and items visibility:
removed global variables and a lot of redundancies
2010-01-31 20:01:46 +00:00
stambaughw 4611bfd58c Comment translations.
* Completed translation of all kicad source.
* Translated source files A through C in pcbnew.
2009-11-12 15:43:38 +00:00
charras 29e217d310 pcbnew Rewrite the GUI relative to the tracks widths and vias diameters and drills selection and edition, for compatibility with new netclass approach. 2009-10-30 17:58:15 +00:00
charras 56059efd8a Netclasses work continued
Fixed problems in libedit and crashes when no component loaded
2009-10-10 17:27:53 +00:00
dickelbeck 362b6b53f6 NETCLASS work, see CHANGELOG.txt 2009-09-10 15:22:26 +00:00
dickelbeck 85dc98a58a more netclass work 2009-08-17 02:59:38 +00:00
dickelbeck 5c3f35c2f3 beautification in preparation for netclass work. 2009-08-10 02:22:56 +00:00