489 lines
15 KiB
C++
489 lines
15 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2019 Jean-Pierre Charras, jp.charras at wanadoo.fr
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* Copyright (C) 2009-2019 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 3
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "class_board_stackup.h"
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#include <convert_to_biu.h>
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#include <base_units.h>
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#include <layers_id_colors_and_visibility.h>
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#include <board_design_settings.h>
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#include <class_board.h>
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#include <i18n_utility.h> // For _HKI definition
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#include "stackup_predefined_prms.h"
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// A reasonable thickness for copper layers:
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const int copperDefaultThickness = Millimeter2iu( 0.035 );
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// A reasonable thickness for solder mask:
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const int maskDefaultThickness = Millimeter2iu( 0.01 );
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BOARD_STACKUP_ITEM::BOARD_STACKUP_ITEM( BOARD_STACKUP_ITEM_TYPE aType )
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{
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m_LayerId = UNDEFINED_LAYER;
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m_Type = aType;
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m_DielectricLayerId = 0;
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m_EpsilonR = 0;
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m_LossTangent = 0.0;
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// Initialize parameters to a usual value for allowed types:
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switch( m_Type )
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{
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case BS_ITEM_TYPE_COPPER:
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m_TypeName = "copper";
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m_Thickness = copperDefaultThickness;
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break;
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case BS_ITEM_TYPE_DIELECTRIC:
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m_TypeName = "core"; // or prepreg
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m_Material = "FR4"; // or other dielectric name
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m_DielectricLayerId = 1;
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m_Thickness = 0; // will be set later
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m_LossTangent = 0.02; // for FR4
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m_EpsilonR = 4.5; // for FR4
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break;
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case BS_ITEM_TYPE_SOLDERPASTE:
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m_TypeName = "solderpaste";
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m_Thickness = 0.0; // Not used
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break;
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case BS_ITEM_TYPE_SOLDERMASK:
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m_TypeName = "soldermask";
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m_Color = NOT_SPECIFIED;
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m_Thickness = maskDefaultThickness;
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m_EpsilonR = 3.5;
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m_LossTangent = 0.0;
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break;
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case BS_ITEM_TYPE_SILKSCREEN:
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m_TypeName = "silkscreen";
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m_Color = NOT_SPECIFIED;
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m_Thickness = 0.0; // Not used
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break;
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case BS_ITEM_TYPE_UNDEFINED:
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m_Thickness = 0.0;
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break;
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}
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}
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BOARD_STACKUP_ITEM::BOARD_STACKUP_ITEM( BOARD_STACKUP_ITEM& aOther )
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{
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m_LayerId = aOther.m_LayerId;
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m_Type = aOther.m_Type;
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m_DielectricLayerId = aOther.m_DielectricLayerId;
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m_TypeName = aOther.m_TypeName;
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m_Material = aOther.m_Material;
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m_Color = aOther.m_Color;
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m_Thickness = aOther.m_Thickness;
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m_EpsilonR = aOther.m_EpsilonR;
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m_LossTangent = aOther.m_LossTangent;
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}
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bool BOARD_STACKUP_ITEM::HasEpsilonRValue()
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{
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return m_Type == BS_ITEM_TYPE_DIELECTRIC || m_Type == BS_ITEM_TYPE_SOLDERMASK;
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};
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bool BOARD_STACKUP_ITEM::HasLossTangentValue()
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{
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return m_Type == BS_ITEM_TYPE_DIELECTRIC || m_Type == BS_ITEM_TYPE_SOLDERMASK;
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};
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bool BOARD_STACKUP_ITEM::IsMaterialEditable()
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{
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// The material is editable only for dielectric
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return m_Type == BS_ITEM_TYPE_DIELECTRIC;
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}
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bool BOARD_STACKUP_ITEM::IsColorEditable()
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{
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return m_Type == BS_ITEM_TYPE_SOLDERMASK || m_Type == BS_ITEM_TYPE_SILKSCREEN;
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}
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bool BOARD_STACKUP_ITEM::IsThicknessEditable()
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{
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switch( m_Type )
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{
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case BS_ITEM_TYPE_COPPER:
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return true;
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case BS_ITEM_TYPE_DIELECTRIC:
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return true;
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case BS_ITEM_TYPE_SOLDERMASK:
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return true;
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case BS_ITEM_TYPE_SOLDERPASTE:
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return false;
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case BS_ITEM_TYPE_SILKSCREEN:
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return false;
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default:
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break;
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}
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return false;
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}
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BOARD_STACKUP::BOARD_STACKUP()
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{
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m_HasDielectricConstrains = false; // True if some dielectric layers have constrains
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// (Loss tg and Epison R)
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m_HasThicknessConstrains = false; // True if some dielectric or copper layers have constrains
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m_EdgeConnectorConstraints = BS_EDGE_CONNECTOR_NONE;
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m_CastellatedPads = false; // True if some castellated pads exist
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m_EdgePlating = false; // True if edge board is plated
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m_FinishType = "None"; // undefined finish type
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}
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BOARD_STACKUP::BOARD_STACKUP( BOARD_STACKUP& aOther )
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{
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m_HasDielectricConstrains = aOther.m_HasDielectricConstrains;
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m_EdgeConnectorConstraints = aOther.m_EdgeConnectorConstraints;
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m_CastellatedPads = aOther.m_CastellatedPads;
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m_EdgePlating = aOther.m_EdgePlating;
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m_FinishType = aOther.m_FinishType;
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// All items in aOther.m_list have to be duplicated, because aOther.m_list
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// manage pointers to these items
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for( auto item : aOther.m_list )
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{
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BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
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Add( dup_item );
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}
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}
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BOARD_STACKUP& BOARD_STACKUP::operator=( const BOARD_STACKUP& aOther )
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{
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m_HasDielectricConstrains = aOther.m_HasDielectricConstrains;
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m_EdgeConnectorConstraints = aOther.m_EdgeConnectorConstraints;
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m_CastellatedPads = aOther.m_CastellatedPads;
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m_EdgePlating = aOther.m_EdgePlating;
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m_FinishType = aOther.m_FinishType;
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RemoveAll();
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// All items in aOther.m_list have to be duplicated, because aOther.m_list
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// manage pointers to these items
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for( auto item : aOther.m_list )
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{
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BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
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Add( dup_item );
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}
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return *this;
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}
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void BOARD_STACKUP::RemoveAll()
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{
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for( auto item : m_list )
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delete item;
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m_list.clear();
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}
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BOARD_STACKUP_ITEM* BOARD_STACKUP::GetStackupLayer( int aIndex )
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{
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if( aIndex < 0 || aIndex >= GetCount() )
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return nullptr;
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return GetList()[aIndex];
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}
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int BOARD_STACKUP::BuildBoardTicknessFromStackup() const
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{
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// return the board thickness from the thickness of BOARD_STACKUP_ITEM list
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int thickness = 0;
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for( auto item : m_list )
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{
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if( item->IsThicknessEditable() )
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thickness += item->m_Thickness;
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}
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return thickness;
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}
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bool BOARD_STACKUP::SynchronizeWithBoard( BOARD_DESIGN_SETTINGS* aSettings )
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{
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bool change = false;
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// Build the suitable stackup:
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BOARD_STACKUP stackup;
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stackup.BuildDefaultStackupList( aSettings );
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// First test for removed layers:
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for( BOARD_STACKUP_ITEM* old_item: m_list )
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{
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bool found = false;
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for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
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{
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if( item->m_LayerId == old_item->m_LayerId )
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{
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found = true;
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break;
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}
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}
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if( !found ) // a layer was removed: a change is found
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{
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change = true;
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break;
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}
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}
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// Now initialize all stackup items to the initial values, when exist
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for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
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{
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bool found = false;
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// Search for initial settings:
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for( BOARD_STACKUP_ITEM* initial_item: m_list )
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{
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if( item->m_LayerId != UNDEFINED_LAYER )
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{
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if( item->m_LayerId == initial_item->m_LayerId )
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{
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*item = *initial_item;
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found = true;
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break;
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}
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}
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else // dielectric layer: see m_DielectricLayerId for identification
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{
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if( item->m_DielectricLayerId == initial_item->m_DielectricLayerId )
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{
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*item = *initial_item;
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found = true;
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break;
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}
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}
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}
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if( !found )
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change = true;
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}
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// Transfer other stackup settings from aSettings
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BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
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m_HasDielectricConstrains = source_stackup.m_HasDielectricConstrains;
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m_EdgeConnectorConstraints = source_stackup.m_EdgeConnectorConstraints;
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m_CastellatedPads = source_stackup.m_CastellatedPads;
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m_EdgePlating = source_stackup.m_EdgePlating;
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m_FinishType = source_stackup.m_FinishType;
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*this = stackup;
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return change;
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}
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void BOARD_STACKUP::BuildDefaultStackupList( BOARD_DESIGN_SETTINGS* aSettings )
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{
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// Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.
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// Note: the m_TypeName string is made translatable using _HKI marker, but is not
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// translated when building the stackup.
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// It will be used as this in files, and can be translated only in dialog
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LSET enabledLayer = aSettings->GetEnabledLayers();
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int copperLayerCount = aSettings->GetCopperLayerCount();
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double diel_thickness = aSettings->GetBoardThickness()
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- (copperDefaultThickness * copperLayerCount);
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diel_thickness /= copperLayerCount - 1;
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int dielectric_idx = 0;
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// Add silk screen, solder mask and solder paste layers on top
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if( enabledLayer[F_SilkS] )
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{
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BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SILKSCREEN );
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item->m_LayerId = F_SilkS;
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item->m_TypeName = _HKI( "Top Silk Screen" );
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Add( item );
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}
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if( enabledLayer[F_Paste] )
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{
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BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SOLDERPASTE );
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item->m_LayerId = F_Paste;
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item->m_TypeName = _HKI( "Top Solder Paste" );
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Add( item );
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}
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if( enabledLayer[F_Mask] )
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{
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BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SOLDERMASK );
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item->m_LayerId = F_Mask;
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item->m_TypeName = _HKI( "Top Solder Mask" );
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Add( item );
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}
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// Add copper and dielectric layers
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for( int ii = 0; ii < copperLayerCount; ii++ )
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{
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BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_COPPER );
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item->m_LayerId = ( PCB_LAYER_ID )ii;
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Add( item );
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if( ii == copperLayerCount-1 )
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{
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item->m_LayerId = B_Cu;
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break;
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}
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// Add the dielectric layer:
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item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_DIELECTRIC );
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item->m_Thickness = diel_thickness;
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item->m_DielectricLayerId = dielectric_idx + 1;
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// Display a dielectric default layer name:
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if( (dielectric_idx & 1) == 0 )
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{
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item->m_TypeName = _HKI( "core" );
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item->m_Material = "FR4";
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}
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else
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{
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item->m_TypeName = _HKI( "prepreg" );
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item->m_Material = "FR4";
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}
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Add( item );
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dielectric_idx++;
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}
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// Add silk screen, solder mask and solder paste layers on bottom
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if( enabledLayer[B_Mask] )
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{
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BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SOLDERMASK );
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item->m_LayerId = B_Mask;
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item->m_TypeName = _HKI( "Bottom Solder Mask" );
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Add( item );
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}
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if( enabledLayer[B_Paste] )
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{
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BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SOLDERPASTE );
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item->m_LayerId = B_Paste;
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item->m_TypeName = _HKI( "Bottom Solder Paste" );
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Add( item );
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}
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if( enabledLayer[B_SilkS] )
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{
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BOARD_STACKUP_ITEM* item = new BOARD_STACKUP_ITEM( BS_ITEM_TYPE_SILKSCREEN );
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item->m_LayerId = B_SilkS;
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item->m_TypeName = _HKI( "Bottom Silk Screen" );
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Add( item );
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}
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// Transfer other stackup settings from aSettings
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BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
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m_HasDielectricConstrains = source_stackup.m_HasDielectricConstrains;
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m_EdgeConnectorConstraints = source_stackup.m_EdgeConnectorConstraints;
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m_CastellatedPads = source_stackup.m_CastellatedPads;
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m_EdgePlating = source_stackup.m_EdgePlating;
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m_FinishType = source_stackup.m_FinishType;
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}
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void BOARD_STACKUP::FormatBoardStackup( OUTPUTFORMATTER* aFormatter,
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BOARD* aBoard, int aNestLevel ) const
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{
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// Board stackup is the ordered list from top to bottom of
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// physical layers and substrate used to build the board.
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if( m_list.empty() )
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return;
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aFormatter->Print( aNestLevel, "(board_stackup\n" );
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int nest_level = aNestLevel+1;
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for( BOARD_STACKUP_ITEM* item: m_list )
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{
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wxString layer_name;
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if( item->m_LayerId == UNDEFINED_LAYER )
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{
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layer_name.Printf( "dielectric %d", item->m_DielectricLayerId );
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}
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else
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layer_name = aBoard->GetLayerName( item->m_LayerId );
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aFormatter->Print( nest_level, "(layer %s (type %s)",
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aFormatter->Quotew( layer_name ).c_str(),
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aFormatter->Quotew( item->m_TypeName ).c_str() );
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if( item->IsThicknessEditable() )
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aFormatter->Print( 0, " (thickness %s)",
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FormatInternalUnits( (int)item->m_Thickness ).c_str() );
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if( item->m_Type == BS_ITEM_TYPE_DIELECTRIC )
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aFormatter->Print( 0, " (material %s)",
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aFormatter->Quotew( item->m_Material ).c_str() );
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if( item->HasEpsilonRValue() )
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aFormatter->Print( 0, " (epsilon_r %g)", item->m_EpsilonR );
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if( item->HasLossTangentValue() )
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aFormatter->Print( 0, " (loss %s)",
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Double2Str(item->m_LossTangent ).c_str() );
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if( item->IsColorEditable() && !item->m_Color.IsEmpty()
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&& item->m_Color != NOT_SPECIFIED )
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aFormatter->Print( 0, " (color %s)",
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aFormatter->Quotew( item->m_Color ).c_str() );
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aFormatter->Print( 0, ")\n" );
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}
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// Other infos about board, related to layers and other fabrication specifications
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if( !m_FinishType.IsEmpty() && m_FinishType != NOT_SPECIFIED )
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aFormatter->Print( nest_level, "(copper_finish %s)\n",
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aFormatter->Quotew( m_FinishType ).c_str() );
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aFormatter->Print( nest_level, "(dielectric_constrains %s)\n",
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m_HasDielectricConstrains ? "yes" : "no" );
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if( m_EdgeConnectorConstraints > 0 )
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aFormatter->Print( nest_level, "(edge_connector %s)\n",
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m_EdgeConnectorConstraints > 1 ? "bevelled": "yes" );
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if( m_CastellatedPads )
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aFormatter->Print( nest_level, "(castellated_pads yes)\n" );
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if( m_EdgePlating )
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aFormatter->Print( nest_level, "(edge_plating yes)\n" );
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aFormatter->Print( aNestLevel, ")\n" );
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}
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