kicad/pcbnew/dialogs/panel_setup_rules_help.md at d25fe17b28587e066e80e35dc5d528c22a12dc38

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Top-level Clauses

(version <number>)

(rule <rule_name> <rule_clause> ...)

Rule Clauses

(constraint <constraint_type> ...)

(condition "<expression>")

(layer "<layer_name>")

(severity <severity_name>)

Constraint Types

annular_width
clearance
courtyard_clearance
diff_pair_gap
diff_pair_uncoupled
disallow
edge_clearance
length
hole_clearance
hole_size
mechanical_clearance
mechanical_hole_clearance
min_resolved_spokes
silk_clearance
skew
text_height
text_thickness
thermal_relief_gap
thermal_spoke_width
track_width
via_count
via_diameter
zone_connection

Note: clearance and hole_clearance rules are not run against items of the same net; mechanical_clearance and mechanical_hole_clearance rules are.

Item Types

buried_via
graphic
hole
micro_via
pad
text
track
via
zone

Zone Connections

solid
thermal_reliefs
none

Severity Names

warning
error
exclusion
ignore

Examples

(version 1)

(rule HV
   (constraint clearance (min 1.5mm))
   (condition "A.NetClass == 'HV'"))


(rule HV
   (layer outer)
   (constraint clearance (min 1.5mm))
   (condition "A.NetClass == 'HV'"))


(rule HV_HV
   # wider clearance between HV tracks
   (constraint clearance (min "1.5mm + 2.0mm"))
   (condition "A.NetClass == 'HV' && B.NetClass == 'HV'"))


(rule HV_unshielded
   (constraint clearance (min 2mm))
   (condition "A.NetClass == 'HV' && !A.insideArea('Shield*')"))


(rule heavy_thermals
   (constraint thermal_spoke_width (min 0.5mm))
   (condition "A.NetClass == 'HV'"))

Notes

Version clause must be the first clause. It indicates the syntax version of the file so that future rules parsers can perform automatic updates. It should be set to "1".

Rules should be ordered by specificity. Later rules take precedence over earlier rules; once a matching rule is found no further rules will be checked.

Use Ctrl+/ to comment or uncomment line(s).

Expression functions

All function parameters support simple wildcards (* and ?).

A.insideCourtyard('<footprint_refdes>')

True if any part of A lies within the given footprint's principal courtyard.

A.insideFrontCourtyard('<footprint_refdes>')

True if any part of A lies within the given footprint's front courtyard.

A.insideBackCourtyard('<footprint_refdes>')

True if any part of A lies within the given footprint's back courtyard.

A.insideArea('<zone_name>')

True if any part of A lies within the given zone's outline.

A.isPlated()

True if A has a hole which is plated.

A.inDiffPair('<net_name>')

True if A has net that is part of the specified differential pair. <net_name> is the base name of the differential pair. For example, inDiffPair('CLK') matches items in the CLK_P and CLK_N nets.

AB.isCoupledDiffPair()

True if A and B are members of the same diff pair.

A.memberOf('<group_name>')

True if A is a member of the given group. Includes nested membership.

A.existsOnLayer('<layer_name>')

True if A exists on the given layer. The layer name can be either the name assigned in Board Setup > Board Editor Layers or the canonical name (ie: F.Cu).

NB: this returns true if A is on the given layer, independently of whether or not the rule is being evaluated for that layer. For the latter use a (layer "layer_name") clause in the rule.

More Examples

(rule "copper keepout"
   (constraint disallow track via zone)
   (condition "A.insideArea('zone3')"))


(rule "BGA neckdown"
   (constraint track_width (min 0.2mm) (opt 0.25mm))
   (constraint clearance (min 0.05mm) (opt 0.08mm))
   (condition "A.insideCourtyard('U3')"))


# prevent silk over tented vias
(rule silk_over_via
   (constraint silk_clearance (min 0.2mm))
   (condition "A.Type == '*Text' && B.Type == 'Via'"))


(rule "Distance between Vias of Different Nets"  
    (constraint hole_to_hole (min 0.254mm))
    (condition "A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net"))

(rule "Clearance between Pads of Different Nets"  
    (constraint clearance (min 3.0mm))
    (condition "A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net"))


(rule "Via Hole to Track Clearance"  
    (constraint hole_clearance (min 0.254mm))
    (condition "A.Type == 'Via' && B.Type == 'Track'"))

(rule "Pad to Track Clearance"  
    (constraint clearance (min 0.2mm))
    (condition "A.Type == 'Pad' && B.Type == 'Track'"))


(rule "clearance-to-1mm-cutout"
    (constraint clearance (min 0.8mm))
    (condition "A.Layer == 'Edge.Cuts' && A.Thickness == 1.0mm"))


(rule "Max Drill Hole Size Mechanical"  
    (constraint hole_size (max 6.3mm))
    (condition "A.Pad_Type == 'NPTH, mechanical'"))

(rule "Max Drill Hole Size PTH"  
    (constraint hole_size (max 6.35mm))
    (condition "A.Pad_Type == 'Through-hole'"))


# Specify an optimal gap for a particular diff-pair
(rule "dp clock gap"
    (constraint diff_pair_gap (opt "0.8mm"))
    (condition "A.inDiffPair('CLK') && AB.isCoupledDiffPair()"))

# Specify a larger clearance around any diff-pair
(rule "dp clearance"
    (constraint clearance (min "1.5mm"))
    (condition "A.inDiffPair('*') && !AB.isCoupledDiffPair()"))


# Don't use thermal reliefs on heatsink pads
(rule heat_sink_pad
    (constraint zone_connection solid)
    (condition "A.Fabrication_Property == 'Heatsink pad'"))

# Require all four thermal relief spokes to connect to parent zone
(rule fully_spoked_pads
    (constraint min_resolved_spokes 4))

# Prevent solder wicking from SMD pads
(rule holes_in_pads
    (constraint mechanical_hole_clearance (min 0.2mm))
    (condition "B.Pad_Type == 'SMD'"))


# Disallow solder mask margin overrides
(rule "disallow solder mask margin overrides"
    (constraint assertion "A.Soldermask_Margin_Override == 0mm")
    (condition "A.Type == 'Pad'"))

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