Initial commit
This commit is contained in:
commit
eebf2d6093
|
@ -0,0 +1,17 @@
|
|||
name: docs
|
||||
|
||||
on:
|
||||
push:
|
||||
workflow_dispatch:
|
||||
|
||||
jobs:
|
||||
docs:
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- name: Checkout repo
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
submodules: recursive
|
||||
|
||||
- name: Build docs
|
||||
uses: TinyTapeout/tt-gds-action/docs@tt07
|
|
@ -0,0 +1,17 @@
|
|||
name: fpga
|
||||
|
||||
on:
|
||||
push:
|
||||
workflow_dispatch:
|
||||
|
||||
jobs:
|
||||
fpga:
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- name: checkout repo
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
submodules: recursive
|
||||
|
||||
- name: FPGA bitstream for TT ASIC Sim (ICE40UP5K)
|
||||
uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt07
|
|
@ -0,0 +1,45 @@
|
|||
name: gds
|
||||
|
||||
on:
|
||||
push:
|
||||
workflow_dispatch:
|
||||
|
||||
jobs:
|
||||
gds:
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- name: checkout repo
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
submodules: recursive
|
||||
|
||||
- name: Build GDS
|
||||
uses: TinyTapeout/tt-gds-action@tt07
|
||||
|
||||
precheck:
|
||||
needs: gds
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- name: Run Tiny Tapeout Precheck
|
||||
uses: TinyTapeout/tt-gds-action/precheck@tt07
|
||||
|
||||
gl_test:
|
||||
needs: gds
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- name: checkout repo
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
submodules: recursive
|
||||
|
||||
- name: GL test
|
||||
uses: TinyTapeout/tt-gds-action/gl_test@tt07
|
||||
|
||||
viewer:
|
||||
needs: gds
|
||||
runs-on: ubuntu-latest
|
||||
permissions:
|
||||
pages: write # to deploy to Pages
|
||||
id-token: write # to verify the deployment originates from an appropriate source
|
||||
steps:
|
||||
- uses: TinyTapeout/tt-gds-action/viewer@tt07
|
|
@ -0,0 +1,47 @@
|
|||
name: test
|
||||
on: [push, workflow_dispatch]
|
||||
jobs:
|
||||
test:
|
||||
runs-on: ubuntu-latest
|
||||
steps:
|
||||
- name: Checkout repo
|
||||
uses: actions/checkout@v4
|
||||
with:
|
||||
submodules: recursive
|
||||
|
||||
- name: Install iverilog
|
||||
shell: bash
|
||||
run: sudo apt-get update && sudo apt-get install -y iverilog
|
||||
|
||||
# Set Python up and install cocotb
|
||||
- name: Setup python
|
||||
uses: actions/setup-python@v5
|
||||
with:
|
||||
python-version: '3.11'
|
||||
|
||||
- name: Install Python packages
|
||||
shell: bash
|
||||
run: pip install -r test/requirements.txt
|
||||
|
||||
- name: Run tests
|
||||
run: |
|
||||
cd test
|
||||
make clean
|
||||
make
|
||||
# make will return success even if the test fails, so check for failure in the results.xml
|
||||
! grep failure results.xml
|
||||
|
||||
- name: Test Summary
|
||||
uses: test-summary/action@v2.3
|
||||
with:
|
||||
paths: "test/results.xml"
|
||||
if: always()
|
||||
|
||||
- name: upload vcd
|
||||
if: success() || failure()
|
||||
uses: actions/upload-artifact@v4
|
||||
with:
|
||||
name: test-vcd
|
||||
path: |
|
||||
test/tb.vcd
|
||||
test/result.xml
|
|
@ -0,0 +1,11 @@
|
|||
.DS_Store
|
||||
.idea
|
||||
.vscode
|
||||
*.vcd
|
||||
runs
|
||||
tt_submission
|
||||
src/user_config.tcl
|
||||
test/sim_build
|
||||
test/__pycache__/
|
||||
test/results.xml
|
||||
test/gate_level_netlist.v
|
|
@ -0,0 +1,201 @@
|
|||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction,
|
||||
and distribution as defined by Sections 1 through 9 of this document.
|
||||
|
||||
"Licensor" shall mean the copyright owner or entity authorized by
|
||||
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||||
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||||
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|
||||
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|
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||||
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|
||||
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|
||||
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|
||||
|
||||
"You" (or "Your") shall mean an individual or Legal Entity
|
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|
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|
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Notwithstanding the above, nothing herein shall supersede or modify
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|
||||
END OF TERMS AND CONDITIONS
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||||
|
||||
APPENDIX: How to apply the Apache License to your work.
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||||
|
||||
To apply the Apache License to your work, attach the following
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||||
Copyright [yyyy] [name of copyright owner]
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||||
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you may not use this file except in compliance with the License.
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||||
You may obtain a copy of the License at
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||||
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Unless required by applicable law or agreed to in writing, software
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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|
@ -0,0 +1,41 @@
|
|||
![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg)
|
||||
|
||||
# Tiny Tapeout Verilog Project Template
|
||||
|
||||
- [Read the documentation for project](docs/info.md)
|
||||
|
||||
## What is Tiny Tapeout?
|
||||
|
||||
Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.
|
||||
|
||||
To learn more and get started, visit https://tinytapeout.com.
|
||||
|
||||
## Set up your Verilog project
|
||||
|
||||
1. Add your Verilog files to the `src` folder.
|
||||
2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/).
|
||||
3. Edit [docs/info.md](docs/info.md) and add a description of your project.
|
||||
4. Adapt the testbench to your design. See [test/README.md](test/README.md) for more information.
|
||||
|
||||
The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/).
|
||||
|
||||
## Enable GitHub actions to build the results page
|
||||
|
||||
- [Enabling GitHub Pages](https://tinytapeout.com/faq/#my-github-action-is-failing-on-the-pages-part)
|
||||
|
||||
## Resources
|
||||
|
||||
- [FAQ](https://tinytapeout.com/faq/)
|
||||
- [Digital design lessons](https://tinytapeout.com/digital_design/)
|
||||
- [Learn how semiconductors work](https://tinytapeout.com/siliwiz/)
|
||||
- [Join the community](https://tinytapeout.com/discord)
|
||||
- [Build your design locally](https://docs.google.com/document/d/1aUUZ1jthRpg4QURIIyzlOaPWlmQzr-jBn3wZipVUPt4)
|
||||
|
||||
## What next?
|
||||
|
||||
- [Submit your design to the next shuttle](https://app.tinytapeout.com/).
|
||||
- Edit [this README](README.md) and explain your design, how it works, and how to test it.
|
||||
- Share your project on your social network of choice:
|
||||
- LinkedIn [#tinytapeout](https://www.linkedin.com/search/results/content/?keywords=%23tinytapeout) [@TinyTapeout](https://www.linkedin.com/company/100708654/)
|
||||
- Mastodon [#tinytapeout](https://chaos.social/tags/tinytapeout) [@matthewvenn](https://chaos.social/@matthewvenn)
|
||||
- X (formerly Twitter) [#tinytapeout](https://twitter.com/hashtag/tinytapeout) [@tinytapeout](https://twitter.com/tinytapeout)
|
|
@ -0,0 +1,20 @@
|
|||
<!---
|
||||
|
||||
This file is used to generate your project datasheet. Please fill in the information below and delete any unused
|
||||
sections.
|
||||
|
||||
You can also include images in this folder and reference them in the markdown. Each image must be less than
|
||||
512 kb in size, and the combined size of all images must be less than 1 MB.
|
||||
-->
|
||||
|
||||
## How it works
|
||||
|
||||
Explain how your project works
|
||||
|
||||
## How to test
|
||||
|
||||
Explain how to use your project
|
||||
|
||||
## External hardware
|
||||
|
||||
List external hardware used in your project (e.g. PMOD, LED display, etc), if any
|
|
@ -0,0 +1,53 @@
|
|||
# Tiny Tapeout project information
|
||||
project:
|
||||
title: "" # Project title
|
||||
author: "" # Your name
|
||||
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
|
||||
description: "" # One line description of what your project does
|
||||
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
|
||||
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)
|
||||
|
||||
# How many tiles your design occupies? A single tile is about 167x108 uM.
|
||||
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
|
||||
|
||||
# Your top module name must start with "tt_um_". Make it unique by including your github username:
|
||||
top_module: "tt_um_example"
|
||||
|
||||
# List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
|
||||
source_files:
|
||||
- "project.v"
|
||||
|
||||
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
|
||||
pinout:
|
||||
# Inputs
|
||||
ui[0]: ""
|
||||
ui[1]: ""
|
||||
ui[2]: ""
|
||||
ui[3]: ""
|
||||
ui[4]: ""
|
||||
ui[5]: ""
|
||||
ui[6]: ""
|
||||
ui[7]: ""
|
||||
|
||||
# Outputs
|
||||
uo[0]: ""
|
||||
uo[1]: ""
|
||||
uo[2]: ""
|
||||
uo[3]: ""
|
||||
uo[4]: ""
|
||||
uo[5]: ""
|
||||
uo[6]: ""
|
||||
uo[7]: ""
|
||||
|
||||
# Bidirectional pins
|
||||
uio[0]: ""
|
||||
uio[1]: ""
|
||||
uio[2]: ""
|
||||
uio[3]: ""
|
||||
uio[4]: ""
|
||||
uio[5]: ""
|
||||
uio[6]: ""
|
||||
uio[7]: ""
|
||||
|
||||
# Do not change!
|
||||
yaml_version: 6
|
|
@ -0,0 +1,84 @@
|
|||
# DO NOT EDIT THIS FILE before reading the comments below:
|
||||
|
||||
# This is the default configuration for Tiny Tapeout projects. It should fit most designs.
|
||||
# If you change it, please make sure you understand what you are doing. We are not responsible
|
||||
# if your project fails because of a bad configuration.
|
||||
|
||||
# !!! DO NOT EDIT THIS FILE unless you know what you are doing !!!
|
||||
|
||||
# If you get stuck with this config, please open an issue or get in touch via the discord.
|
||||
|
||||
# Here are some of the variables you may want to change:
|
||||
|
||||
# PL_TARGET_DENSITY - You can increase this if Global Placement fails with error GPL-0302.
|
||||
# Users have reported that values up to 0.8 worked well for them.
|
||||
set ::env(PL_TARGET_DENSITY) 0.6
|
||||
|
||||
# CLOCK_PERIOD - Increase this in case you are getting setup time violations.
|
||||
# The value is in nanoseconds, so 20ns == 50MHz.
|
||||
set ::env(CLOCK_PERIOD) "20"
|
||||
|
||||
# Hold slack margin - Increase them in case you are getting hold violations.
|
||||
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.1
|
||||
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.05
|
||||
|
||||
# RUN_LINTER, LINTER_INCLUDE_PDK_MODELS - Disabling the linter is not recommended!
|
||||
set ::env(RUN_LINTER) 1
|
||||
set ::env(LINTER_INCLUDE_PDK_MODELS) 1
|
||||
|
||||
# If you need a custom clock configuration, read the following documentation first:
|
||||
# https://tinytapeout.com/faq/#how-can-i-map-an-additional-external-clock-to-one-of-the-gpios
|
||||
set ::env(CLOCK_PORT) {clk}
|
||||
|
||||
# Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html
|
||||
|
||||
# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
# !!! DO NOT CHANGE ANYTHING BELOW THIS POINT !!!
|
||||
# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
|
||||
|
||||
# Load configuration auto-generated by tt-support-tools
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
source $::env(DESIGN_DIR)/user_config.tcl
|
||||
|
||||
# Save some time
|
||||
set ::env(RUN_KLAYOUT_XOR) 0
|
||||
set ::env(RUN_KLAYOUT_DRC) 0
|
||||
|
||||
# Don't put clock buffers on the outputs
|
||||
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
|
||||
|
||||
# Allow use of specific sky130 cells
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
|
||||
|
||||
# Reduce wasted space
|
||||
set ::env(TOP_MARGIN_MULT) 1
|
||||
set ::env(BOTTOM_MARGIN_MULT) 1
|
||||
set ::env(LEFT_MARGIN_MULT) 6
|
||||
set ::env(RIGHT_MARGIN_MULT) 6
|
||||
|
||||
# Absolute die size
|
||||
set ::env(FP_SIZING) absolute
|
||||
|
||||
set ::env(PL_BASIC_PLACEMENT) {0}
|
||||
set ::env(GRT_ALLOW_CONGESTION) "1"
|
||||
|
||||
set ::env(FP_IO_HLENGTH) 2
|
||||
set ::env(FP_IO_VLENGTH) 2
|
||||
|
||||
# Use alternative efabless decap cells to solve LI density issue
|
||||
set ::env(DECAP_CELL) "\
|
||||
sky130_fd_sc_hd__decap_3 \
|
||||
sky130_fd_sc_hd__decap_4 \
|
||||
sky130_fd_sc_hd__decap_6 \
|
||||
sky130_fd_sc_hd__decap_8 \
|
||||
sky130_ef_sc_hd__decap_12"
|
||||
|
||||
# Clock
|
||||
set ::env(RUN_CTS) 1
|
||||
|
||||
# Don't use power rings or met5 layer
|
||||
set ::env(DESIGN_IS_CORE) 0
|
||||
set ::env(RT_MAX_LAYER) {met4}
|
||||
|
||||
# MAGIC_DEF_LABELS may cause issues with LVS
|
||||
set ::env(MAGIC_DEF_LABELS) 0
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Your Name
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module tt_um_example (
|
||||
input wire [7:0] ui_in, // Dedicated inputs
|
||||
output wire [7:0] uo_out, // Dedicated outputs
|
||||
input wire [7:0] uio_in, // IOs: Input path
|
||||
output wire [7:0] uio_out, // IOs: Output path
|
||||
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
|
||||
input wire ena, // always 1 when the design is powered, so you can ignore it
|
||||
input wire clk, // clock
|
||||
input wire rst_n // reset_n - low to reset
|
||||
);
|
||||
|
||||
// All output pins must be assigned. If not used, assign to 0.
|
||||
assign uo_out = ui_in + uio_in; // Example: ou_out is the sum of ui_in and uio_in
|
||||
assign uio_out = 0;
|
||||
assign uio_oe = 0;
|
||||
|
||||
endmodule
|
|
@ -0,0 +1,42 @@
|
|||
# Makefile
|
||||
# See https://docs.cocotb.org/en/stable/quickstart.html for more info
|
||||
|
||||
# defaults
|
||||
SIM ?= icarus
|
||||
TOPLEVEL_LANG ?= verilog
|
||||
SRC_DIR = $(PWD)/../src
|
||||
PROJECT_SOURCES = project.v
|
||||
|
||||
ifneq ($(GATES),yes)
|
||||
|
||||
# RTL simulation:
|
||||
SIM_BUILD = sim_build/rtl
|
||||
VERILOG_SOURCES += $(addprefix $(SRC_DIR)/,$(PROJECT_SOURCES))
|
||||
COMPILE_ARGS += -I$(SRC_DIR)
|
||||
|
||||
else
|
||||
|
||||
# Gate level simulation:
|
||||
SIM_BUILD = sim_build/gl
|
||||
COMPILE_ARGS += -DGL_TEST
|
||||
COMPILE_ARGS += -DFUNCTIONAL
|
||||
COMPILE_ARGS += -DUSE_POWER_PINS
|
||||
COMPILE_ARGS += -DSIM
|
||||
COMPILE_ARGS += -DUNIT_DELAY=\#1
|
||||
VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
|
||||
VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
|
||||
|
||||
# this gets copied in by the GDS action workflow
|
||||
VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
|
||||
|
||||
endif
|
||||
|
||||
# Include the testbench sources:
|
||||
VERILOG_SOURCES += $(PWD)/tb.v
|
||||
TOPLEVEL = tb
|
||||
|
||||
# MODULE is the basename of the Python test file
|
||||
MODULE = test
|
||||
|
||||
# include cocotb's make rules to take care of the simulator setup
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
|
@ -0,0 +1,31 @@
|
|||
# Sample testbench for a Tiny Tapeout project
|
||||
|
||||
This is a sample testbench for a Tiny Tapeout project. It uses [cocotb](https://docs.cocotb.org/en/stable/) to drive the DUT and check the outputs.
|
||||
See below to get started or for more information, check the [website](https://tinytapeout.com/hdl/testing/).
|
||||
|
||||
## Setting up
|
||||
|
||||
1. Edit [Makefile](Makefile) and modify `PROJECT_SOURCES` to point to your Verilog files.
|
||||
2. Edit [tb.v](tb.v) and replace `tt_um_example` with your module name.
|
||||
|
||||
## How to run
|
||||
|
||||
To run the RTL simulation:
|
||||
|
||||
```sh
|
||||
make -B
|
||||
```
|
||||
|
||||
To run gatelevel simulation, first harden your project and copy `../runs/wokwi/results/final/verilog/gl/{your_module_name}.v` to `gate_level_netlist.v`.
|
||||
|
||||
Then run:
|
||||
|
||||
```sh
|
||||
make -B GATES=yes
|
||||
```
|
||||
|
||||
## How to view the VCD file
|
||||
|
||||
```sh
|
||||
gtkwave tb.vcd tb.gtkw
|
||||
```
|
|
@ -0,0 +1,2 @@
|
|||
pytest==8.1.1
|
||||
cocotb==1.8.1
|
|
@ -0,0 +1,39 @@
|
|||
[*]
|
||||
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
|
||||
[*] Mon Nov 20 16:00:28 2023
|
||||
[*]
|
||||
[dumpfile] "/home/uri/p/tt-new-template-proto/test/tb.vcd"
|
||||
[dumpfile_mtime] "Mon Nov 20 15:58:34 2023"
|
||||
[dumpfile_size] 1110
|
||||
[savefile] "/home/uri/p/tt-new-template-proto/test/tb.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1376 600
|
||||
[pos] -1 -1
|
||||
*-24.534533 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] tb.
|
||||
[sst_width] 297
|
||||
[signals_width] 230
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 158
|
||||
@28
|
||||
tb.user_project.ena
|
||||
@29
|
||||
tb.user_project.clk
|
||||
@28
|
||||
tb.user_project.rst_n
|
||||
@200
|
||||
-Inputs
|
||||
@22
|
||||
tb.user_project.ui_in[7:0]
|
||||
@200
|
||||
-Bidirectional Pins
|
||||
@22
|
||||
tb.user_project.uio_in[7:0]
|
||||
tb.user_project.uio_oe[7:0]
|
||||
tb.user_project.uio_out[7:0]
|
||||
@200
|
||||
-Output Pins
|
||||
@22
|
||||
tb.user_project.uo_out[7:0]
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
|
@ -0,0 +1,45 @@
|
|||
`default_nettype none
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/* This testbench just instantiates the module and makes some convenient wires
|
||||
that can be driven / tested by the cocotb test.py.
|
||||
*/
|
||||
module tb ();
|
||||
|
||||
// Dump the signals to a VCD file. You can view it with gtkwave.
|
||||
initial begin
|
||||
$dumpfile("tb.vcd");
|
||||
$dumpvars(0, tb);
|
||||
#1;
|
||||
end
|
||||
|
||||
// Wire up the inputs and outputs:
|
||||
reg clk;
|
||||
reg rst_n;
|
||||
reg ena;
|
||||
reg [7:0] ui_in;
|
||||
reg [7:0] uio_in;
|
||||
wire [7:0] uo_out;
|
||||
wire [7:0] uio_out;
|
||||
wire [7:0] uio_oe;
|
||||
|
||||
// Replace tt_um_example with your module name:
|
||||
tt_um_example user_project (
|
||||
|
||||
// Include power ports for the Gate Level test:
|
||||
`ifdef GL_TEST
|
||||
.VPWR(1'b1),
|
||||
.VGND(1'b0),
|
||||
`endif
|
||||
|
||||
.ui_in (ui_in), // Dedicated inputs
|
||||
.uo_out (uo_out), // Dedicated outputs
|
||||
.uio_in (uio_in), // IOs: Input path
|
||||
.uio_out(uio_out), // IOs: Output path
|
||||
.uio_oe (uio_oe), // IOs: Enable path (active high: 0=input, 1=output)
|
||||
.ena (ena), // enable - goes high when design is selected
|
||||
.clk (clk), // clock
|
||||
.rst_n (rst_n) // not reset
|
||||
);
|
||||
|
||||
endmodule
|
|
@ -0,0 +1,40 @@
|
|||
# SPDX-FileCopyrightText: © 2024 Tiny Tapeout
|
||||
# SPDX-License-Identifier: MIT
|
||||
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import ClockCycles
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def test_project(dut):
|
||||
dut._log.info("Start")
|
||||
|
||||
# Set the clock period to 10 us (100 KHz)
|
||||
clock = Clock(dut.clk, 10, units="us")
|
||||
cocotb.start_soon(clock.start())
|
||||
|
||||
# Reset
|
||||
dut._log.info("Reset")
|
||||
dut.ena.value = 1
|
||||
dut.ui_in.value = 0
|
||||
dut.uio_in.value = 0
|
||||
dut.rst_n.value = 0
|
||||
await ClockCycles(dut.clk, 10)
|
||||
dut.rst_n.value = 1
|
||||
|
||||
dut._log.info("Test project behavior")
|
||||
|
||||
# Set the input values you want to test
|
||||
dut.ui_in.value = 20
|
||||
dut.uio_in.value = 30
|
||||
|
||||
# Wait for one clock cycle to see the output values
|
||||
await ClockCycles(dut.clk, 1)
|
||||
|
||||
# The following assersion is just an example of how to check the output values.
|
||||
# Change it to match the actual expected output of your module:
|
||||
assert dut.uo_out.value == 50
|
||||
|
||||
# Keep testing the module by changing the input values, waiting for
|
||||
# one or more clock cycles, and asserting the expected output values.
|
Loading…
Reference in New Issue