46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
`default_nettype none
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`timescale 1ns / 1ps
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/* This testbench just instantiates the module and makes some convenient wires
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that can be driven / tested by the cocotb test.py.
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*/
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module tb ();
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// Dump the signals to a VCD file. You can view it with gtkwave.
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initial begin
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$dumpfile("tb.vcd");
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$dumpvars(0, tb);
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#1;
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end
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// Wire up the inputs and outputs:
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reg clk;
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reg rst_n;
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reg ena;
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reg [7:0] ui_in;
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reg [7:0] uio_in;
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wire [7:0] uo_out;
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wire [7:0] uio_out;
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wire [7:0] uio_oe;
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// Replace tt_um_example with your module name:
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tt_um_xeniarose_sha256 user_project (
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// Include power ports for the Gate Level test:
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`ifdef GL_TEST
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.VPWR(1'b1),
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.VGND(1'b0),
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`endif
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.ui_in (ui_in), // Dedicated inputs
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.uo_out (uo_out), // Dedicated outputs
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.uio_in (uio_in), // IOs: Input path
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.uio_out(uio_out), // IOs: Output path
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.uio_oe (uio_oe), // IOs: Enable path (active high: 0=input, 1=output)
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.ena (ena), // enable - goes high when design is selected
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.clk (clk), // clock
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.rst_n (rst_n) // not reset
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);
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endmodule
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