.clang-format

@@ -0,0 +1,9 @@
+---
+BasedOnStyle: Google
+IndentWidth: 4
+ColumnLimit: 100
+---
+Language: Cpp
+DerivePointerAlignment: false
+PointerAlignment: Left
+...

.gitignore

@@ -1,2 +1,4 @@
 cmake-build/
+build/
 ex/
+compile_commands.json

.gitmodules

@@ -1,6 +1,3 @@
 [submodule "tinyusb"]
 	path = tinyusb
 	url = https://github.com/hathach/tinyusb
-[submodule "CMSIS_5"]
-	path = CMSIS_5
-	url = https://github.com/ARM-software/CMSIS_5.git

CMSIS/Core/Include/cachel1_armv7.h

@@ -0,0 +1,411 @@
+/******************************************************************************
+ * @file     cachel1_armv7.h
+ * @brief    CMSIS Level 1 Cache API for Armv7-M and later
+ * @version  V1.0.0
+ * @date     03. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_CACHEL1_ARMV7_H
+#define ARM_CACHEL1_ARMV7_H
+
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+#ifndef __SCB_DCACHE_LINE_SIZE
+#define __SCB_DCACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif
+
+#ifndef __SCB_ICACHE_LINE_SIZE
+#define __SCB_ICACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
+#endif 
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
+
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   I-Cache Invalidate by address
+  \details Invalidates I-Cache for the given address.
+           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           I-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   isize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    if ( isize > 0 ) {
+       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
+
+      __DSB();
+
+      do {
+        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_ICACHE_LINE_SIZE;
+        op_size -= __SCB_ICACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address.
+           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are invalidated.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) { 
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    
+      __DSB();
+
+      do {
+        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+           D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned.
+  \param[in]   addr    address
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) { 
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    
+      __DSB();
+
+      do {
+        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr += __SCB_DCACHE_LINE_SIZE;
+        op_size -= __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+           D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
+           D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) { 
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+    
+      __DSB();
+
+      do {
+        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+        op_addr +=          __SCB_DCACHE_LINE_SIZE;
+        op_size -=          __SCB_DCACHE_LINE_SIZE;
+      } while ( op_size > 0 );
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+#endif /* ARM_CACHEL1_ARMV7_H */

CMSIS/Core/Include/cmsis_armcc.h

@@ -0,0 +1,885 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.2.1
+ * @date     26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+  /* __ARM_ARCH_8_1M_MAIN__  not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __memory_changed()
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section("RESET")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

CMSIS/Core/Include/cmsis_compiler.h

@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

CMSIS/Core/Include/cmsis_iccarm.h

@@ -0,0 +1,969 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.2.0
+ * @date     28. January 2020
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2020 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#undef __WEAK                           /* undo the definition from DLib_Defaults.h */
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* __CMSIS_ICCARM_H__ */

CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.4
+ * @date     23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

CMSIS/Core/Include/core_cm0.h

@@ -0,0 +1,952 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     21. August 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RESERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */
+  *(vectors + (int32_t)IRQn) = vector;                              /* use pointer arithmetic to access vector */
+  /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */
+  return *(vectors + (int32_t)IRQn);                                /* use pointer arithmetic to access vector */
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

CMSIS/Core/Include/core_cm1.h

@@ -0,0 +1,979 @@
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.1
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_FP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  /* ARM Application Note 321 states that the M1 does not require the architectural barrier */
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

CMSIS/Core/Include/mpu_armv7.h

@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.2
+ * @date     25. May 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

CMSIS/Core/Include/mpu_armv8.h

@@ -0,0 +1,352 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.2
+ * @date     10. February 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  (((BASE) & MPU_RBAR_BASE_Msk) | \
+  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DMB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

CMSIS/Core/Include/pmu_armv8.h

@@ -0,0 +1,337 @@
+/******************************************************************************
+ * @file     pmu_armv8.h
+ * @brief    CMSIS PMU API for Armv8.1-M PMU
+ * @version  V1.0.1
+ * @date     15. April 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_PMU_ARMV8_H
+#define ARM_PMU_ARMV8_H
+
+/**
+ * \brief PMU Events
+ * \note  See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
+ * */
+
+#define ARM_PMU_SW_INCR                              0x0000             /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
+#define ARM_PMU_L1I_CACHE_REFILL                     0x0001             /*!< L1 I-Cache refill */
+#define ARM_PMU_L1D_CACHE_REFILL                     0x0003             /*!< L1 D-Cache refill */
+#define ARM_PMU_L1D_CACHE                            0x0004             /*!< L1 D-Cache access */
+#define ARM_PMU_LD_RETIRED                           0x0006             /*!< Memory-reading instruction architecturally executed and condition code check pass */
+#define ARM_PMU_ST_RETIRED                           0x0007             /*!< Memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_INST_RETIRED                         0x0008             /*!< Instruction architecturally executed */
+#define ARM_PMU_EXC_TAKEN                            0x0009             /*!< Exception entry */
+#define ARM_PMU_EXC_RETURN                           0x000A             /*!< Exception return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_PC_WRITE_RETIRED                     0x000C             /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
+#define ARM_PMU_BR_IMMED_RETIRED                     0x000D             /*!< Immediate branch architecturally executed */
+#define ARM_PMU_BR_RETURN_RETIRED                    0x000E             /*!< Function return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_UNALIGNED_LDST_RETIRED               0x000F             /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BR_MIS_PRED                          0x0010             /*!< Mispredicted or not predicted branch speculatively executed */
+#define ARM_PMU_CPU_CYCLES                           0x0011             /*!< Cycle */
+#define ARM_PMU_BR_PRED                              0x0012             /*!< Predictable branch speculatively executed */
+#define ARM_PMU_MEM_ACCESS                           0x0013             /*!< Data memory access */
+#define ARM_PMU_L1I_CACHE                            0x0014             /*!< Level 1 instruction cache access */
+#define ARM_PMU_L1D_CACHE_WB                         0x0015             /*!< Level 1 data cache write-back */
+#define ARM_PMU_L2D_CACHE                            0x0016             /*!< Level 2 data cache access */
+#define ARM_PMU_L2D_CACHE_REFILL                     0x0017             /*!< Level 2 data cache refill */
+#define ARM_PMU_L2D_CACHE_WB                         0x0018             /*!< Level 2 data cache write-back */
+#define ARM_PMU_BUS_ACCESS                           0x0019             /*!< Bus access */
+#define ARM_PMU_MEMORY_ERROR                         0x001A             /*!< Local memory error */
+#define ARM_PMU_INST_SPEC                            0x001B             /*!< Instruction speculatively executed */
+#define ARM_PMU_BUS_CYCLES                           0x001D             /*!< Bus cycles */
+#define ARM_PMU_CHAIN                                0x001E             /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
+#define ARM_PMU_L1D_CACHE_ALLOCATE                   0x001F             /*!< Level 1 data cache allocation without refill */
+#define ARM_PMU_L2D_CACHE_ALLOCATE                   0x0020             /*!< Level 2 data cache allocation without refill */
+#define ARM_PMU_BR_RETIRED                           0x0021             /*!< Branch instruction architecturally executed */
+#define ARM_PMU_BR_MIS_PRED_RETIRED                  0x0022             /*!< Mispredicted branch instruction architecturally executed */
+#define ARM_PMU_STALL_FRONTEND                       0x0023             /*!< No operation issued because of the frontend */
+#define ARM_PMU_STALL_BACKEND                        0x0024             /*!< No operation issued because of the backend */
+#define ARM_PMU_L2I_CACHE                            0x0027             /*!< Level 2 instruction cache access */
+#define ARM_PMU_L2I_CACHE_REFILL                     0x0028             /*!< Level 2 instruction cache refill */
+#define ARM_PMU_L3D_CACHE_ALLOCATE                   0x0029             /*!< Level 3 data cache allocation without refill */
+#define ARM_PMU_L3D_CACHE_REFILL                     0x002A             /*!< Level 3 data cache refill */
+#define ARM_PMU_L3D_CACHE                            0x002B             /*!< Level 3 data cache access */
+#define ARM_PMU_L3D_CACHE_WB                         0x002C             /*!< Level 3 data cache write-back */
+#define ARM_PMU_LL_CACHE_RD                          0x0036             /*!< Last level data cache read */
+#define ARM_PMU_LL_CACHE_MISS_RD                     0x0037             /*!< Last level data cache read miss */
+#define ARM_PMU_L1D_CACHE_MISS_RD                    0x0039             /*!< Level 1 data cache read miss */
+#define ARM_PMU_OP_COMPLETE                          0x003A             /*!< Operation retired */
+#define ARM_PMU_OP_SPEC                              0x003B             /*!< Operation speculatively executed */
+#define ARM_PMU_STALL                                0x003C             /*!< Stall cycle for instruction or operation not sent for execution */
+#define ARM_PMU_STALL_OP_BACKEND                     0x003D             /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
+#define ARM_PMU_STALL_OP_FRONTEND                    0x003E             /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
+#define ARM_PMU_STALL_OP                             0x003F             /*!< Instruction or operation slots not occupied each cycle */
+#define ARM_PMU_L1D_CACHE_RD                         0x0040             /*!< Level 1 data cache read */
+#define ARM_PMU_LE_RETIRED                           0x0100             /*!< Loop end instruction executed */
+#define ARM_PMU_LE_SPEC                              0x0101             /*!< Loop end instruction speculatively executed */
+#define ARM_PMU_BF_RETIRED                           0x0104             /*!< Branch future instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BF_SPEC                              0x0105             /*!< Branch future instruction speculatively executed and condition code check pass */
+#define ARM_PMU_LE_CANCEL                            0x0108             /*!< Loop end instruction not taken */
+#define ARM_PMU_BF_CANCEL                            0x0109             /*!< Branch future instruction not taken */
+#define ARM_PMU_SE_CALL_S                            0x0114             /*!< Call to secure function, resulting in Security state change */
+#define ARM_PMU_SE_CALL_NS                           0x0115             /*!< Call to non-secure function, resulting in Security state change */
+#define ARM_PMU_DWT_CMPMATCH0                        0x0118             /*!< DWT comparator 0 match */
+#define ARM_PMU_DWT_CMPMATCH1                        0x0119             /*!< DWT comparator 1 match */
+#define ARM_PMU_DWT_CMPMATCH2                        0x011A             /*!< DWT comparator 2 match */
+#define ARM_PMU_DWT_CMPMATCH3                        0x011B             /*!< DWT comparator 3 match */
+#define ARM_PMU_MVE_INST_RETIRED                     0x0200             /*!< MVE instruction architecturally executed */
+#define ARM_PMU_MVE_INST_SPEC                        0x0201             /*!< MVE instruction speculatively executed */
+#define ARM_PMU_MVE_FP_RETIRED                       0x0204             /*!< MVE floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SPEC                          0x0205             /*!< MVE floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_HP_RETIRED                    0x0208             /*!< MVE half-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_HP_SPEC                       0x0209             /*!< MVE half-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_SP_RETIRED                    0x020C             /*!< MVE single-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SP_SPEC                       0x020D             /*!< MVE single-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_MAC_RETIRED                   0x0214             /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_FP_MAC_SPEC                      0x0215             /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_INT_RETIRED                      0x0224             /*!< MVE integer instruction architecturally executed */
+#define ARM_PMU_MVE_INT_SPEC                         0x0225             /*!< MVE integer instruction speculatively executed */
+#define ARM_PMU_MVE_INT_MAC_RETIRED                  0x0228             /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_INT_MAC_SPEC                     0x0229             /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_RETIRED                     0x0238             /*!< MVE load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_SPEC                        0x0239             /*!< MVE load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_RETIRED                       0x023C             /*!< MVE load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_SPEC                          0x023D             /*!< MVE load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_RETIRED                       0x0240             /*!< MVE store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_SPEC                          0x0241             /*!< MVE store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_CONTIG_RETIRED              0x0244             /*!< MVE contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_CONTIG_SPEC                 0x0245             /*!< MVE contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_CONTIG_RETIRED                0x0248             /*!< MVE contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_CONTIG_SPEC                   0x0249             /*!< MVE contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_CONTIG_RETIRED                0x024C             /*!< MVE contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_CONTIG_SPEC                   0x024D             /*!< MVE contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED           0x0250             /*!< MVE non-contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC              0x0251             /*!< MVE non-contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED             0x0254             /*!< MVE non-contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_SPEC                0x0255             /*!< MVE non-contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED             0x0258             /*!< MVE non-contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_SPEC                0x0259             /*!< MVE non-contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_MULTI_RETIRED               0x025C             /*!< MVE memory instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LDST_MULTI_SPEC                  0x025D             /*!< MVE memory instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LD_MULTI_RETIRED                 0x0260             /*!< MVE memory load instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LD_MULTI_SPEC                    0x0261             /*!< MVE memory load instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_ST_MULTI_RETIRED                 0x0261             /*!< MVE memory store instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_ST_MULTI_SPEC                    0x0265             /*!< MVE memory store instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED           0x028C             /*!< MVE unaligned memory load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC              0x028D             /*!< MVE unaligned memory load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED             0x0290             /*!< MVE unaligned load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_SPEC                0x0291             /*!< MVE unaligned load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED             0x0294             /*!< MVE unaligned store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_SPEC                0x0295             /*!< MVE unaligned store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298             /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC    0x0299             /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_RETIRED                  0x02A0             /*!< MVE vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_SPEC                     0x02A1             /*!< MVE vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_FP_RETIRED               0x02A4             /*!< MVE floating-point vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_FP_SPEC                  0x02A5             /*!< MVE floating-point vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_INT_RETIRED              0x02A8             /*!< MVE integer vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_INT_SPEC                 0x02A9             /*!< MVE integer vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_PRED                             0x02B8             /*!< Cycles where one or more predicated beats architecturally executed */
+#define ARM_PMU_MVE_STALL                            0x02CC             /*!< Stall cycles caused by an MVE instruction */
+#define ARM_PMU_MVE_STALL_RESOURCE                   0x02CD             /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_MEM               0x02CE             /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_FP                0x02CF             /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_INT               0x02D0             /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
+#define ARM_PMU_MVE_STALL_BREAK                      0x02D3             /*!< Stall cycles caused by an MVE chain break */
+#define ARM_PMU_MVE_STALL_DEPENDENCY                 0x02D4             /*!< Stall cycles caused by MVE register dependency */
+#define ARM_PMU_ITCM_ACCESS                          0x4007             /*!< Instruction TCM access */
+#define ARM_PMU_DTCM_ACCESS                          0x4008             /*!< Data TCM access */
+#define ARM_PMU_TRCEXTOUT0                           0x4010             /*!< ETM external output 0 */
+#define ARM_PMU_TRCEXTOUT1                           0x4011             /*!< ETM external output 1 */
+#define ARM_PMU_TRCEXTOUT2                           0x4012             /*!< ETM external output 2 */
+#define ARM_PMU_TRCEXTOUT3                           0x4013             /*!< ETM external output 3 */
+#define ARM_PMU_CTI_TRIGOUT4                         0x4018             /*!< Cross-trigger Interface output trigger 4 */
+#define ARM_PMU_CTI_TRIGOUT5                         0x4019             /*!< Cross-trigger Interface output trigger 5 */
+#define ARM_PMU_CTI_TRIGOUT6                         0x401A             /*!< Cross-trigger Interface output trigger 6 */
+#define ARM_PMU_CTI_TRIGOUT7                         0x401B             /*!< Cross-trigger Interface output trigger 7 */
+
+/** \brief PMU Functions */
+
+__STATIC_INLINE void ARM_PMU_Enable(void);
+__STATIC_INLINE void ARM_PMU_Disable(void);
+
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
+
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
+
+/** 
+  \brief   Enable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Enable(void) 
+{
+  PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
+}
+
+/** 
+  \brief   Disable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Disable(void) 
+{
+  PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
+}
+
+/** 
+  \brief   Set event to count for PMU eventer counter
+  \param [in]    num     Event counter (0-30) to configure
+  \param [in]    type    Event to count
+*/
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
+{
+  PMU->EVTYPER[num] = type;
+}
+
+/** 
+  \brief  Reset cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
+{
+  PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
+}
+
+/** 
+  \brief  Reset all event counters
+*/
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
+{
+  PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
+}
+
+/** 
+  \brief  Enable counters 
+  \param [in]     mask    Counters to enable
+  \note   Enables one or more of the following:
+          - event counters (0-30)
+          - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
+{
+  PMU->CNTENSET = mask;
+}
+
+/** 
+  \brief  Disable counters
+  \param [in]     mask    Counters to enable
+  \note   Disables one or more of the following:
+          - event counters (0-30)
+          - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
+{
+  PMU->CNTENCLR = mask;
+}
+
+/** 
+  \brief  Read cycle counter
+  \return                 Cycle count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
+{
+  return PMU->CCNTR;
+}
+
+/** 
+  \brief   Read event counter
+  \param [in]     num     Event counter (0-30) to read
+  \return                 Event count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
+{
+  return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
+}
+
+/** 
+  \brief   Read counter overflow status
+  \return  Counter overflow status bits for the following:
+          - event counters (0-30)
+          - cycle counter
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
+{
+  return PMU->OVSSET;	
+}
+
+/** 
+  \brief   Clear counter overflow status
+  \param [in]     mask    Counter overflow status bits to clear
+  \note    Clears overflow status bits for one or more of the following:
+           - event counters (0-30)
+           - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
+{
+  PMU->OVSCLR = mask;
+}
+
+/** 
+  \brief   Enable counter overflow interrupt request 
+  \param [in]     mask    Counter overflow interrupt request bits to set
+  \note    Sets overflow interrupt request bits for one or more of the following:
+           - event counters (0-30)
+           - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
+{
+  PMU->INTENSET = mask;
+}
+
+/** 
+  \brief   Disable counter overflow interrupt request 
+  \param [in]     mask    Counter overflow interrupt request bits to clear
+  \note    Clears overflow interrupt request bits for one or more of the following:
+           - event counters (0-30)
+           - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
+{
+  PMU->INTENCLR = mask;
+}
+
+/** 
+  \brief   Software increment event counter 
+  \param [in]     mask    Counters to increment
+  \note    Software increment bits for one or more event counters (0-30)
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
+{
+  PMU->SWINC = mask;
+}
+
+#endif

CMSIS/Core/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

CMSIS/DAP/Firmware/Include/DAP.h

@@ -0,0 +1,325 @@
+/*
+ * Copyright (c) 2013-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        26. November 2019
+ * $Revision:    V2.0.0
+ *
+ * Project:      CMSIS-DAP Include
+ * Title:        DAP.h Definitions
+ *
+ *---------------------------------------------------------------------------*/
+
+#ifndef __DAP_H__
+#define __DAP_H__
+
+
+// DAP Firmware Version
+#ifdef  DAP_FW_V1
+#define DAP_FW_VER                      "1.2.0"
+#else
+#define DAP_FW_VER                      "2.0.0"
+#endif
+
+// DAP Command IDs
+#define ID_DAP_Info                     0x00U
+#define ID_DAP_HostStatus               0x01U
+#define ID_DAP_Connect                  0x02U
+#define ID_DAP_Disconnect               0x03U
+#define ID_DAP_TransferConfigure        0x04U
+#define ID_DAP_Transfer                 0x05U
+#define ID_DAP_TransferBlock            0x06U
+#define ID_DAP_TransferAbort            0x07U
+#define ID_DAP_WriteABORT               0x08U
+#define ID_DAP_Delay                    0x09U
+#define ID_DAP_ResetTarget              0x0AU
+#define ID_DAP_SWJ_Pins                 0x10U
+#define ID_DAP_SWJ_Clock                0x11U
+#define ID_DAP_SWJ_Sequence             0x12U
+#define ID_DAP_SWD_Configure            0x13U
+#define ID_DAP_SWD_Sequence             0x1DU
+#define ID_DAP_JTAG_Sequence            0x14U
+#define ID_DAP_JTAG_Configure           0x15U
+#define ID_DAP_JTAG_IDCODE              0x16U
+#define ID_DAP_SWO_Transport            0x17U
+#define ID_DAP_SWO_Mode                 0x18U
+#define ID_DAP_SWO_Baudrate             0x19U
+#define ID_DAP_SWO_Control              0x1AU
+#define ID_DAP_SWO_Status               0x1BU
+#define ID_DAP_SWO_ExtendedStatus       0x1EU
+#define ID_DAP_SWO_Data                 0x1CU
+
+#define ID_DAP_QueueCommands            0x7EU
+#define ID_DAP_ExecuteCommands          0x7FU
+
+// DAP Vendor Command IDs
+#define ID_DAP_Vendor0                  0x80U
+#define ID_DAP_Vendor1                  0x81U
+#define ID_DAP_Vendor2                  0x82U
+#define ID_DAP_Vendor3                  0x83U
+#define ID_DAP_Vendor4                  0x84U
+#define ID_DAP_Vendor5                  0x85U
+#define ID_DAP_Vendor6                  0x86U
+#define ID_DAP_Vendor7                  0x87U
+#define ID_DAP_Vendor8                  0x88U
+#define ID_DAP_Vendor9                  0x89U
+#define ID_DAP_Vendor10                 0x8AU
+#define ID_DAP_Vendor11                 0x8BU
+#define ID_DAP_Vendor12                 0x8CU
+#define ID_DAP_Vendor13                 0x8DU
+#define ID_DAP_Vendor14                 0x8EU
+#define ID_DAP_Vendor15                 0x8FU
+#define ID_DAP_Vendor16                 0x90U
+#define ID_DAP_Vendor17                 0x91U
+#define ID_DAP_Vendor18                 0x92U
+#define ID_DAP_Vendor19                 0x93U
+#define ID_DAP_Vendor20                 0x94U
+#define ID_DAP_Vendor21                 0x95U
+#define ID_DAP_Vendor22                 0x96U
+#define ID_DAP_Vendor23                 0x97U
+#define ID_DAP_Vendor24                 0x98U
+#define ID_DAP_Vendor25                 0x99U
+#define ID_DAP_Vendor26                 0x9AU
+#define ID_DAP_Vendor27                 0x9BU
+#define ID_DAP_Vendor28                 0x9CU
+#define ID_DAP_Vendor29                 0x9DU
+#define ID_DAP_Vendor30                 0x9EU
+#define ID_DAP_Vendor31                 0x9FU
+
+#define ID_DAP_Invalid                  0xFFU
+
+// DAP Status Code
+#define DAP_OK                          0U
+#define DAP_ERROR                       0xFFU
+
+// DAP ID
+#define DAP_ID_VENDOR                   1U
+#define DAP_ID_PRODUCT                  2U
+#define DAP_ID_SER_NUM                  3U
+#define DAP_ID_FW_VER                   4U
+#define DAP_ID_DEVICE_VENDOR            5U
+#define DAP_ID_DEVICE_NAME              6U
+#define DAP_ID_CAPABILITIES             0xF0U
+#define DAP_ID_TIMESTAMP_CLOCK          0xF1U
+#define DAP_ID_SWO_BUFFER_SIZE          0xFDU
+#define DAP_ID_PACKET_COUNT             0xFEU
+#define DAP_ID_PACKET_SIZE              0xFFU
+
+// DAP Host Status
+#define DAP_DEBUGGER_CONNECTED          0U
+#define DAP_TARGET_RUNNING              1U
+
+// DAP Port
+#define DAP_PORT_AUTODETECT             0U      // Autodetect Port
+#define DAP_PORT_DISABLED               0U      // Port Disabled (I/O pins in High-Z)
+#define DAP_PORT_SWD                    1U      // SWD Port (SWCLK, SWDIO) + nRESET
+#define DAP_PORT_JTAG                   2U      // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET
+
+// DAP SWJ Pins
+#define DAP_SWJ_SWCLK_TCK               0       // SWCLK/TCK
+#define DAP_SWJ_SWDIO_TMS               1       // SWDIO/TMS
+#define DAP_SWJ_TDI                     2       // TDI
+#define DAP_SWJ_TDO                     3       // TDO
+#define DAP_SWJ_nTRST                   5       // nTRST
+#define DAP_SWJ_nRESET                  7       // nRESET
+
+// DAP Transfer Request
+#define DAP_TRANSFER_APnDP              (1U<<0)
+#define DAP_TRANSFER_RnW                (1U<<1)
+#define DAP_TRANSFER_A2                 (1U<<2)
+#define DAP_TRANSFER_A3                 (1U<<3)
+#define DAP_TRANSFER_MATCH_VALUE        (1U<<4)
+#define DAP_TRANSFER_MATCH_MASK         (1U<<5)
+#define DAP_TRANSFER_TIMESTAMP          (1U<<7)
+
+// DAP Transfer Response
+#define DAP_TRANSFER_OK                 (1U<<0)
+#define DAP_TRANSFER_WAIT               (1U<<1)
+#define DAP_TRANSFER_FAULT              (1U<<2)
+#define DAP_TRANSFER_ERROR              (1U<<3)
+#define DAP_TRANSFER_MISMATCH           (1U<<4)
+
+// DAP SWO Trace Mode
+#define DAP_SWO_OFF                     0U
+#define DAP_SWO_UART                    1U
+#define DAP_SWO_MANCHESTER              2U
+
+// DAP SWO Trace Status
+#define DAP_SWO_CAPTURE_ACTIVE          (1U<<0)
+#define DAP_SWO_CAPTURE_PAUSED          (1U<<1)
+#define DAP_SWO_STREAM_ERROR            (1U<<6)
+#define DAP_SWO_BUFFER_OVERRUN          (1U<<7)
+
+
+// Debug Port Register Addresses
+#define DP_IDCODE                       0x00U   // IDCODE Register (SW Read only)
+#define DP_ABORT                        0x00U   // Abort Register (SW Write only)
+#define DP_CTRL_STAT                    0x04U   // Control & Status
+#define DP_WCR                          0x04U   // Wire Control Register (SW Only)
+#define DP_SELECT                       0x08U   // Select Register (JTAG R/W & SW W)
+#define DP_RESEND                       0x08U   // Resend (SW Read Only)
+#define DP_RDBUFF                       0x0CU   // Read Buffer (Read Only)
+
+// JTAG IR Codes
+#define JTAG_ABORT                      0x08U
+#define JTAG_DPACC                      0x0AU
+#define JTAG_APACC                      0x0BU
+#define JTAG_IDCODE                     0x0EU
+#define JTAG_BYPASS                     0x0FU
+
+// JTAG Sequence Info
+#define JTAG_SEQUENCE_TCK               0x3FU   // TCK count
+#define JTAG_SEQUENCE_TMS               0x40U   // TMS value
+#define JTAG_SEQUENCE_TDO               0x80U   // TDO capture
+
+// SWD Sequence Info
+#define SWD_SEQUENCE_CLK                0x3FU   // SWCLK count
+#define SWD_SEQUENCE_DIN                0x80U   // SWDIO capture
+
+
+#include <stddef.h>
+#include <stdint.h>
+#include "cmsis_compiler.h"
+
+// DAP Data structure
+typedef struct {
+  uint8_t     debug_port;                       // Debug Port
+  uint8_t     fast_clock;                       // Fast Clock Flag
+  uint8_t     padding[2];
+  uint32_t   clock_delay;                       // Clock Delay
+  uint32_t     timestamp;                       // Last captured Timestamp
+  struct {                                      // Transfer Configuration
+    uint8_t   idle_cycles;                      // Idle cycles after transfer
+    uint8_t    padding[3];
+    uint16_t  retry_count;                      // Number of retries after WAIT response
+    uint16_t  match_retry;                      // Number of retries if read value does not match
+    uint32_t  match_mask;                       // Match Mask
+  } transfer;
+#if (DAP_SWD != 0)
+  struct {                                      // SWD Configuration
+    uint8_t    turnaround;                      // Turnaround period
+    uint8_t    data_phase;                      // Always generate Data Phase
+  } swd_conf;
+#endif
+#if (DAP_JTAG != 0)
+  struct {                                      // JTAG Device Chain
+    uint8_t   count;                            // Number of devices
+    uint8_t   index;                            // Device index (device at TDO has index 0)
+#if (DAP_JTAG_DEV_CNT != 0)
+    uint8_t   ir_length[DAP_JTAG_DEV_CNT];      // IR Length in bits
+    uint16_t  ir_before[DAP_JTAG_DEV_CNT];      // Bits before IR
+    uint16_t  ir_after [DAP_JTAG_DEV_CNT];      // Bits after IR
+#endif
+  } jtag_dev;
+#endif
+} DAP_Data_t;
+
+extern          DAP_Data_t DAP_Data;            // DAP Data
+extern volatile uint8_t    DAP_TransferAbort;   // Transfer Abort Flag
+
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+// Functions
+extern void     SWJ_Sequence    (uint32_t count, const uint8_t *data);
+extern void     SWD_Sequence    (uint32_t info,  const uint8_t *swdo, uint8_t *swdi);
+extern void     JTAG_Sequence   (uint32_t info,  const uint8_t *tdi,  uint8_t *tdo);
+extern void     JTAG_IR         (uint32_t ir);
+extern uint32_t JTAG_ReadIDCode (void);
+extern void     JTAG_WriteAbort (uint32_t data);
+extern uint8_t  JTAG_Transfer   (uint32_t request, uint32_t *data);
+extern uint8_t  SWD_Transfer    (uint32_t request, uint32_t *data);
+
+extern void     Delayms         (uint32_t delay);
+
+extern uint32_t SWO_Transport      (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Mode           (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Baudrate       (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Control        (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Status                                 (uint8_t *response);
+extern uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response);
+extern uint32_t SWO_Data           (const uint8_t *request, uint8_t *response);
+
+extern void     SWO_QueueTransfer    (uint8_t *buf, uint32_t num);
+extern void     SWO_AbortTransfer    (void);
+extern void     SWO_TransferComplete (void);
+
+extern uint32_t UART_SWO_Mode     (uint32_t enable);
+extern uint32_t UART_SWO_Baudrate (uint32_t baudrate);
+extern uint32_t UART_SWO_Control  (uint32_t active);
+extern void     UART_SWO_Capture  (uint8_t *buf, uint32_t num);
+extern uint32_t UART_SWO_GetCount (void);
+
+extern uint32_t Manchester_SWO_Mode     (uint32_t enable);
+extern uint32_t Manchester_SWO_Baudrate (uint32_t baudrate);
+extern uint32_t Manchester_SWO_Control  (uint32_t active);
+extern void     Manchester_SWO_Capture  (uint8_t *buf, uint32_t num);
+extern uint32_t Manchester_SWO_GetCount (void);
+
+extern uint32_t DAP_ProcessVendorCommand (const uint8_t *request, uint8_t *response);
+extern uint32_t DAP_ProcessCommand       (const uint8_t *request, uint8_t *response);
+extern uint32_t DAP_ExecuteCommand       (const uint8_t *request, uint8_t *response);
+
+extern void     DAP_Setup (void);
+
+// Configurable delay for clock generation
+#ifndef DELAY_SLOW_CYCLES
+#define DELAY_SLOW_CYCLES       3U      // Number of cycles for one iteration
+#endif
+#if defined(__CC_ARM)
+__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) {
+  uint32_t count = delay;
+  while (--count);
+}
+#else
+__STATIC_FORCEINLINE void PIN_DELAY_SLOW (uint32_t delay) {
+  __ASM volatile (
+  ".syntax unified\n"
+  "0:\n\t"
+    "subs %0,%0,#1\n\t"
+    "bne  0b\n"
+  : "+l" (delay) : : "cc"
+  );
+}
+#endif
+
+// Fixed delay for fast clock generation
+#ifndef DELAY_FAST_CYCLES
+#define DELAY_FAST_CYCLES       0U      // Number of cycles: 0..3
+#endif
+__STATIC_FORCEINLINE void PIN_DELAY_FAST (void) {
+#if (DELAY_FAST_CYCLES >= 1U)
+  __NOP();
+#endif
+#if (DELAY_FAST_CYCLES >= 2U)
+  __NOP();
+#endif
+#if (DELAY_FAST_CYCLES >= 3U)
+  __NOP();
+#endif
+}
+
+#ifdef  __cplusplus
+}
+#endif
+
+
+#endif  /* __DAP_H__ */

CMSIS/DAP/Firmware/Source/DAP_vendor.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        1. December 2017
+ * $Revision:    V2.0.0
+ *
+ * Project:      CMSIS-DAP Source
+ * Title:        DAP_vendor.c CMSIS-DAP Vendor Commands
+ *
+ *---------------------------------------------------------------------------*/
+ 
+#include "DAP_config.h"
+#include "DAP.h"
+
+//**************************************************************************************************
+/** 
+\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands
+\ingroup DAP_Vendor_gr 
+@{
+
+The file DAP_vendor.c provides template source code for extension of a Debug Unit with 
+Vendor Commands. Copy this file to the project folder of the Debug Unit and add the 
+file to the MDK-ARM project under the file group Configuration.
+*/
+
+/** Process DAP Vendor Command and prepare Response Data
+\param request   pointer to request data
+\param response  pointer to response data
+\return          number of bytes in response (lower 16 bits)
+                 number of bytes in request (upper 16 bits)
+*/
+uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) {
+  uint32_t num = (1U << 16) | 1U;
+
+  *response++ = *request;        // copy Command ID
+
+  switch (*request++) {          // first byte in request is Command ID
+    case ID_DAP_Vendor0:
+#if 0                            // example user command
+      num += 1U << 16;           // increment request count
+      if (*request == 1U) {      // when first command data byte is 1
+        *response++ = 'X';       // send 'X' as response
+        num++;                   // increment response count
+      }
+#endif
+      break;
+
+    case ID_DAP_Vendor1:  break;
+    case ID_DAP_Vendor2:  break;
+    case ID_DAP_Vendor3:  break;
+    case ID_DAP_Vendor4:  break;
+    case ID_DAP_Vendor5:  break;
+    case ID_DAP_Vendor6:  break;
+    case ID_DAP_Vendor7:  break;
+    case ID_DAP_Vendor8:  break;
+    case ID_DAP_Vendor9:  break;
+    case ID_DAP_Vendor10: break;
+    case ID_DAP_Vendor11: break;
+    case ID_DAP_Vendor12: break;
+    case ID_DAP_Vendor13: break;
+    case ID_DAP_Vendor14: break;
+    case ID_DAP_Vendor15: break;
+    case ID_DAP_Vendor16: break;
+    case ID_DAP_Vendor17: break;
+    case ID_DAP_Vendor18: break;
+    case ID_DAP_Vendor19: break;
+    case ID_DAP_Vendor20: break;
+    case ID_DAP_Vendor21: break;
+    case ID_DAP_Vendor22: break;
+    case ID_DAP_Vendor23: break;
+    case ID_DAP_Vendor24: break;
+    case ID_DAP_Vendor25: break;
+    case ID_DAP_Vendor26: break;
+    case ID_DAP_Vendor27: break;
+    case ID_DAP_Vendor28: break;
+    case ID_DAP_Vendor29: break;
+    case ID_DAP_Vendor30: break;
+    case ID_DAP_Vendor31: break;
+  }
+
+  return (num);
+}
+
+///@}

CMSIS/DAP/Firmware/Source/JTAG_DP.c

@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        1. December 2017
+ * $Revision:    V2.0.0
+ *
+ * Project:      CMSIS-DAP Source
+ * Title:        JTAG_DP.c CMSIS-DAP JTAG DP I/O
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "DAP_config.h"
+#include "DAP.h"
+
+
+// JTAG Macros
+
+#define PIN_TCK_SET PIN_SWCLK_TCK_SET
+#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR
+#define PIN_TMS_SET PIN_SWDIO_TMS_SET
+#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR
+
+#define JTAG_CYCLE_TCK()                \
+  PIN_TCK_CLR();                        \
+  PIN_DELAY();                          \
+  PIN_TCK_SET();                        \
+  PIN_DELAY()
+
+#define JTAG_CYCLE_TDI(tdi)             \
+  PIN_TDI_OUT(tdi);                     \
+  PIN_TCK_CLR();                        \
+  PIN_DELAY();                          \
+  PIN_TCK_SET();                        \
+  PIN_DELAY()
+
+#define JTAG_CYCLE_TDO(tdo)             \
+  PIN_TCK_CLR();                        \
+  PIN_DELAY();                          \
+  tdo = PIN_TDO_IN();                   \
+  PIN_TCK_SET();                        \
+  PIN_DELAY()
+
+#define JTAG_CYCLE_TDIO(tdi,tdo)        \
+  PIN_TDI_OUT(tdi);                     \
+  PIN_TCK_CLR();                        \
+  PIN_DELAY();                          \
+  tdo = PIN_TDO_IN();                   \
+  PIN_TCK_SET();                        \
+  PIN_DELAY()
+
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+
+
+#if (DAP_JTAG != 0)
+
+
+// Generate JTAG Sequence
+//   info:   sequence information
+//   tdi:    pointer to TDI generated data
+//   tdo:    pointer to TDO captured data
+//   return: none
+void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo) {
+  uint32_t i_val;
+  uint32_t o_val;
+  uint32_t bit;
+  uint32_t n, k;
+
+  n = info & JTAG_SEQUENCE_TCK;
+  if (n == 0U) {
+    n = 64U;
+  }
+
+  if (info & JTAG_SEQUENCE_TMS) {
+    PIN_TMS_SET();
+  } else {
+    PIN_TMS_CLR();
+  }
+
+  while (n) {
+    i_val = *tdi++;
+    o_val = 0U;
+    for (k = 8U; k && n; k--, n--) {
+      JTAG_CYCLE_TDIO(i_val, bit);
+      i_val >>= 1;
+      o_val >>= 1;
+      o_val  |= bit << 7;
+    }
+    o_val >>= k;
+    if (info & JTAG_SEQUENCE_TDO) {
+      *tdo++ = (uint8_t)o_val;
+    }
+  }
+}
+
+
+// JTAG Set IR
+//   ir:     IR value
+//   return: none
+#define JTAG_IR_Function(speed) /**/                                            \
+static void JTAG_IR_##speed (uint32_t ir) {                                     \
+  uint32_t n;                                                                   \
+                                                                                \
+  PIN_TMS_SET();                                                                \
+  JTAG_CYCLE_TCK();                         /* Select-DR-Scan */                \
+  JTAG_CYCLE_TCK();                         /* Select-IR-Scan */                \
+  PIN_TMS_CLR();                                                                \
+  JTAG_CYCLE_TCK();                         /* Capture-IR */                    \
+  JTAG_CYCLE_TCK();                         /* Shift-IR */                      \
+                                                                                \
+  PIN_TDI_OUT(1U);                                                              \
+  for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) {      \
+    JTAG_CYCLE_TCK();                       /* Bypass before data */            \
+  }                                                                             \
+  for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1U; n; n--) { \
+    JTAG_CYCLE_TDI(ir);                     /* Set IR bits (except last) */     \
+    ir >>= 1;                                                                   \
+  }                                                                             \
+  n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index];                      \
+  if (n) {                                                                      \
+    JTAG_CYCLE_TDI(ir);                     /* Set last IR bit */               \
+    PIN_TDI_OUT(1U);                                                            \
+    for (--n; n; n--) {                                                         \
+      JTAG_CYCLE_TCK();                     /* Bypass after data */             \
+    }                                                                           \
+    PIN_TMS_SET();                                                              \
+    JTAG_CYCLE_TCK();                       /* Bypass & Exit1-IR */             \
+  } else {                                                                      \
+    PIN_TMS_SET();                                                              \
+    JTAG_CYCLE_TDI(ir);                     /* Set last IR bit & Exit1-IR */    \
+  }                                                                             \
+                                                                                \
+  JTAG_CYCLE_TCK();                         /* Update-IR */                     \
+  PIN_TMS_CLR();                                                                \
+  JTAG_CYCLE_TCK();                         /* Idle */                          \
+  PIN_TDI_OUT(1U);                                                              \
+}
+
+
+// JTAG Transfer I/O
+//   request: A[3:2] RnW APnDP
+//   data:    DATA[31:0]
+//   return:  ACK[2:0]
+#define JTAG_TransferFunction(speed)        /**/                                \
+static uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) {        \
+  uint32_t ack;                                                                 \
+  uint32_t bit;                                                                 \
+  uint32_t val;                                                                 \
+  uint32_t n;                                                                   \
+                                                                                \
+  PIN_TMS_SET();                                                                \
+  JTAG_CYCLE_TCK();                         /* Select-DR-Scan */                \
+  PIN_TMS_CLR();                                                                \
+  JTAG_CYCLE_TCK();                         /* Capture-DR */                    \
+  JTAG_CYCLE_TCK();                         /* Shift-DR */                      \
+                                                                                \
+  for (n = DAP_Data.jtag_dev.index; n; n--) {                                   \
+    JTAG_CYCLE_TCK();                       /* Bypass before data */            \
+  }                                                                             \
+                                                                                \
+  JTAG_CYCLE_TDIO(request >> 1, bit);       /* Set RnW, Get ACK.0 */            \
+  ack  = bit << 1;                                                              \
+  JTAG_CYCLE_TDIO(request >> 2, bit);       /* Set A2,  Get ACK.1 */            \
+  ack |= bit << 0;                                                              \
+  JTAG_CYCLE_TDIO(request >> 3, bit);       /* Set A3,  Get ACK.2 */            \
+  ack |= bit << 2;                                                              \
+                                                                                \
+  if (ack != DAP_TRANSFER_OK) {                                                 \
+    /* Exit on error */                                                         \
+    PIN_TMS_SET();                                                              \
+    JTAG_CYCLE_TCK();                       /* Exit1-DR */                      \
+    goto exit;                                                                  \
+  }                                                                             \
+                                                                                \
+  if (request & DAP_TRANSFER_RnW) {                                             \
+    /* Read Transfer */                                                         \
+    val = 0U;                                                                   \
+    for (n = 31U; n; n--) {                                                     \
+      JTAG_CYCLE_TDO(bit);                  /* Get D0..D30 */                   \
+      val  |= bit << 31;                                                        \
+      val >>= 1;                                                                \
+    }                                                                           \
+    n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U;                 \
+    if (n) {                                                                    \
+      JTAG_CYCLE_TDO(bit);                  /* Get D31 */                       \
+      for (--n; n; n--) {                                                       \
+        JTAG_CYCLE_TCK();                   /* Bypass after data */             \
+      }                                                                         \
+      PIN_TMS_SET();                                                            \
+      JTAG_CYCLE_TCK();                     /* Bypass & Exit1-DR */             \
+    } else {                                                                    \
+      PIN_TMS_SET();                                                            \
+      JTAG_CYCLE_TDO(bit);                  /* Get D31 & Exit1-DR */            \
+    }                                                                           \
+    val |= bit << 31;                                                           \
+    if (data) { *data = val; }                                                  \
+  } else {                                                                      \
+    /* Write Transfer */                                                        \
+    val = *data;                                                                \
+    for (n = 31U; n; n--) {                                                     \
+      JTAG_CYCLE_TDI(val);                  /* Set D0..D30 */                   \
+      val >>= 1;                                                                \
+    }                                                                           \
+    n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U;                 \
+    if (n) {                                                                    \
+      JTAG_CYCLE_TDI(val);                  /* Set D31 */                       \
+      for (--n; n; n--) {                                                       \
+        JTAG_CYCLE_TCK();                   /* Bypass after data */             \
+      }                                                                         \
+      PIN_TMS_SET();                                                            \
+      JTAG_CYCLE_TCK();                     /* Bypass & Exit1-DR */             \
+    } else {                                                                    \
+      PIN_TMS_SET();                                                            \
+      JTAG_CYCLE_TDI(val);                  /* Set D31 & Exit1-DR */            \
+    }                                                                           \
+  }                                                                             \
+                                                                                \
+exit:                                                                           \
+  JTAG_CYCLE_TCK();                         /* Update-DR */                     \
+  PIN_TMS_CLR();                                                                \
+  JTAG_CYCLE_TCK();                         /* Idle */                          \
+  PIN_TDI_OUT(1U);                                                              \
+                                                                                \
+  /* Capture Timestamp */                                                       \
+  if (request & DAP_TRANSFER_TIMESTAMP) {                                       \
+    DAP_Data.timestamp = TIMESTAMP_GET();                                       \
+  }                                                                             \
+                                                                                \
+  /* Idle cycles */                                                             \
+  n = DAP_Data.transfer.idle_cycles;                                            \
+  while (n--) {                                                                 \
+    JTAG_CYCLE_TCK();                       /* Idle */                          \
+  }                                                                             \
+                                                                                \
+  return ((uint8_t)ack);                                                        \
+}
+
+
+#undef  PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_FAST()
+JTAG_IR_Function(Fast)
+JTAG_TransferFunction(Fast)
+
+#undef  PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+JTAG_IR_Function(Slow)
+JTAG_TransferFunction(Slow)
+
+
+// JTAG Read IDCODE register
+//   return: value read
+uint32_t JTAG_ReadIDCode (void) {
+  uint32_t bit;
+  uint32_t val;
+  uint32_t n;
+
+  PIN_TMS_SET();
+  JTAG_CYCLE_TCK();                         /* Select-DR-Scan */
+  PIN_TMS_CLR();
+  JTAG_CYCLE_TCK();                         /* Capture-DR */
+  JTAG_CYCLE_TCK();                         /* Shift-DR */
+
+  for (n = DAP_Data.jtag_dev.index; n; n--) {
+    JTAG_CYCLE_TCK();                       /* Bypass before data */
+  }
+
+  val = 0U;
+  for (n = 31U; n; n--) {
+    JTAG_CYCLE_TDO(bit);                    /* Get D0..D30 */
+    val  |= bit << 31;
+    val >>= 1;
+  }
+  PIN_TMS_SET();
+  JTAG_CYCLE_TDO(bit);                      /* Get D31 & Exit1-DR */
+  val |= bit << 31;
+
+  JTAG_CYCLE_TCK();                         /* Update-DR */
+  PIN_TMS_CLR();
+  JTAG_CYCLE_TCK();                         /* Idle */
+
+  return (val);
+}
+
+
+// JTAG Write ABORT register
+//   data:   value to write
+//   return: none
+void JTAG_WriteAbort (uint32_t data) {
+  uint32_t n;
+
+  PIN_TMS_SET();
+  JTAG_CYCLE_TCK();                         /* Select-DR-Scan */
+  PIN_TMS_CLR();
+  JTAG_CYCLE_TCK();                         /* Capture-DR */
+  JTAG_CYCLE_TCK();                         /* Shift-DR */
+
+  for (n = DAP_Data.jtag_dev.index; n; n--) {
+    JTAG_CYCLE_TCK();                       /* Bypass before data */
+  }
+
+  PIN_TDI_OUT(0U);
+  JTAG_CYCLE_TCK();                         /* Set RnW=0 (Write) */
+  JTAG_CYCLE_TCK();                         /* Set A2=0 */
+  JTAG_CYCLE_TCK();                         /* Set A3=0 */
+
+  for (n = 31U; n; n--) {
+    JTAG_CYCLE_TDI(data);                   /* Set D0..D30 */
+    data >>= 1;
+  }
+  n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U;
+  if (n) {
+    JTAG_CYCLE_TDI(data);                   /* Set D31 */
+    for (--n; n; n--) {
+      JTAG_CYCLE_TCK();                     /* Bypass after data */
+    }
+    PIN_TMS_SET();
+    JTAG_CYCLE_TCK();                       /* Bypass & Exit1-DR */
+  } else {
+    PIN_TMS_SET();
+    JTAG_CYCLE_TDI(data);                   /* Set D31 & Exit1-DR */
+  }
+
+  JTAG_CYCLE_TCK();                         /* Update-DR */
+  PIN_TMS_CLR();
+  JTAG_CYCLE_TCK();                         /* Idle */
+  PIN_TDI_OUT(1U);
+}
+
+
+// JTAG Set IR
+//   ir:     IR value
+//   return: none
+void JTAG_IR (uint32_t ir) {
+  if (DAP_Data.fast_clock) {
+    JTAG_IR_Fast(ir);
+  } else {
+    JTAG_IR_Slow(ir);
+  }
+}
+
+
+// JTAG Transfer I/O
+//   request: A[3:2] RnW APnDP
+//   data:    DATA[31:0]
+//   return:  ACK[2:0]
+uint8_t  JTAG_Transfer(uint32_t request, uint32_t *data) {
+  if (DAP_Data.fast_clock) {
+    return JTAG_TransferFast(request, data);
+  } else {
+    return JTAG_TransferSlow(request, data);
+  }
+}
+
+
+#endif  /* (DAP_JTAG != 0) */

CMSIS/DAP/Firmware/Source/SWO.c

@@ -0,0 +1,800 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        1. December 2017
+ * $Revision:    V2.0.0
+ *
+ * Project:      CMSIS-DAP Source
+ * Title:        SWO.c CMSIS-DAP SWO I/O
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "DAP_config.h"
+#include "DAP.h"
+#if (SWO_UART != 0)
+#include "Driver_USART.h"
+#endif
+#if (SWO_STREAM != 0)
+#include "cmsis_os2.h"
+#endif
+
+#if (SWO_STREAM != 0)
+#ifdef DAP_FW_V1
+#error "SWO Streaming Trace not supported in DAP V1!"
+#endif
+#endif
+
+#if (SWO_UART != 0)
+
+#ifndef  USART_PORT
+#define  USART_PORT 0           /* USART Port Number */
+#endif
+
+// USART Driver
+#define _USART_Driver_(n)  Driver_USART##n
+#define  USART_Driver_(n) _USART_Driver_(n)
+extern ARM_DRIVER_USART    USART_Driver_(USART_PORT);
+#define pUSART           (&USART_Driver_(USART_PORT))
+
+static uint8_t USART_Ready = 0U;
+
+#endif  /* (SWO_UART != 0) */
+
+
+#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0))
+
+
+#define SWO_STREAM_TIMEOUT      50U     /* Stream timeout in ms */
+
+#define USB_BLOCK_SIZE          512U    /* USB Block Size */
+#define TRACE_BLOCK_SIZE        64U     /* Trace Block Size (2^n: 32...512) */
+
+// Trace State
+static uint8_t  TraceTransport =  0U;       /* Trace Transport */
+static uint8_t  TraceMode      =  0U;       /* Trace Mode */
+static uint8_t  TraceStatus    =  0U;       /* Trace Status without Errors */
+static uint8_t  TraceError[2]  = {0U, 0U};  /* Trace Error flags (banked) */
+static uint8_t  TraceError_n   =  0U;       /* Active Trace Error bank */
+
+// Trace Buffer
+static uint8_t  TraceBuf[SWO_BUFFER_SIZE];  /* Trace Buffer (must be 2^n) */
+static volatile uint32_t TraceIndexI  = 0U; /* Incoming Trace Index */
+static volatile uint32_t TraceIndexO  = 0U; /* Outgoing Trace Index */
+static volatile uint8_t  TraceUpdate;       /* Trace Update Flag */
+static          uint32_t TraceBlockSize;    /* Current Trace Block Size */
+
+#if (TIMESTAMP_CLOCK != 0U) 
+// Trace Timestamp
+static volatile struct {
+  uint32_t index;
+  uint32_t tick;
+} TraceTimestamp;
+#endif
+
+// Trace Helper functions
+static void     ClearTrace     (void);
+static void     ResumeTrace    (void);
+static uint32_t GetTraceCount  (void);
+static uint8_t  GetTraceStatus (void);
+static void     SetTraceError  (uint8_t flag);
+
+#if (SWO_STREAM != 0)
+extern osThreadId_t      SWO_ThreadId;
+static volatile uint8_t  TransferBusy = 0U; /* Transfer Busy Flag */
+static          uint32_t TransferSize;      /* Current Transfer Size */
+#endif
+
+
+#if (SWO_UART != 0)
+
+// USART Driver Callback function
+//   event: event mask
+static void USART_Callback (uint32_t event) {
+  uint32_t index_i;
+  uint32_t index_o;
+  uint32_t count;
+  uint32_t num;
+
+  if (event &  ARM_USART_EVENT_RECEIVE_COMPLETE) {
+#if (TIMESTAMP_CLOCK != 0U) 
+    TraceTimestamp.tick = TIMESTAMP_GET();
+#endif
+    index_o  = TraceIndexO;
+    index_i  = TraceIndexI;
+    index_i += TraceBlockSize;
+    TraceIndexI = index_i;
+#if (TIMESTAMP_CLOCK != 0U) 
+    TraceTimestamp.index = index_i;
+#endif
+    num   = TRACE_BLOCK_SIZE - (index_i & (TRACE_BLOCK_SIZE - 1U));
+    count = index_i - index_o;
+    if (count <= (SWO_BUFFER_SIZE - num)) {
+      index_i &= SWO_BUFFER_SIZE - 1U;
+      TraceBlockSize = num;
+      pUSART->Receive(&TraceBuf[index_i], num);
+    } else {
+      TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED;
+    }
+    TraceUpdate = 1U;
+#if (SWO_STREAM != 0)
+    if (TraceTransport == 2U) {
+      if (count >= (USB_BLOCK_SIZE - (index_o & (USB_BLOCK_SIZE - 1U)))) {
+        osThreadFlagsSet(SWO_ThreadId, 1U);
+      }
+    }
+#endif
+  }
+  if (event &  ARM_USART_EVENT_RX_OVERFLOW) {
+    SetTraceError(DAP_SWO_BUFFER_OVERRUN);
+  }
+  if (event & (ARM_USART_EVENT_RX_BREAK         |
+               ARM_USART_EVENT_RX_FRAMING_ERROR |
+               ARM_USART_EVENT_RX_PARITY_ERROR)) {
+    SetTraceError(DAP_SWO_STREAM_ERROR);
+  }
+}
+
+// Enable or disable UART SWO Mode
+//   enable: enable flag
+//   return: 1 - Success, 0 - Error
+__WEAK uint32_t UART_SWO_Mode (uint32_t enable) {
+  int32_t status;
+
+  USART_Ready = 0U;
+
+  if (enable != 0U) {
+    status = pUSART->Initialize(USART_Callback);
+    if (status != ARM_DRIVER_OK) {
+      return (0U);
+    }
+    status = pUSART->PowerControl(ARM_POWER_FULL);
+    if (status != ARM_DRIVER_OK) {
+      pUSART->Uninitialize();
+      return (0U);
+    }
+  } else {
+    pUSART->Control(ARM_USART_CONTROL_RX, 0U);
+    pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+    pUSART->PowerControl(ARM_POWER_OFF);
+    pUSART->Uninitialize();
+  }
+  return (1U);
+}
+
+// Configure UART SWO Baudrate
+//   baudrate: requested baudrate
+//   return:   actual baudrate or 0 when not configured
+__WEAK uint32_t UART_SWO_Baudrate (uint32_t baudrate) {
+  int32_t  status;
+  uint32_t index;
+  uint32_t num;
+
+  if (baudrate > SWO_UART_MAX_BAUDRATE) {
+    baudrate = SWO_UART_MAX_BAUDRATE;
+  }
+
+  if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
+    pUSART->Control(ARM_USART_CONTROL_RX, 0U);
+    if (pUSART->GetStatus().rx_busy) {
+      TraceIndexI += pUSART->GetRxCount();
+      pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+    }
+  }
+
+  status = pUSART->Control(ARM_USART_MODE_ASYNCHRONOUS |
+                           ARM_USART_DATA_BITS_8       |
+                           ARM_USART_PARITY_NONE       |
+                           ARM_USART_STOP_BITS_1,
+                           baudrate);
+
+  if (status == ARM_DRIVER_OK) {
+    USART_Ready = 1U;
+  } else {
+    USART_Ready = 0U;
+    return (0U);
+  }
+
+  if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
+    if ((TraceStatus & DAP_SWO_CAPTURE_PAUSED) == 0U) {
+      index = TraceIndexI & (SWO_BUFFER_SIZE - 1U);
+      num = TRACE_BLOCK_SIZE - (index & (TRACE_BLOCK_SIZE - 1U));
+      TraceBlockSize = num;
+      pUSART->Receive(&TraceBuf[index], num);
+    }
+    pUSART->Control(ARM_USART_CONTROL_RX, 1U);
+  }
+
+  return (baudrate);
+}
+
+// Control UART SWO Capture
+//   active: active flag
+//   return: 1 - Success, 0 - Error
+__WEAK uint32_t UART_SWO_Control (uint32_t active) {
+  int32_t status;
+
+  if (active) {
+    if (!USART_Ready) { 
+      return (0U);
+    }
+    TraceBlockSize = 1U;
+    status = pUSART->Receive(&TraceBuf[0], 1U);
+    if (status != ARM_DRIVER_OK) {
+      return (0U);
+    }
+    status = pUSART->Control(ARM_USART_CONTROL_RX, 1U);
+    if (status != ARM_DRIVER_OK) {
+      return (0U);
+    }
+  } else {
+    pUSART->Control(ARM_USART_CONTROL_RX, 0U);
+    if (pUSART->GetStatus().rx_busy) {
+      TraceIndexI += pUSART->GetRxCount();
+      pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
+    }
+  }
+  return (1U);
+}
+
+// Start UART SWO Capture
+//   buf: pointer to buffer for capturing
+//   num: number of bytes to capture
+__WEAK void UART_SWO_Capture (uint8_t *buf, uint32_t num) {
+  TraceBlockSize = num;
+  pUSART->Receive(buf, num);
+}
+
+// Get UART SWO Pending Trace Count
+//   return: number of pending trace data bytes
+__WEAK uint32_t UART_SWO_GetCount (void) {
+  uint32_t count;
+
+  if (pUSART->GetStatus().rx_busy) {
+    count = pUSART->GetRxCount();
+  } else {
+    count = 0U;
+  }
+  return (count);
+}
+
+#endif  /* (SWO_UART != 0) */
+
+
+#if (SWO_MANCHESTER != 0)
+
+// Enable or disable Manchester SWO Mode
+//   enable: enable flag
+//   return: 1 - Success, 0 - Error
+__WEAK uint32_t Manchester_SWO_Mode (uint32_t enable) {
+  return (0U);
+}
+
+// Configure Manchester SWO Baudrate
+//   baudrate: requested baudrate
+//   return:   actual baudrate or 0 when not configured
+__WEAK uint32_t Manchester_SWO_Baudrate (uint32_t baudrate) {
+  return (0U);
+}
+
+// Control Manchester SWO Capture
+//   active: active flag
+//   return: 1 - Success, 0 - Error
+__WEAK uint32_t Manchester_SWO_Control (uint32_t active) {
+  return (0U);
+}
+
+// Start Manchester SWO Capture
+//   buf: pointer to buffer for capturing
+//   num: number of bytes to capture
+__WEAK void Manchester_SWO_Capture (uint8_t *buf, uint32_t num) {
+}
+
+// Get Manchester SWO Pending Trace Count
+//   return: number of pending trace data bytes
+__WEAK uint32_t Manchester_SWO_GetCount (void) {
+}
+
+#endif  /* (SWO_MANCHESTER != 0) */
+
+
+// Clear Trace Errors and Data
+static void ClearTrace (void) {
+
+#if (SWO_STREAM != 0)
+  if (TraceTransport == 2U) {
+    if (TransferBusy != 0U) {
+      SWO_AbortTransfer();
+      TransferBusy = 0U;
+    }
+  }
+#endif
+
+  TraceError[0] = 0U;
+  TraceError[1] = 0U;
+  TraceError_n  = 0U;
+  TraceIndexI   = 0U;
+  TraceIndexO   = 0U;
+
+#if (TIMESTAMP_CLOCK != 0U) 
+  TraceTimestamp.index = 0U;
+  TraceTimestamp.tick  = 0U;
+#endif
+}
+
+// Resume Trace Capture
+static void ResumeTrace (void) {
+  uint32_t index_i;
+  uint32_t index_o;
+
+  if (TraceStatus == (DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED)) {
+    index_i = TraceIndexI;
+    index_o = TraceIndexO;
+    if ((index_i - index_o) < SWO_BUFFER_SIZE) {
+      index_i &= SWO_BUFFER_SIZE - 1U;
+      switch (TraceMode) {
+#if (SWO_UART != 0)
+        case DAP_SWO_UART:
+          TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
+          UART_SWO_Capture(&TraceBuf[index_i], 1U);
+          break;
+#endif
+#if (SWO_MANCHESTER != 0)
+        case DAP_SWO_MANCHESTER:
+          TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
+          Manchester_SWO_Capture(&TraceBuf[index_i], 1U);
+          break;
+#endif
+        default:
+          break;
+      }
+    }
+  }
+}
+
+// Get Trace Count
+//   return: number of available data bytes in trace buffer
+static uint32_t GetTraceCount (void) {
+  uint32_t count;
+
+  if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) {
+    do {
+      TraceUpdate = 0U;
+      count = TraceIndexI - TraceIndexO;
+      switch (TraceMode) {
+#if (SWO_UART != 0)
+        case DAP_SWO_UART:
+          count += UART_SWO_GetCount();
+          break;
+#endif
+#if (SWO_MANCHESTER != 0)
+        case DAP_SWO_MANCHESTER:
+          count += Manchester_SWO_GetCount();
+          break;
+#endif
+        default:
+          break;
+      }
+    } while (TraceUpdate != 0U);
+  } else {
+    count = TraceIndexI - TraceIndexO;
+  }
+
+  return (count);
+}
+
+// Get Trace Status (clear Error flags)
+//   return: Trace Status (Active flag and Error flags)
+static uint8_t GetTraceStatus (void) {
+  uint8_t  status;
+  uint32_t n;
+
+  n = TraceError_n;
+  TraceError_n ^= 1U;
+  status = TraceStatus | TraceError[n];
+  TraceError[n] = 0U;
+
+  return (status);
+}
+
+// Set Trace Error flag(s)
+//   flag:  error flag(s) to set
+static void SetTraceError (uint8_t flag) {
+  TraceError[TraceError_n] |= flag;
+}
+
+
+// Process SWO Transport command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_Transport (const uint8_t *request, uint8_t *response) {
+  uint8_t  transport;
+  uint32_t result;
+
+  if ((TraceStatus & DAP_SWO_CAPTURE_ACTIVE) == 0U) {
+    transport = *request;
+    switch (transport) {
+      case 0U:
+      case 1U:
+#if (SWO_STREAM != 0)
+      case 2U:
+#endif
+        TraceTransport = transport;
+        result = 1U;
+        break;
+      default:
+        result = 0U;
+        break;
+    }
+  } else {
+    result = 0U;
+  }
+
+  if (result != 0U) {
+    *response = DAP_OK;
+  } else {
+    *response = DAP_ERROR;
+  }
+
+  return ((1U << 16) | 1U);
+}
+
+
+// Process SWO Mode command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) {
+  uint8_t  mode;
+  uint32_t result;
+
+  mode = *request;
+
+  switch (TraceMode) {
+#if (SWO_UART != 0)
+    case DAP_SWO_UART:
+      UART_SWO_Mode(0U);
+      break;
+#endif
+#if (SWO_MANCHESTER != 0)
+    case DAP_SWO_MANCHESTER:
+      Manchester_SWO_Mode(0U);
+      break;
+#endif
+    default:
+      break;
+  }
+
+  switch (mode) {
+    case DAP_SWO_OFF:
+      result = 1U;
+      break;
+#if (SWO_UART != 0)
+    case DAP_SWO_UART:
+      result = UART_SWO_Mode(1U);
+      break;
+#endif
+#if (SWO_MANCHESTER != 0)
+    case DAP_SWO_MANCHESTER:
+      result = Manchester_SWO_Mode(1U);
+      break;
+#endif
+    default:
+      result = 0U;
+      break;
+  }
+  if (result != 0U) {
+    TraceMode = mode;
+  } else {
+    TraceMode = DAP_SWO_OFF;
+  }
+
+  TraceStatus = 0U;
+
+  if (result != 0U) {
+    *response = DAP_OK;
+  } else {
+    *response = DAP_ERROR;
+  }
+
+  return ((1U << 16) | 1U);
+}
+
+
+// Process SWO Baudrate command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) {
+  uint32_t baudrate;
+
+  baudrate = (uint32_t)(*(request+0) <<  0) |
+             (uint32_t)(*(request+1) <<  8) |
+             (uint32_t)(*(request+2) << 16) |
+             (uint32_t)(*(request+3) << 24);
+
+  switch (TraceMode) {
+#if (SWO_UART != 0)
+    case DAP_SWO_UART:
+      baudrate = UART_SWO_Baudrate(baudrate);
+      break;
+#endif
+#if (SWO_MANCHESTER != 0)
+    case DAP_SWO_MANCHESTER:
+      baudrate = Manchester_SWO_Baudrate(baudrate);
+      break;
+#endif
+    default:
+      baudrate = 0U;
+      break;
+  }
+
+  if (baudrate == 0U) {
+    TraceStatus = 0U;
+  }
+
+  *response++ = (uint8_t)(baudrate >>  0);
+  *response++ = (uint8_t)(baudrate >>  8);
+  *response++ = (uint8_t)(baudrate >> 16);
+  *response   = (uint8_t)(baudrate >> 24);
+
+  return ((4U << 16) | 4U);
+}
+
+
+// Process SWO Control command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_Control (const uint8_t *request, uint8_t *response) {
+  uint8_t  active;
+  uint32_t result;
+
+  active = *request & DAP_SWO_CAPTURE_ACTIVE;
+
+  if (active != (TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) {
+    if (active) {
+      ClearTrace();
+    }
+    switch (TraceMode) {
+#if (SWO_UART != 0)
+      case DAP_SWO_UART:
+        result = UART_SWO_Control(active);
+        break;
+#endif
+#if (SWO_MANCHESTER != 0)
+      case DAP_SWO_MANCHESTER:
+        result = Manchester_SWO_Control(active);
+        break;
+#endif
+      default:
+        result = 0U;
+        break;
+    }
+    if (result != 0U) {
+      TraceStatus = active;
+#if (SWO_STREAM != 0)
+      if (TraceTransport == 2U) {
+        osThreadFlagsSet(SWO_ThreadId, 1U);
+      }
+#endif
+    }
+  } else {
+    result = 1U;
+  }
+
+  if (result != 0U) {
+    *response = DAP_OK;
+  } else {
+    *response = DAP_ERROR;
+  }
+
+  return ((1U << 16) | 1U);
+}
+
+
+// Process SWO Status command and prepare response
+//   response: pointer to response data
+//   return:   number of bytes in response
+uint32_t SWO_Status (uint8_t *response) {
+  uint8_t  status;
+  uint32_t count;
+
+  status = GetTraceStatus();
+  count  = GetTraceCount();
+
+  *response++ = status;
+  *response++ = (uint8_t)(count >>  0);
+  *response++ = (uint8_t)(count >>  8);
+  *response++ = (uint8_t)(count >> 16);
+  *response   = (uint8_t)(count >> 24);
+
+  return (5U);
+}
+
+
+// Process SWO Extended Status command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_ExtendedStatus (const uint8_t *request, uint8_t *response) {
+  uint8_t  cmd;
+  uint8_t  status;
+  uint32_t count;
+#if (TIMESTAMP_CLOCK != 0U) 
+  uint32_t index;
+  uint32_t tick;
+#endif
+  uint32_t num;
+
+  num = 0U;
+  cmd = *request;
+
+  if (cmd & 0x01U) {
+    status = GetTraceStatus();
+    *response++ = status;
+    num += 1U;
+  }
+
+  if (cmd & 0x02U) {
+    count = GetTraceCount();
+    *response++ = (uint8_t)(count >>  0);
+    *response++ = (uint8_t)(count >>  8);
+    *response++ = (uint8_t)(count >> 16);
+    *response++ = (uint8_t)(count >> 24);
+    num += 4U;
+  }
+
+#if (TIMESTAMP_CLOCK != 0U) 
+  if (cmd & 0x04U) {
+    do {
+      TraceUpdate = 0U;
+      index = TraceTimestamp.index;
+      tick  = TraceTimestamp.tick;
+    } while (TraceUpdate != 0U);
+    *response++ = (uint8_t)(index >>  0);
+    *response++ = (uint8_t)(index >>  8);
+    *response++ = (uint8_t)(index >> 16);
+    *response++ = (uint8_t)(index >> 24);
+    *response++ = (uint8_t)(tick  >>  0);
+    *response++ = (uint8_t)(tick  >>  8);
+    *response++ = (uint8_t)(tick  >> 16);
+    *response++ = (uint8_t)(tick  >> 24);
+    num += 4U;
+  }
+#endif
+
+  return ((1U << 16) | num);
+}
+
+
+// Process SWO Data command and prepare response
+//   request:  pointer to request data
+//   response: pointer to response data
+//   return:   number of bytes in response (lower 16 bits)
+//             number of bytes in request (upper 16 bits)
+uint32_t SWO_Data (const uint8_t *request, uint8_t *response) {
+  uint8_t  status;
+  uint32_t count;
+  uint32_t index;
+  uint32_t n, i;
+
+  status = GetTraceStatus();
+  count  = GetTraceCount();
+
+  if (TraceTransport == 1U) {
+    n = (uint32_t)(*(request+0) << 0) |
+        (uint32_t)(*(request+1) << 8);
+    if (n > (DAP_PACKET_SIZE - 4U)) {
+      n = DAP_PACKET_SIZE - 4U;
+    }
+    if (count > n) {
+      count = n;
+    }
+  } else {
+    count = 0U;
+  }
+
+  *response++ = status;
+  *response++ = (uint8_t)(count >> 0);
+  *response++ = (uint8_t)(count >> 8);
+
+  if (TraceTransport == 1U) {
+    index = TraceIndexO;
+    for (i = index, n = count; n; n--) {
+      i &= SWO_BUFFER_SIZE - 1U;
+      *response++ = TraceBuf[i++];
+    }
+    TraceIndexO = index + count;
+    ResumeTrace();
+  }
+
+  return ((2U << 16) | (3U + count));
+}
+
+
+#if (SWO_STREAM != 0)
+
+// SWO Data Transfer complete callback
+void SWO_TransferComplete (void) {
+  TraceIndexO += TransferSize;
+  TransferBusy = 0U;
+  ResumeTrace();
+  osThreadFlagsSet(SWO_ThreadId, 1U);
+}
+
+// SWO Thread
+__NO_RETURN void SWO_Thread (void *argument) {
+  uint32_t timeout;
+  uint32_t flags;
+  uint32_t count;
+  uint32_t index;
+  uint32_t i, n;
+  (void)   argument;
+
+  timeout = osWaitForever;
+
+  for (;;) {
+    flags = osThreadFlagsWait(1U, osFlagsWaitAny, timeout);
+    if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
+      timeout = SWO_STREAM_TIMEOUT;
+    } else {
+      timeout = osWaitForever;
+      flags   = osFlagsErrorTimeout;
+    }
+    if (TransferBusy == 0U) {
+      count = GetTraceCount();
+      if (count != 0U) {
+        index = TraceIndexO & (SWO_BUFFER_SIZE - 1U);
+        n = SWO_BUFFER_SIZE - index;
+        if (count > n) {
+          count = n;
+        }
+        if (flags != osFlagsErrorTimeout) {
+          i = index & (USB_BLOCK_SIZE - 1U);
+          if (i == 0U) {
+            count &= ~(USB_BLOCK_SIZE - 1U);
+          } else {
+            n = USB_BLOCK_SIZE - i;
+            if (count >= n) {
+              count = n;
+            } else {
+              count = 0U;
+            }
+          }
+        }
+        if (count != 0U) {
+          TransferSize = count;
+          TransferBusy = 1U;
+          SWO_QueueTransfer(&TraceBuf[index], count);
+        }
+      }
+    }
+  }
+}
+
+#endif  /* (SWO_STREAM != 0) */
+
+
+#endif  /* ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) */

CMSIS/DAP/Firmware/Source/SW_DP.c

@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------
+ *
+ * $Date:        1. December 2017
+ * $Revision:    V2.0.0
+ *
+ * Project:      CMSIS-DAP Source
+ * Title:        SW_DP.c CMSIS-DAP SW DP I/O
+ *
+ *---------------------------------------------------------------------------*/
+
+#include "DAP_config.h"
+#include "DAP.h"
+
+
+// SW Macros
+
+#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET
+#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR
+
+#define SW_CLOCK_CYCLE()                \
+  PIN_SWCLK_CLR();                      \
+  PIN_DELAY();                          \
+  PIN_SWCLK_SET();                      \
+  PIN_DELAY()
+
+#define SW_WRITE_BIT(bit)               \
+  PIN_SWDIO_OUT(bit);                   \
+  PIN_SWCLK_CLR();                      \
+  PIN_DELAY();                          \
+  PIN_SWCLK_SET();                      \
+  PIN_DELAY()
+
+#define SW_READ_BIT(bit)                \
+  PIN_SWCLK_CLR();                      \
+  PIN_DELAY();                          \
+  bit = PIN_SWDIO_IN();                 \
+  PIN_SWCLK_SET();                      \
+  PIN_DELAY()
+
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+
+
+// Generate SWJ Sequence
+//   count:  sequence bit count
+//   data:   pointer to sequence bit data
+//   return: none
+#if ((DAP_SWD != 0) || (DAP_JTAG != 0))
+void SWJ_Sequence (uint32_t count, const uint8_t *data) {
+  uint32_t val;
+  uint32_t n;
+
+  val = 0U;
+  n = 0U;
+  while (count--) {
+    if (n == 0U) {
+      val = *data++;
+      n = 8U;
+    }
+    if (val & 1U) {
+      PIN_SWDIO_TMS_SET();
+    } else {
+      PIN_SWDIO_TMS_CLR();
+    }
+    SW_CLOCK_CYCLE();
+    val >>= 1;
+    n--;
+  }
+}
+#endif
+
+
+// Generate SWD Sequence
+//   info:   sequence information
+//   swdo:   pointer to SWDIO generated data
+//   swdi:   pointer to SWDIO captured data
+//   return: none
+#if (DAP_SWD != 0)
+void SWD_Sequence (uint32_t info, const uint8_t *swdo, uint8_t *swdi) {
+  uint32_t val;
+  uint32_t bit;
+  uint32_t n, k;
+
+  n = info & SWD_SEQUENCE_CLK;
+  if (n == 0U) {
+    n = 64U;
+  }
+
+  if (info & SWD_SEQUENCE_DIN) {
+    while (n) {
+      val = 0U;
+      for (k = 8U; k && n; k--, n--) {
+        SW_READ_BIT(bit);
+        val >>= 1;
+        val  |= bit << 7;
+      }
+      val >>= k;
+      *swdi++ = (uint8_t)val;
+    }
+  } else {
+    while (n) {
+      val = *swdo++;
+      for (k = 8U; k && n; k--, n--) {
+        SW_WRITE_BIT(val);
+        val >>= 1;
+      }
+    }
+  }
+}
+#endif
+
+
+#if (DAP_SWD != 0)
+
+
+// SWD Transfer I/O
+//   request: A[3:2] RnW APnDP
+//   data:    DATA[31:0]
+//   return:  ACK[2:0]
+#define SWD_TransferFunction(speed)     /**/                                    \
+static uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) {         \
+  uint32_t ack;                                                                 \
+  uint32_t bit;                                                                 \
+  uint32_t val;                                                                 \
+  uint32_t parity;                                                              \
+                                                                                \
+  uint32_t n;                                                                   \
+                                                                                \
+  /* Packet Request */                                                          \
+  parity = 0U;                                                                  \
+  SW_WRITE_BIT(1U);                     /* Start Bit */                         \
+  bit = request >> 0;                                                           \
+  SW_WRITE_BIT(bit);                    /* APnDP Bit */                         \
+  parity += bit;                                                                \
+  bit = request >> 1;                                                           \
+  SW_WRITE_BIT(bit);                    /* RnW Bit */                           \
+  parity += bit;                                                                \
+  bit = request >> 2;                                                           \
+  SW_WRITE_BIT(bit);                    /* A2 Bit */                            \
+  parity += bit;                                                                \
+  bit = request >> 3;                                                           \
+  SW_WRITE_BIT(bit);                    /* A3 Bit */                            \
+  parity += bit;                                                                \
+  SW_WRITE_BIT(parity);                 /* Parity Bit */                        \
+  SW_WRITE_BIT(0U);                     /* Stop Bit */                          \
+  SW_WRITE_BIT(1U);                     /* Park Bit */                          \
+                                                                                \
+  /* Turnaround */                                                              \
+  PIN_SWDIO_OUT_DISABLE();                                                      \
+  for (n = DAP_Data.swd_conf.turnaround; n; n--) {                              \
+    SW_CLOCK_CYCLE();                                                           \
+  }                                                                             \
+                                                                                \
+  /* Acknowledge response */                                                    \
+  SW_READ_BIT(bit);                                                             \
+  ack  = bit << 0;                                                              \
+  SW_READ_BIT(bit);                                                             \
+  ack |= bit << 1;                                                              \
+  SW_READ_BIT(bit);                                                             \
+  ack |= bit << 2;                                                              \
+                                                                                \
+  if (ack == DAP_TRANSFER_OK) {         /* OK response */                       \
+    /* Data transfer */                                                         \
+    if (request & DAP_TRANSFER_RnW) {                                           \
+      /* Read data */                                                           \
+      val = 0U;                                                                 \
+      parity = 0U;                                                              \
+      for (n = 32U; n; n--) {                                                   \
+        SW_READ_BIT(bit);               /* Read RDATA[0:31] */                  \
+        parity += bit;                                                          \
+        val >>= 1;                                                              \
+        val  |= bit << 31;                                                      \
+      }                                                                         \
+      SW_READ_BIT(bit);                 /* Read Parity */                       \
+      if ((parity ^ bit) & 1U) {                                                \
+        ack = DAP_TRANSFER_ERROR;                                               \
+      }                                                                         \
+      if (data) { *data = val; }                                                \
+      /* Turnaround */                                                          \
+      for (n = DAP_Data.swd_conf.turnaround; n; n--) {                          \
+        SW_CLOCK_CYCLE();                                                       \
+      }                                                                         \
+      PIN_SWDIO_OUT_ENABLE();                                                   \
+    } else {                                                                    \
+      /* Turnaround */                                                          \
+      for (n = DAP_Data.swd_conf.turnaround; n; n--) {                          \
+        SW_CLOCK_CYCLE();                                                       \
+      }                                                                         \
+      PIN_SWDIO_OUT_ENABLE();                                                   \
+      /* Write data */                                                          \
+      val = *data;                                                              \
+      parity = 0U;                                                              \
+      for (n = 32U; n; n--) {                                                   \
+        SW_WRITE_BIT(val);              /* Write WDATA[0:31] */                 \
+        parity += val;                                                          \
+        val >>= 1;                                                              \
+      }                                                                         \
+      SW_WRITE_BIT(parity);             /* Write Parity Bit */                  \
+    }                                                                           \
+    /* Capture Timestamp */                                                     \
+    if (request & DAP_TRANSFER_TIMESTAMP) {                                     \
+      DAP_Data.timestamp = TIMESTAMP_GET();                                     \
+    }                                                                           \
+    /* Idle cycles */                                                           \
+    n = DAP_Data.transfer.idle_cycles;                                          \
+    if (n) {                                                                    \
+      PIN_SWDIO_OUT(0U);                                                        \
+      for (; n; n--) {                                                          \
+        SW_CLOCK_CYCLE();                                                       \
+      }                                                                         \
+    }                                                                           \
+    PIN_SWDIO_OUT(1U);                                                          \
+    return ((uint8_t)ack);                                                      \
+  }                                                                             \
+                                                                                \
+  if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) {              \
+    /* WAIT or FAULT response */                                                \
+    if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0U)) { \
+      for (n = 32U+1U; n; n--) {                                                \
+        SW_CLOCK_CYCLE();               /* Dummy Read RDATA[0:31] + Parity */   \
+      }                                                                         \
+    }                                                                           \
+    /* Turnaround */                                                            \
+    for (n = DAP_Data.swd_conf.turnaround; n; n--) {                            \
+      SW_CLOCK_CYCLE();                                                         \
+    }                                                                           \
+    PIN_SWDIO_OUT_ENABLE();                                                     \
+    if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0U)) { \
+      PIN_SWDIO_OUT(0U);                                                        \
+      for (n = 32U+1U; n; n--) {                                                \
+        SW_CLOCK_CYCLE();               /* Dummy Write WDATA[0:31] + Parity */  \
+      }                                                                         \
+    }                                                                           \
+    PIN_SWDIO_OUT(1U);                                                          \
+    return ((uint8_t)ack);                                                      \
+  }                                                                             \
+                                                                                \
+  /* Protocol error */                                                          \
+  for (n = DAP_Data.swd_conf.turnaround + 32U + 1U; n; n--) {                   \
+    SW_CLOCK_CYCLE();                   /* Back off data phase */               \
+  }                                                                             \
+  PIN_SWDIO_OUT_ENABLE();                                                       \
+  PIN_SWDIO_OUT(1U);                                                            \
+  return ((uint8_t)ack);                                                        \
+}
+
+
+#undef  PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_FAST()
+SWD_TransferFunction(Fast)
+
+#undef  PIN_DELAY
+#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
+SWD_TransferFunction(Slow)
+
+
+// SWD Transfer I/O
+//   request: A[3:2] RnW APnDP
+//   data:    DATA[31:0]
+//   return:  ACK[2:0]
+uint8_t  SWD_Transfer(uint32_t request, uint32_t *data) {
+  if (DAP_Data.fast_clock) {
+    return SWD_TransferFast(request, data);
+  } else {
+    return SWD_TransferSlow(request, data);
+  }
+}
+
+
+#endif  /* (DAP_SWD != 0) */

CMSIS/LICENSE.cmsis

@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
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+
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CMSIS_5

@@ -1 +0,0 @@
-Subproject commit d61cf40e6c44726917d9085660f7eb2691547cc7

CMakeLists.txt

@@ -9,6 +9,8 @@ set(BOARD "raspberry_pi_pico" CACHE STRING "Board used, determines the pinout. D
 get_filename_component(PROJECT ${CMAKE_CURRENT_SOURCE_DIR} NAME)
 set(PROJECT ${BOARD}-${PROJECT})
 
+set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
+
 # TOP is absolute path to root directory of TinyUSB git repo
 set(TOP "./tinyusb")
 get_filename_component(TOP "${TOP}" REALPATH)
@@ -20,7 +22,7 @@ if(FAMILY STREQUAL "rp2040")
   if (USE_SYSTEMWIDE_PICOSDK)
     set(TOP "$ENV{PICO_SDK_PATH}/lib/tinyusb")
     get_filename_component(TOP "${TOP}" REALPATH)
-    include(pico_sdk_import.cmake)
+    include(cmake/pico_sdk_import.cmake)
   else()
     set(PICO_SDK_PATH ${TOP}/hw/mcu/raspberrypi/pico-sdk)
     include(${PICO_SDK_PATH}/pico_sdk_init.cmake)
@@ -53,11 +55,11 @@ endif()
 
 target_sources(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/libco/libco.S
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Source/DAP.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS/DAP/Firmware/Source/DAP.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Source/JTAG_DP.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS/DAP/Firmware/Source/JTAG_DP.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Source/DAP_vendor.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS/DAP/Firmware/Source/DAP_vendor.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Source/SWO.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS/DAP/Firmware/Source/SWO.c
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Source/SW_DP.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS/DAP/Firmware/Source/SW_DP.c
   ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/cdc_uart.c
   ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/i2c_tinyusb.c
   ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/spi_serprog.c
@@ -78,14 +80,17 @@ endif()
 target_include_directories(${PROJECT} PUBLIC
   ${CMAKE_CURRENT_SOURCE_DIR}/src/
   ${CMAKE_CURRENT_SOURCE_DIR}/libco/
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/DAP/Firmware/Include/
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS/DAP/Firmware/Include/
-  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS_5/CMSIS/Core/Include/
+  ${CMAKE_CURRENT_SOURCE_DIR}/CMSIS/Core/Include/
   ${CMAKE_CURRENT_SOURCE_DIR}/bsp/${FAMILY}/
   ${CMAKE_CURRENT_SOURCE_DIR}/bsp/default/
 )
 
-set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall")
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -Wextra")
-set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall")
+set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -Wextra")
+
+add_custom_target(fix_db ALL WORKING_DIRECTORY ${OUTPUT_DIR}
+  COMMAND "${CMAKE_CURRENT_SOURCE_DIR}/scripts/fix_clang_db.py")
 
 if(FAMILY STREQUAL "rp2040")
   target_link_libraries(${PROJECT} pico_stdlib pico_unique_id hardware_spi

COPYING

@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
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+
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+
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+
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+
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+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
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+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
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+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+    <program>  Copyright (C) <year>  <name of author>
+    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<https://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<https://www.gnu.org/licenses/why-not-lgpl.html>.

LICENSE

@@ -0,0 +1 @@
+COPYING

LICENSE.dappermime

@@ -0,0 +1,39 @@
+The below copyright and permission notice applies to portions of the following files, which have
+been modified from their original versions in <https://github.com/majbthrd/DapperMime>
+(the "DapperMime repository")
+
+ - src/tusb_config.h
+ - src/usb_descriptors.c
+ - bsp/rp2040/DAP_config.h
+ - bsp/rp2040/cdc_uart.c
+ - bsp/stm32f072disco/DAP_config.h
+ - bsp/rp2040/board.h
+ - src/main.c
+
+The below notice does not apply to any modifications made to the above files since the versions
+present in the DapperMime repository, nor to any files not present in the DapperMime repository.
+
+
+
+
+The MIT License (MIT)
+
+Copyright (c) 2019 Ha Thach (tinyusb.org)
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.

Makefile

@@ -1,22 +0,0 @@
-include ./tinyusb/tools/top.mk
-include ./tinyusb/examples/make.mk
-
-INC += \
-	. \
-	./CMSIS_5/CMSIS/DAP/Firmware/Include \
-	./bsp/$(BOARD) \
-	./bsp/default \
-	$(TOP)/hw
-
-APP_SOURCE += $(wildcard ./*.c) $(wildcard ./bsp/$(BOARD)/*.c)
-
-SRC_C += $(addprefix $(CURRENT_PATH)/, $(APP_SOURCE))
-
-SRC_C += \
-    ./CMSIS_5/CMSIS/DAP/Firmware/Source/DAP.c \
-    ./CMSIS_5/CMSIS/DAP/Firmware/Source/JTAG_DP.c \
-    ./CMSIS_5/CMSIS/DAP/Firmware/Source/DAP_vendor.c \
-    ./CMSIS_5/CMSIS/DAP/Firmware/Source/SWO.c \
-    ./CMSIS_5/CMSIS/DAP/Firmware/Source/SW_DP.c
-
-include ./tinyusb/examples/rules.mk

README.md

@@ -33,7 +33,7 @@ Compilation is done using CMake:
 
 ```
 mkdir cmake-build && cd cmake-build
-cmake -DBOARD=raspberry_pi_pico -DFAMILIY=rp2040 -DCMAKE_BUILD_TYPE=RelWithDebInfo ..
+cmake -DBOARD=raspberry_pi_pico -DFAMILY=rp2040 -DCMAKE_BUILD_TYPE=RelWithDebInfo ..
 ```
 
 `BOARD` and `FAMILY` should correspond to those used in the TinyUSB `hw` folder,
@@ -54,7 +54,7 @@ the `-DUSE_SYSTEMWIDE_PICOSDK=On` flag to CMake, too.
 Other options are:
 * `-DPICO_NO_FLASH=[On|Off]`: store the binary in RAM only, useful for development.
 * `-DPICO_COPY_TO_RAM=[On|Off]`: write to flash, but always run from RAM
-* `-DUSE_USBCDC_FOR_STDIO=[On|Off]`: export an extra USB-CDC interface for debuggin
+* `-DUSE_USBCDC_FOR_STDIO=[On|Off]`: export an extra USB-CDC interface for debugging
 
 ## Usage
 

bsp/default/DAP_config.h

@@ -135,9 +135,9 @@ This information includes:
 \return String length.
 */
 __STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
-	const static char vnd[] = INFO_MANUFACTURER;
+    const static char vnd[] = INFO_MANUFACTURER;
-	for (size_t i = 0; i < sizeof(vnd); ++i) str[i] = vnd[i];
+    for (size_t i = 0; i < sizeof(vnd); ++i) str[i] = vnd[i];
-	return sizeof(vnd)-1;
+    return sizeof(vnd)-1;
 }
 
 /** Get Product ID string.
@@ -145,9 +145,9 @@ __STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
 \return String length.
 */
 __STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
-	const static char prd[] = INFO_PRODUCT(INFO_BOARDNAME);
+    const static char prd[] = INFO_PRODUCT(INFO_BOARDNAME);
-	for (size_t i = 0; i < sizeof(prd); ++i) str[i] = prd[i];
+    for (size_t i = 0; i < sizeof(prd); ++i) str[i] = prd[i];
-	return sizeof(prd)-1;
+    return sizeof(prd)-1;
 }
 
 /** Get Serial Number string.
@@ -155,7 +155,7 @@ __STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
 \return String length.
 */
 __STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
-	return get_unique_id_u8(str);
+    return get_unique_id_u8(str);
 }
 
 ///@}
@@ -205,7 +205,7 @@ Configures the DAP Hardware I/O pins for JTAG mode:
  - TDO to input mode.
 */
 __STATIC_INLINE void PORT_JTAG_SETUP (void) {
-	;
+    ;
 }
  
 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
@@ -214,7 +214,7 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
  - TDI, nTRST to HighZ mode (pins are unused in SWD mode).
 */
 __STATIC_INLINE void PORT_SWD_SETUP (void) {
-	;
+    ;
 }
 
 /** Disable JTAG/SWD I/O Pins.
@@ -222,7 +222,7 @@ Disables the DAP Hardware I/O pins which configures:
  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
 */
 __STATIC_INLINE void PORT_OFF (void) {
-	;
+    ;
 }
 
 
@@ -232,21 +232,21 @@ __STATIC_INLINE void PORT_OFF (void) {
 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN  (void) {
-	return (0U);
+    return (0U);
 }
 
 /** SWCLK/TCK I/O pin: Set Output to High.
 Set the SWCLK/TCK DAP hardware I/O pin to high level.
 */
 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET (void) {
-	;
+    ;
 }
 
 /** SWCLK/TCK I/O pin: Set Output to Low.
 Set the SWCLK/TCK DAP hardware I/O pin to low level.
 */
 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
-	;
+    ;
 }
 
 
@@ -256,35 +256,35 @@ __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN  (void) {
-	return (0U);
+    return (0U);
 }
 
 /** SWDIO/TMS I/O pin: Set Output to High.
 Set the SWDIO/TMS DAP hardware I/O pin to high level.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET (void) {
-	;
+    ;
 }
 
 /** SWDIO/TMS I/O pin: Set Output to Low.
 Set the SWDIO/TMS DAP hardware I/O pin to low level.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR (void) {
-	;
+    ;
 }
 
 /** SWDIO I/O pin: Get Input (used in SWD mode only).
 \return Current status of the SWDIO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN      (void) {
-	return (board_millis() & 1); /* pacify GCC warning */
+    return (board_millis() & 1); /* pacify GCC warning */
 }
 
 /** SWDIO I/O pin: Set Output (used in SWD mode only).
 \param bit Output value for the SWDIO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT     (uint32_t bit) {
-	(void)bit;
+    (void)bit;
 }
 
 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
@@ -292,7 +292,7 @@ Configure the SWDIO DAP hardware I/O pin to output mode. This function is
 called prior \ref PIN_SWDIO_OUT function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE  (void) {
-	;
+    ;
 }
 
 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
@@ -300,7 +300,7 @@ Configure the SWDIO DAP hardware I/O pin to input mode. This function is
 called prior \ref PIN_SWDIO_IN function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
-	;
+    ;
 }
 
 
@@ -310,14 +310,14 @@ __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
 \return Current status of the TDI DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN  (void) {
-	return (0U);
+    return (0U);
 }
 
 /** TDI I/O pin: Set Output.
 \param bit Output value for the TDI DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
-	(void)bit;
+    (void)bit;
 }
 
 
@@ -327,7 +327,7 @@ __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
 \return Current status of the TDO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void) {
-	return (board_millis() & 1); /* pacify GCC warning */
+    return (board_millis() & 1); /* pacify GCC warning */
 }
 
 
@@ -337,7 +337,7 @@ __STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void) {
 \return Current status of the nTRST DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void) {
-	return (0U);
+    return (0U);
 }
 
 /** nTRST I/O pin: Set Output.
@@ -346,7 +346,7 @@ __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void) {
            - 1: release JTAG TRST Test Reset.
 */
 __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
-	(void)bit;
+    (void)bit;
 }
 
 // nRESET Pin I/O------------------------------------------
@@ -355,7 +355,7 @@ __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
 \return Current status of the nRESET DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void) {
-	return (0U);
+    return (0U);
 }
 
 /** nRESET I/O pin: Set Output.
@@ -364,7 +364,7 @@ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void) {
            - 1: release device hardware reset.
 */
 __STATIC_FORCEINLINE void     PIN_nRESET_OUT (uint32_t bit) {
-	(void)bit;
+    (void)bit;
 }
 
 ///@}
@@ -389,7 +389,7 @@ It is recommended to provide the following LEDs for status indication:
            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
 */
 __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
-	(void)bit;
+    (void)bit;
 }
 
 /** Debug Unit: Set status Target Running LED.
@@ -398,7 +398,7 @@ __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
            - 0: Target Running LED OFF: program execution in target stopped.
 */
 __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
-	(void)bit;
+    (void)bit;
 }
 
 ///@}
@@ -421,9 +421,9 @@ default, the DWT timer is used.  The frequency of this timer is configured with
 */
 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
 #if TIMESTAMP_CLOCK > 0
-	return (DWT->CYCCNT);
+    return (DWT->CYCCNT);
 #else
-	return 0;
+    return 0;
 #endif
 }
 
@@ -448,7 +448,7 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an
  - LED output pins are enabled and LEDs are turned off.
 */
 __STATIC_INLINE void DAP_SETUP (void) {
-	;
+    ;
 }
 
 /** Reset Target Device with custom specific I/O pin or command sequence.
@@ -459,7 +459,7 @@ when a device needs a time-critical unlock sequence that enables the debug port.
         1 = a device specific reset sequence is implemented.
 */
 __STATIC_INLINE uint8_t RESET_TARGET (void) {
-	return (0U);             // change to '1' when a device reset sequence is implemented
+    return (0U);             // change to '1' when a device reset sequence is implemented
 }
 
 ///@}

bsp/default/unique.c

@@ -6,22 +6,22 @@
 /* in the absence of the board-specific directory providing a unique ID, we provide a canned one */
 
 __attribute__((__weak__)) uint8_t get_unique_id_u8(uint8_t *desc_str) {
-	static const char canned[] = "123456";
+    static const char canned[] = "123456";
 
-	for (int i=0; i<TU_ARRAY_SIZE(canned); i++) {
+    for (int i=0; i<TU_ARRAY_SIZE(canned); i++) {
-		desc_str[i] = canned[i];
+        desc_str[i] = canned[i];
-	}
+    }
 
-	return i;
+    return i;
 }
 
 __attribute__((__weak__)) uint8_t get_unique_id_u16(uint16_t *desc_str) {
-	static const char canned[] = "123456";
+    static const char canned[] = "123456";
 
-	for (int i=0; i<TU_ARRAY_SIZE(canned); i++) {
+    for (int i=0; i<TU_ARRAY_SIZE(canned); i++) {
-		desc_str[i] = canned[i];
+        desc_str[i] = canned[i];
-	}
+    }
 
-	return i;
+    return i;
 }
 

bsp/rp2040/DAP_config.h

@@ -161,9 +161,9 @@ This information includes:
 \return String length.
 */
 __STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
-	const static char vnd[] = INFO_MANUFACTURER;
+    const static char vnd[] = INFO_MANUFACTURER;
-	for (size_t i = 0; i < sizeof(vnd); ++i) str[i] = vnd[i];
+    for (size_t i = 0; i < sizeof(vnd); ++i) str[i] = vnd[i];
-	return sizeof(vnd)-1;
+    return sizeof(vnd)-1;
 }
 
 /** Get Product ID string.
@@ -171,9 +171,9 @@ __STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
 \return String length.
 */
 __STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
-	const static char prd[] = INFO_PRODUCT(INFO_BOARDNAME);
+    const static char prd[] = INFO_PRODUCT(INFO_BOARDNAME);
-	for (size_t i = 0; i < sizeof(prd); ++i) str[i] = prd[i];
+    for (size_t i = 0; i < sizeof(prd); ++i) str[i] = prd[i];
-	return sizeof(prd)-1;
+    return sizeof(prd)-1;
 }
 
 /** Get Serial Number string.
@@ -181,7 +181,7 @@ __STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
 \return String length.
 */
 __STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
-	return get_unique_id_u8((uint8_t*)str);
+    return get_unique_id_u8((uint8_t*)str);
 }
 
 ///@}
@@ -231,44 +231,44 @@ Configures the DAP Hardware I/O pins for JTAG mode:
  - TDO to input mode.
 */
 __STATIC_INLINE void PORT_JTAG_SETUP (void) {
-	resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
+    resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
 
-	/* set to default high level */
+    /* set to default high level */
-	sio_hw->gpio_oe_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK | PINOUT_nRESET_MASK;
+    sio_hw->gpio_oe_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK | PINOUT_nRESET_MASK;
-	sio_hw->gpio_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK | PINOUT_nRESET_MASK;
+    sio_hw->gpio_set = PINOUT_TCK_MASK | PINOUT_TMS_MASK | PINOUT_TDI_MASK | PINOUT_nTRST_MASK | PINOUT_nRESET_MASK;
-	/* TDO needs to be an input */
+    /* TDO needs to be an input */
-	sio_hw->gpio_oe_clr = PINOUT_TDO_MASK;
+    sio_hw->gpio_oe_clr = PINOUT_TDO_MASK;
 
-	hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TCK],
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TCK],
-		  PADS_BANK0_GPIO0_IE_BITS, // bits to set: input enable
+          PADS_BANK0_GPIO0_IE_BITS, // bits to set: input enable
-		  PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS); // bits to mask out: input enable, output disable
+          PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS); // bits to mask out: input enable, output disable
-	hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TMS],
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TMS],
-		  PADS_BANK0_GPIO0_IE_BITS,
+          PADS_BANK0_GPIO0_IE_BITS,
-		  PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+          PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-	hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDI],
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDI],
-		  PADS_BANK0_GPIO0_IE_BITS,
+          PADS_BANK0_GPIO0_IE_BITS,
-		  PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+          PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-	hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDO],
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_TDO],
-		  PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS, // TDO needs to have its output disabled
+          PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS, // TDO needs to have its output disabled
-		  PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+          PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-	hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nTRST],
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nTRST],
-		  PADS_BANK0_GPIO0_IE_BITS,
+          PADS_BANK0_GPIO0_IE_BITS,
-		  PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+          PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-	hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nRESET],
+    hw_write_masked(&padsbank0_hw->io[PINOUT_JTAG_nRESET],
-		  PADS_BANK0_GPIO0_IE_BITS,
+          PADS_BANK0_GPIO0_IE_BITS,
-		  PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+          PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
 
-	// NOTE: hiZ: ctrl = (ctrl & ~(CTRL_OEOVER_BITS)) | (GPIO_OVERRIDE_LOW << CTRL_OEOVER_LSB);
+    // NOTE: hiZ: ctrl = (ctrl & ~(CTRL_OEOVER_BITS)) | (GPIO_OVERRIDE_LOW << CTRL_OEOVER_LSB);
-	// normal == 0, low == 2
+    // normal == 0, low == 2
 
-	// set pin modes to general IO (SIO)
+    // set pin modes to general IO (SIO)
-	iobank0_hw->io[PINOUT_JTAG_TCK].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_TCK].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-	iobank0_hw->io[PINOUT_JTAG_TMS].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_TMS].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-	iobank0_hw->io[PINOUT_JTAG_TDI].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_TDI].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-	iobank0_hw->io[PINOUT_JTAG_TDO].ctrl = (GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB)
+    iobank0_hw->io[PINOUT_JTAG_TDO].ctrl = (GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB)
-										  /*| (GPIO_OVERRIDE_LOW << IO_BANK0_GPIO0_CTRL_OEOVER_LSB)*/;
+                                          /*| (GPIO_OVERRIDE_LOW << IO_BANK0_GPIO0_CTRL_OEOVER_LSB)*/;
-	iobank0_hw->io[PINOUT_JTAG_nTRST].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_nTRST].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-	iobank0_hw->io[PINOUT_JTAG_nRESET].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_JTAG_nRESET].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
 }
 
 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
@@ -277,16 +277,16 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
  - TDI, nTRST to HighZ mode (pins are unused in SWD mode).
 */
 __STATIC_INLINE void PORT_SWD_SETUP (void) {
-	resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
+    resets_hw->reset &= ~(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS);
 
-	/* set to default high level */
+    /* set to default high level */
-	sio_hw->gpio_oe_set = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
+    sio_hw->gpio_oe_set = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
-	sio_hw->gpio_set = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
+    sio_hw->gpio_set = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK;
 
-	hw_write_masked(&padsbank0_hw->io[PINOUT_SWCLK], PADS_BANK0_GPIO0_IE_BITS, PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_SWCLK], PADS_BANK0_GPIO0_IE_BITS, PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-	hw_write_masked(&padsbank0_hw->io[PINOUT_SWDIO], PADS_BANK0_GPIO0_IE_BITS, PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_SWDIO], PADS_BANK0_GPIO0_IE_BITS, PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-	iobank0_hw->io[PINOUT_SWCLK].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_SWCLK].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
-	iobank0_hw->io[PINOUT_SWDIO].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_SWDIO].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
 }
 
 /** Disable JTAG/SWD I/O Pins.
@@ -294,9 +294,9 @@ Disables the DAP Hardware I/O pins which configures:
  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
 */
 __STATIC_INLINE void PORT_OFF (void) {
-	sio_hw->gpio_oe_clr = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK
+    sio_hw->gpio_oe_clr = PINOUT_SWCLK_MASK | PINOUT_SWDIO_MASK
-		| PINOUT_TDI_MASK //| PINOUT_TDO_MASK
+        | PINOUT_TDI_MASK //| PINOUT_TDO_MASK
-		| PINOUT_nTRST_MASK | PINOUT_nRESET_MASK;
+        | PINOUT_nTRST_MASK | PINOUT_nRESET_MASK;
 }
 
 
@@ -306,21 +306,21 @@ __STATIC_INLINE void PORT_OFF (void) {
 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN  (void) {
-	return (sio_hw->gpio_in & PINOUT_SWCLK_MASK) >> PINOUT_SWCLK;
+    return (sio_hw->gpio_in & PINOUT_SWCLK_MASK) >> PINOUT_SWCLK;
 }
 
 /** SWCLK/TCK I/O pin: Set Output to High.
 Set the SWCLK/TCK DAP hardware I/O pin to high level.
 */
 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET (void) {
-	sio_hw->gpio_set = PINOUT_SWCLK_MASK;
+    sio_hw->gpio_set = PINOUT_SWCLK_MASK;
 }
 
 /** SWCLK/TCK I/O pin: Set Output to Low.
 Set the SWCLK/TCK DAP hardware I/O pin to low level.
 */
 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
-	sio_hw->gpio_clr = PINOUT_SWCLK_MASK;
+    sio_hw->gpio_clr = PINOUT_SWCLK_MASK;
 }
 
 
@@ -330,7 +330,7 @@ __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN  (void) {
-	return (sio_hw->gpio_in & PINOUT_SWDIO_MASK) >> PINOUT_SWDIO;
+    return (sio_hw->gpio_in & PINOUT_SWDIO_MASK) >> PINOUT_SWDIO;
 }
 
 /* PIN_SWDIO_TMS_SET and PIN_SWDIO_TMS_CLR are used by SWJ_Sequence */
@@ -339,31 +339,31 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN  (void) {
 Set the SWDIO/TMS DAP hardware I/O pin to high level.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET (void) {
-	sio_hw->gpio_set = PINOUT_SWDIO_MASK;
+    sio_hw->gpio_set = PINOUT_SWDIO_MASK;
 }
 
 /** SWDIO/TMS I/O pin: Set Output to Low.
 Set the SWDIO/TMS DAP hardware I/O pin to low level.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR (void) {
-	sio_hw->gpio_clr = PINOUT_SWDIO_MASK;
+    sio_hw->gpio_clr = PINOUT_SWDIO_MASK;
 }
 
 /** SWDIO I/O pin: Get Input (used in SWD mode only).
 \return Current status of the SWDIO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN      (void) {
-	return (sio_hw->gpio_in & PINOUT_SWDIO_MASK) ? 1U : 0U;
+    return (sio_hw->gpio_in & PINOUT_SWDIO_MASK) ? 1U : 0U;
 }
 
 /** SWDIO I/O pin: Set Output (used in SWD mode only).
 \param bit Output value for the SWDIO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT     (uint32_t bit) {
-	if (bit & 1)
+    if (bit & 1)
-		sio_hw->gpio_set = PINOUT_SWDIO_MASK;
+        sio_hw->gpio_set = PINOUT_SWDIO_MASK;
-	else
+    else
-		sio_hw->gpio_clr = PINOUT_SWDIO_MASK;
+        sio_hw->gpio_clr = PINOUT_SWDIO_MASK;
 }
 
 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
@@ -371,7 +371,7 @@ Configure the SWDIO DAP hardware I/O pin to output mode. This function is
 called prior \ref PIN_SWDIO_OUT function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE  (void) {
-	sio_hw->gpio_oe_set = PINOUT_SWDIO_MASK;
+    sio_hw->gpio_oe_set = PINOUT_SWDIO_MASK;
 }
 
 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
@@ -379,7 +379,7 @@ Configure the SWDIO DAP hardware I/O pin to input mode. This function is
 called prior \ref PIN_SWDIO_IN function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
-	sio_hw->gpio_oe_clr = PINOUT_SWDIO_MASK;
+    sio_hw->gpio_oe_clr = PINOUT_SWDIO_MASK;
 }
 
 
@@ -389,17 +389,17 @@ __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
 \return Current status of the TDI DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN  (void) {
-	return (sio_hw->gpio_in & PINOUT_TDI_MASK) >> PINOUT_JTAG_TDI;
+    return (sio_hw->gpio_in & PINOUT_TDI_MASK) >> PINOUT_JTAG_TDI;
 }
 
 /** TDI I/O pin: Set Output.
 \param bit Output value for the TDI DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
-	if (bit & 1)
+    if (bit & 1)
-		sio_hw->gpio_set = PINOUT_TDI_MASK;
+        sio_hw->gpio_set = PINOUT_TDI_MASK;
-	else
+    else
-		sio_hw->gpio_clr = PINOUT_TDI_MASK;
+        sio_hw->gpio_clr = PINOUT_TDI_MASK;
 }
 
 
@@ -409,7 +409,7 @@ __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
 \return Current status of the TDO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void) {
-	return (sio_hw->gpio_in & PINOUT_TDO_MASK) >> PINOUT_JTAG_TDO;
+    return (sio_hw->gpio_in & PINOUT_TDO_MASK) >> PINOUT_JTAG_TDO;
 }
 
 
@@ -419,7 +419,7 @@ __STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void) {
 \return Current status of the nTRST DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void) {
-	return (sio_hw->gpio_in & PINOUT_nTRST_MASK) >> PINOUT_JTAG_nTRST;
+    return (sio_hw->gpio_in & PINOUT_nTRST_MASK) >> PINOUT_JTAG_nTRST;
 }
 
 /** nTRST I/O pin: Set Output.
@@ -428,10 +428,10 @@ __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void) {
            - 1: release JTAG TRST Test Reset.
 */
 __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
-	if (bit & 1)
+    if (bit & 1)
-		sio_hw->gpio_set = PINOUT_nTRST_MASK;
+        sio_hw->gpio_set = PINOUT_nTRST_MASK;
-	else
+    else
-		sio_hw->gpio_clr = PINOUT_nTRST_MASK;
+        sio_hw->gpio_clr = PINOUT_nTRST_MASK;
 }
 
 // nRESET Pin I/O------------------------------------------
@@ -440,7 +440,7 @@ __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
 \return Current status of the nRESET DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void) {
-	return (sio_hw->gpio_in & PINOUT_nRESET_MASK) >> PINOUT_JTAG_nRESET;
+    return (sio_hw->gpio_in & PINOUT_nRESET_MASK) >> PINOUT_JTAG_nRESET;
 }
 
 /** nRESET I/O pin: Set Output.
@@ -449,10 +449,10 @@ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void) {
            - 1: release device hardware reset.
 */
 __STATIC_FORCEINLINE void     PIN_nRESET_OUT (uint32_t bit) {
-	if (bit & 1)
+    if (bit & 1)
-		sio_hw->gpio_set = PINOUT_nRESET_MASK;
+        sio_hw->gpio_set = PINOUT_nRESET_MASK;
-	else
+    else
-		sio_hw->gpio_clr = PINOUT_nRESET_MASK;
+        sio_hw->gpio_clr = PINOUT_nRESET_MASK;
 }
 
 ///@}
@@ -478,12 +478,12 @@ It is recommended to provide the following LEDs for status indication:
 */
 __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
 #if PINOUT_LED_CONNECTED
-	if (bit & 1)
+    if (bit & 1)
-		sio_hw->gpio_set = PINOUT_LED_MASK;
+        sio_hw->gpio_set = PINOUT_LED_MASK;
-	else
+    else
-		sio_hw->gpio_clr = PINOUT_LED_MASK;
+        sio_hw->gpio_clr = PINOUT_LED_MASK;
 #else
-	(void)bit;
+    (void)bit;
 #endif
 }
 
@@ -494,12 +494,12 @@ __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
 */
 __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
 #if PINOUT_LED_RUNNING
-	if (bit & 1)
+    if (bit & 1)
-		sio_hw->gpio_set = PINOUT_LED_MASK;
+        sio_hw->gpio_set = PINOUT_LED_MASK;
-	else
+    else
-		sio_hw->gpio_clr = PINOUT_LED_MASK;
+        sio_hw->gpio_clr = PINOUT_LED_MASK;
 #else
-	(void)bit;
+    (void)bit;
 #endif
 }
 
@@ -523,9 +523,9 @@ default, the DWT timer is used.  The frequency of this timer is configured with
 */
 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
 #if TIMESTAMP_CLOCK > 0
-	return (DWT->CYCCNT);
+    return (DWT->CYCCNT);
 #else
-	return 0;
+    return 0;
 #endif
 }
 
@@ -550,22 +550,22 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an
  - LED output pins are enabled and LEDs are turned off.
 */
 __STATIC_INLINE void DAP_SETUP (void) {
-	sio_hw->gpio_oe_set = PINOUT_LED_MASK;
+    sio_hw->gpio_oe_set = PINOUT_LED_MASK;
-	sio_hw->gpio_clr = PINOUT_LED_MASK;
+    sio_hw->gpio_clr = PINOUT_LED_MASK;
 
-	hw_write_masked(&padsbank0_hw->io[PINOUT_LED], 0, PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+    hw_write_masked(&padsbank0_hw->io[PINOUT_LED], 0, PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
-	iobank0_hw->io[PINOUT_LED].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+    iobank0_hw->io[PINOUT_LED].ctrl = GPIO_FUNC_SIO << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
 
-	bi_decl(bi_2pins_with_names(
+    bi_decl(bi_2pins_with_names(
-		PINOUT_JTAG_TCK, "TCK / SWCLK",
+        PINOUT_JTAG_TCK, "TCK / SWCLK",
-		PINOUT_JTAG_TMS, "TMS / SWDIO"
+        PINOUT_JTAG_TMS, "TMS / SWDIO"
-	));
+    ));
-	bi_decl(bi_4pins_with_names(
+    bi_decl(bi_4pins_with_names(
-		PINOUT_JTAG_TDI   , "TDI",
+        PINOUT_JTAG_TDI   , "TDI",
-		PINOUT_JTAG_TDO   , "TDO",
+        PINOUT_JTAG_TDO   , "TDO",
-		PINOUT_JTAG_nTRST , "nTRST",
+        PINOUT_JTAG_nTRST , "nTRST",
-		PINOUT_JTAG_nRESET, "nRESET"
+        PINOUT_JTAG_nRESET, "nRESET"
-	));
+    ));
 }
 
 /** Reset Target Device with custom specific I/O pin or command sequence.
@@ -576,7 +576,7 @@ when a device needs a time-critical unlock sequence that enables the debug port.
         1 = a device specific reset sequence is implemented.
 */
 __STATIC_INLINE uint8_t RESET_TARGET (void) {
-	return (0U);             // change to '1' when a device reset sequence is implemented
+    return (0U);             // change to '1' when a device reset sequence is implemented
 }
 
 ///@}

bsp/rp2040/cdc_stdio.c

@@ -22,85 +22,85 @@
 static mutex_t stdio_usb_mutex;
 
 static void stdio_usb_out_chars(const char* buf, int length) {
-	static uint64_t last_avail_time;
+    static uint64_t last_avail_time;
-	uint32_t owner;
+    uint32_t owner;
 
-	if (!mutex_try_enter(&stdio_usb_mutex, &owner)) {
+    if (!mutex_try_enter(&stdio_usb_mutex, &owner)) {
-		if (owner == get_core_num()) return; // would deadlock otherwise
+        if (owner == get_core_num()) return; // would deadlock otherwise
-		mutex_enter_blocking(&stdio_usb_mutex);
+        mutex_enter_blocking(&stdio_usb_mutex);
-	}
+    }
 
-	if (tud_cdc_n_connected(CDC_N_STDIO)) {
+    if (tud_cdc_n_connected(CDC_N_STDIO)) {
-		for (int i = 0; i < length; ) {
+        for (int i = 0; i < length; ) {
-			int n = length - i;
+            int n = length - i;
-			int avail = tud_cdc_n_write_available(CDC_N_STDIO);
+            int avail = tud_cdc_n_write_available(CDC_N_STDIO);
 
-			if (n > avail) n = avail;
+            if (n > avail) n = avail;
-			if (n) {
+            if (n) {
-				int n2 = tud_cdc_n_write(CDC_N_STDIO, buf+i, n);
+                int n2 = tud_cdc_n_write(CDC_N_STDIO, buf+i, n);
-				tud_task();
+                tud_task();
-				tud_cdc_n_write_flush(CDC_N_STDIO);
+                tud_cdc_n_write_flush(CDC_N_STDIO);
-				i += n2;
+                i += n2;
-				last_avail_time = time_us_64();
+                last_avail_time = time_us_64();
-			} else {
+            } else {
-				tud_task();
+                tud_task();
-				tud_cdc_n_write_flush(CDC_N_STDIO);
+                tud_cdc_n_write_flush(CDC_N_STDIO);
 
-				if (!tud_cdc_n_connected(CDC_N_STDIO) ||
+                if (!tud_cdc_n_connected(CDC_N_STDIO) ||
-						(!tud_cdc_n_write_available(CDC_N_STDIO)
+                        (!tud_cdc_n_write_available(CDC_N_STDIO)
-						 && time_us_64() > last_avail_time + PICO_STDIO_USB_STDOUT_TIMEOUT_US)) {
+                         && time_us_64() > last_avail_time + PICO_STDIO_USB_STDOUT_TIMEOUT_US)) {
-					break;
+                    break;
-				}
+                }
-			}
+            }
-		}
+        }
-	} else {
+    } else {
-		// reset our timeout
+        // reset our timeout
-		last_avail_time = 0;
+        last_avail_time = 0;
-	}
+    }
 
-	mutex_exit(&stdio_usb_mutex);
+    mutex_exit(&stdio_usb_mutex);
 }
 
 static int stdio_usb_in_chars(char* buf, int length) {
-	uint32_t owner;
+    uint32_t owner;
 
-	if (!mutex_try_enter(&stdio_usb_mutex, &owner)) {
+    if (!mutex_try_enter(&stdio_usb_mutex, &owner)) {
-		if (owner == get_core_num()) return PICO_ERROR_NO_DATA; // would deadlock otherwise
+        if (owner == get_core_num()) return PICO_ERROR_NO_DATA; // would deadlock otherwise
-		mutex_enter_blocking(&stdio_usb_mutex);
+        mutex_enter_blocking(&stdio_usb_mutex);
-	}
+    }
 
-	int rc = PICO_ERROR_NO_DATA;
+    int rc = PICO_ERROR_NO_DATA;
 
-	if (tud_cdc_n_connected(CDC_N_STDIO) && tud_cdc_n_available(CDC_N_STDIO)) {
+    if (tud_cdc_n_connected(CDC_N_STDIO) && tud_cdc_n_available(CDC_N_STDIO)) {
-		int count = tud_cdc_n_read(CDC_N_STDIO, buf, length);
+        int count = tud_cdc_n_read(CDC_N_STDIO, buf, length);
-		rc = count ? count : PICO_ERROR_NO_DATA;
+        rc = count ? count : PICO_ERROR_NO_DATA;
-	}
+    }
 
-	mutex_exit(&stdio_usb_mutex);
+    mutex_exit(&stdio_usb_mutex);
 
-	return rc;
+    return rc;
 }
 
 extern stdio_driver_t stdio_usb;
 stdio_driver_t stdio_usb = {
-	.out_chars = stdio_usb_out_chars,
+    .out_chars = stdio_usb_out_chars,
-	. in_chars = stdio_usb_in_chars ,
+    . in_chars = stdio_usb_in_chars ,
 #if PICO_STDIO_ENABLE_CRLF_SUPPORT
-	.crlf_enabled = PICO_STDIO_DEFAULT_CRLF
+    .crlf_enabled = PICO_STDIO_DEFAULT_CRLF
 #endif
 };
 
 bool stdio_usb_init(void) {
 //#if !PICO_NO_BI_STDIO_USB
-	bi_decl_if_func_used(bi_program_feature("USB stdin / stdout"));
+    bi_decl_if_func_used(bi_program_feature("USB stdin / stdout"));
 //#endif
 
-	mutex_init(&stdio_usb_mutex);
+    mutex_init(&stdio_usb_mutex);
 
-	// unlike with the SDK code, we don't need to add IRQ stuff for the USB
+    // unlike with the SDK code, we don't need to add IRQ stuff for the USB
-	// task, as our main function handles this automatically
+    // task, as our main function handles this automatically
 
-	stdio_set_driver_enabled(&stdio_usb, true);
+    stdio_set_driver_enabled(&stdio_usb, true);
-	return true;
+    return true;
 }
 

bsp/rp2040/cdc_uart.c

@@ -35,43 +35,43 @@ static uint8_t rx_buf[CFG_TUD_CDC_RX_BUFSIZE];
 static uint8_t tx_buf[CFG_TUD_CDC_TX_BUFSIZE];
 
 void cdc_uart_init(void) {
-	gpio_set_function(PINOUT_UART_TX, GPIO_FUNC_UART);
+    gpio_set_function(PINOUT_UART_TX, GPIO_FUNC_UART);
-	gpio_set_function(PINOUT_UART_RX, GPIO_FUNC_UART);
+    gpio_set_function(PINOUT_UART_RX, GPIO_FUNC_UART);
-	uart_init(PINOUT_UART_INTERFACE, PINOUT_UART_BAUDRATE);
+    uart_init(PINOUT_UART_INTERFACE, PINOUT_UART_BAUDRATE);
 
-	bi_decl(bi_2pins_with_func(PINOUT_UART_TX, PINOUT_UART_RX, GPIO_FUNC_UART));
+    bi_decl(bi_2pins_with_func(PINOUT_UART_TX, PINOUT_UART_RX, GPIO_FUNC_UART));
 }
 
 void cdc_uart_task(void) {
-	// Consume uart fifo regardless even if not connected
+    // Consume uart fifo regardless even if not connected
-	uint rx_len = 0;
+    uint rx_len = 0;
-	while (uart_is_readable(PINOUT_UART_INTERFACE) && (rx_len < sizeof(rx_buf))) {
+    while (uart_is_readable(PINOUT_UART_INTERFACE) && (rx_len < sizeof(rx_buf))) {
-		rx_buf[rx_len++] = uart_getc(PINOUT_UART_INTERFACE);
+        rx_buf[rx_len++] = uart_getc(PINOUT_UART_INTERFACE);
-	}
+    }
 
-	if (tud_cdc_n_connected(CDC_N_UART)) {
+    if (tud_cdc_n_connected(CDC_N_UART)) {
-		// Do we have anything to display on the host's terminal?
+        // Do we have anything to display on the host's terminal?
-		if (rx_len) {
+        if (rx_len) {
-			for (uint i = 0; i < rx_len; i++) {
+            for (uint i = 0; i < rx_len; i++) {
-				tud_cdc_n_write_char(CDC_N_UART, rx_buf[i]);
+                tud_cdc_n_write_char(CDC_N_UART, rx_buf[i]);
-			}
+            }
-			tud_cdc_n_write_flush(CDC_N_UART);
+            tud_cdc_n_write_flush(CDC_N_UART);
-		}
+        }
 
-		if (tud_cdc_n_available(CDC_N_UART)) {
+        if (tud_cdc_n_available(CDC_N_UART)) {
-			// Is there any data from the host for us to tx
+            // Is there any data from the host for us to tx
-			uint tx_len = tud_cdc_n_read(CDC_N_UART, tx_buf, sizeof(tx_buf));
+            uint tx_len = tud_cdc_n_read(CDC_N_UART, tx_buf, sizeof(tx_buf));
-			uart_write_blocking(PINOUT_UART_INTERFACE, tx_buf, tx_len);
+            uart_write_blocking(PINOUT_UART_INTERFACE, tx_buf, tx_len);
-		}
+        }
-	}
+    }
 }
 
 void cdc_uart_set_hwflow(bool enable) {
-	uart_set_hw_flow(PINOUT_UART_INTERFACE, enable, enable);
+    uart_set_hw_flow(PINOUT_UART_INTERFACE, enable, enable);
 }
 
 void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* line_coding) {
-	//picoprobe_info("New baud rate %d\n", line_coding->bit_rate);
+    //picoprobe_info("New baud rate %d\n", line_coding->bit_rate);
-	uart_init(PINOUT_UART_INTERFACE, line_coding->bit_rate);
+    uart_init(PINOUT_UART_INTERFACE, line_coding->bit_rate);
 }
 

bsp/rp2040/i2c_tinyusb.c

@@ -17,407 +17,407 @@ static int delay = 10, delay2 = 5;
 // I2C bitbang reimpl because ugh, synopsys
 // (mostly inspired by original I2CTinyUSB AVR firmware)
 __attribute__((__always_inline__)) inline static void i2cio_set_sda(bool hi) {
-	if (hi) {
+    if (hi) {
-		sio_hw->gpio_oe_clr = (1<<PINOUT_I2C_SDA); // SDA is input
+        sio_hw->gpio_oe_clr = (1<<PINOUT_I2C_SDA); // SDA is input
-		// => pullup configured, so it'll go high
+        // => pullup configured, so it'll go high
-	} else {
+    } else {
-		sio_hw->gpio_oe_set = (1<<PINOUT_I2C_SDA); // SDA is output
+        sio_hw->gpio_oe_set = (1<<PINOUT_I2C_SDA); // SDA is output
-		sio_hw->gpio_clr = (1<<PINOUT_I2C_SDA); // and drive it low
+        sio_hw->gpio_clr = (1<<PINOUT_I2C_SDA); // and drive it low
-	}
+    }
 }
 __attribute__((__always_inline__)) inline static bool i2cio_get_sda(void) {
-	return (sio_hw->gpio_in & (1<<PINOUT_I2C_SDA)) != 0;
+    return (sio_hw->gpio_in & (1<<PINOUT_I2C_SDA)) != 0;
 }
 __attribute__((__always_inline__)) inline static void i2cio_set_scl(bool hi) {
-	busy_wait_us_32(delay2);
+    busy_wait_us_32(delay2);
-	sio_hw->gpio_oe_set = (1<<PINOUT_I2C_SCL); // SCL is output
+    sio_hw->gpio_oe_set = (1<<PINOUT_I2C_SCL); // SCL is output
-	if (hi)
+    if (hi)
-		sio_hw->gpio_set = (1<<PINOUT_I2C_SCL); // SCL is high
+        sio_hw->gpio_set = (1<<PINOUT_I2C_SCL); // SCL is high
-	else
+    else
-		sio_hw->gpio_clr = (1<<PINOUT_I2C_SCL); // SCL is low
+        sio_hw->gpio_clr = (1<<PINOUT_I2C_SCL); // SCL is low
-	busy_wait_us_32(delay2);
+    busy_wait_us_32(delay2);
 }
 
 __attribute__((__always_inline__)) inline static void i2cio_scl_toggle(void) {
-	i2cio_set_scl(true );
+    i2cio_set_scl(true );
-	i2cio_set_scl(false);
+    i2cio_set_scl(false);
 }
 
 static void __no_inline_not_in_flash_func(i2cio_start)(void) { // start condition
-	i2cio_set_sda(false);
+    i2cio_set_sda(false);
-	i2cio_set_scl(false);
+    i2cio_set_scl(false);
 }
 static void __no_inline_not_in_flash_func(i2cio_repstart)(void) { // repstart condition
-	i2cio_set_sda(true);
+    i2cio_set_sda(true);
-	i2cio_set_scl(true);
+    i2cio_set_scl(true);
 
-	i2cio_set_sda(false);
+    i2cio_set_sda(false);
-	i2cio_set_scl(false);
+    i2cio_set_scl(false);
 }
 static void __no_inline_not_in_flash_func(i2cio_stop)(void) { // stop condition
-	i2cio_set_sda(false);
+    i2cio_set_sda(false);
-	i2cio_set_scl(true );
+    i2cio_set_scl(true );
-	i2cio_set_sda(true );
+    i2cio_set_sda(true );
 }
 
 static bool __no_inline_not_in_flash_func(i2cio_write7)(uint8_t v) { // return value: acked? // needed for 10bitaddr xfers
-	for (int i = 6; i >= 0; --i) {
+    for (int i = 6; i >= 0; --i) {
-		i2cio_set_sda((v & (1<<i)) != 0);
+        i2cio_set_sda((v & (1<<i)) != 0);
-		i2cio_scl_toggle();
+        i2cio_scl_toggle();
-	}
+    }
 
-	i2cio_set_sda(true);
+    i2cio_set_sda(true);
-	i2cio_set_scl(true);
+    i2cio_set_scl(true);
 
-	bool ack = !i2cio_get_sda();
+    bool ack = !i2cio_get_sda();
-	i2cio_set_scl(false);
+    i2cio_set_scl(false);
 
-	return ack;
+    return ack;
 }
 static bool __no_inline_not_in_flash_func(i2cio_write8)(uint8_t v) { // return value: acked?
-	for (int i = 7; i >= 0; --i) {
+    for (int i = 7; i >= 0; --i) {
-		i2cio_set_sda((v & (1<<i)) != 0);
+        i2cio_set_sda((v & (1<<i)) != 0);
-		i2cio_scl_toggle();
+        i2cio_scl_toggle();
-	}
+    }
 
-	i2cio_set_sda(true);
+    i2cio_set_sda(true);
-	i2cio_set_scl(true);
+    i2cio_set_scl(true);
 
-	bool ack = !i2cio_get_sda();
+    bool ack = !i2cio_get_sda();
-	i2cio_set_scl(false);
+    i2cio_set_scl(false);
 
-	return ack;
+    return ack;
 }
 static uint8_t __no_inline_not_in_flash_func(i2cio_read8)(bool last) {
-	i2cio_set_sda(true );
+    i2cio_set_sda(true );
-	i2cio_set_scl(false);
+    i2cio_set_scl(false);
 
-	uint8_t rv = 0;
+    uint8_t rv = 0;
-	for (int i = 7; i >= 0; --i) {
+    for (int i = 7; i >= 0; --i) {
-		i2cio_set_scl(true);
+        i2cio_set_scl(true);
-		bool c = i2cio_get_sda();
+        bool c = i2cio_get_sda();
-		rv <<= 1;
+        rv <<= 1;
-		if (c) rv |= 1;
+        if (c) rv |= 1;
-		i2cio_set_scl(false);
+        i2cio_set_scl(false);
-	}
+    }
 
-	if (last) i2cio_set_sda(true);
+    if (last) i2cio_set_sda(true);
-	else i2cio_set_sda(false);
+    else i2cio_set_sda(false);
 
-	i2cio_scl_toggle();
+    i2cio_scl_toggle();
-	i2cio_set_sda(true);
+    i2cio_set_sda(true);
 }
 
 // replicating/rewriting some SDK functions because they don't do what I want
 // so I'm making better ones
 
 static int __no_inline_not_in_flash_func(i2cex_probe_address)(uint16_t addr, bool a10bit) {
-	// I2C pins to SIO
+    // I2C pins to SIO
-	gpio_set_function(PINOUT_I2C_SCL, GPIO_FUNC_SIO);
+    gpio_set_function(PINOUT_I2C_SCL, GPIO_FUNC_SIO);
-	gpio_set_function(PINOUT_I2C_SDA, GPIO_FUNC_SIO);
+    gpio_set_function(PINOUT_I2C_SDA, GPIO_FUNC_SIO);
 
-	int rv;
+    int rv;
-	i2cio_start();
+    i2cio_start();
 
-	if (a10bit) {
+    if (a10bit) {
-		//         A10 magic   higher 2 addr bits         r/#w bit
+        //         A10 magic   higher 2 addr bits         r/#w bit
-		uint8_t addr1 = 0x70 | (((addr >> 8) & 3) << 1) | 0,
+        uint8_t addr1 = 0x70 | (((addr >> 8) & 3) << 1) | 0,
-		        addr2 = addr & 0xff;
+                addr2 = addr & 0xff;
 
-		if (i2cio_write7(addr1)) {
+        if (i2cio_write7(addr1)) {
-			if (i2cio_write8(addr2)) rv = 0;
+            if (i2cio_write8(addr2)) rv = 0;
-			else rv = PICO_ERROR_GENERIC;
+            else rv = PICO_ERROR_GENERIC;
-		} else rv = PICO_ERROR_GENERIC;
+        } else rv = PICO_ERROR_GENERIC;
-	} else {
+    } else {
-		if (i2cio_write8((addr << 1) & 0xff)) rv = 0; // acked: ok
+        if (i2cio_write8((addr << 1) & 0xff)) rv = 0; // acked: ok
-		else rv = PICO_ERROR_GENERIC; // nak :/
+        else rv = PICO_ERROR_GENERIC; // nak :/
-	}
+    }
-	i2cio_stop();
+    i2cio_stop();
 
-	// I2C back to I2C
+    // I2C back to I2C
-	gpio_set_function(PINOUT_I2C_SCL, GPIO_FUNC_I2C);
+    gpio_set_function(PINOUT_I2C_SCL, GPIO_FUNC_I2C);
-	gpio_set_function(PINOUT_I2C_SDA, GPIO_FUNC_I2C);
+    gpio_set_function(PINOUT_I2C_SDA, GPIO_FUNC_I2C);
 
-	return rv;
+    return rv;
 }
 
 inline static void i2cex_abort_xfer(i2c_inst_t* i2c) {
 #if 1
-	// may be bugged??? so doesnt do anything for now
+    // may be bugged??? so doesnt do anything for now
-	return;
+    return;
 #else
-	// now do the abort
+    // now do the abort
-	i2c->hw->enable = 1 /*| (1<<2)*/ | (1<<1);
+    i2c->hw->enable = 1 /*| (1<<2)*/ | (1<<1);
-	// wait for M_TX_ABRT irq
+    // wait for M_TX_ABRT irq
-	do {
+    do {
-		/*if (timeout_check) {
+        /*if (timeout_check) {
-			timeout = timeout_check(ts);
+            timeout = timeout_check(ts);
-			abort |= timeout;
+            abort |= timeout;
-		}*/
+        }*/
-		tight_loop_contents();
+        tight_loop_contents();
-	} while (/*!timeout &&*/ !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS));
+    } while (/*!timeout &&*/ !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS));
-	// reset irq
+    // reset irq
-	//if (!timeout)
+    //if (!timeout)
-		(void)i2c->hw->clr_tx_abrt;
+        (void)i2c->hw->clr_tx_abrt;
 #endif
 }
 
 static int i2cex_write_blocking_until(i2c_inst_t* i2c, uint16_t addr, bool a10bit,
-		const uint8_t* src, size_t len, bool nostop, absolute_time_t until) {
+        const uint8_t* src, size_t len, bool nostop, absolute_time_t until) {
-	timeout_state_t ts_;
+    timeout_state_t ts_;
-	struct timeout_state* ts = &ts_;
+    struct timeout_state* ts = &ts_;
-	check_timeout_fn timeout_check = init_single_timeout_until(&ts_, until);
+    check_timeout_fn timeout_check = init_single_timeout_until(&ts_, until);
 
-	if ((int)len < 0) return PICO_ERROR_GENERIC;
+    if ((int)len < 0) return PICO_ERROR_GENERIC;
-	if (a10bit) { // addr too high
+    if (a10bit) { // addr too high
-		if (addr & ~(uint16_t)((1<<10)-1)) return PICO_ERROR_GENERIC;
+        if (addr & ~(uint16_t)((1<<10)-1)) return PICO_ERROR_GENERIC;
-	} else if (addr & 0x80)
+    } else if (addr & 0x80)
-		return PICO_ERROR_GENERIC;
+        return PICO_ERROR_GENERIC;
 
-	if (len == 0) return i2cex_probe_address(addr, a10bit);
+    if (len == 0) return i2cex_probe_address(addr, a10bit);
 
-	bool abort = false, timeout = false;
+    bool abort = false, timeout = false;
-	uint32_t abort_reason = 0;
+    uint32_t abort_reason = 0;
-	int byte_ctr;
+    int byte_ctr;
 
-	i2c->hw->enable = 0;
+    i2c->hw->enable = 0;
-	// enable 10bit mode if requested
+    // enable 10bit mode if requested
-	hw_write_masked(&i2c->hw->con, I2C_IC_CON_IC_10BITADDR_MASTER_BITS, (a10bit
+    hw_write_masked(&i2c->hw->con, I2C_IC_CON_IC_10BITADDR_MASTER_BITS, (a10bit
-			? I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS
+            ? I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS
-			: I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS ) << I2C_IC_CON_IC_10BITADDR_MASTER_LSB);
+            : I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS ) << I2C_IC_CON_IC_10BITADDR_MASTER_LSB);
-	i2c->hw->tar = addr;
+    i2c->hw->tar = addr;
-	i2c->hw->enable = 1;
+    i2c->hw->enable = 1;
 
-	for (byte_ctr = 0; byte_ctr < (int)len; ++byte_ctr) {
+    for (byte_ctr = 0; byte_ctr < (int)len; ++byte_ctr) {
-		bool first = byte_ctr == 0,
+        bool first = byte_ctr == 0,
-		     last  = byte_ctr == (int)len - 1;
+             last  = byte_ctr == (int)len - 1;
 
-		i2c->hw->data_cmd =
+        i2c->hw->data_cmd =
-			bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
+            bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
-			bool_to_bit(last  && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
+            bool_to_bit(last  && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
-			*src++;
+            *src++;
 
-		do {
+        do {
-			if (timeout_check) {
+            if (timeout_check) {
-				timeout = timeout_check(ts);
+                timeout = timeout_check(ts);
-				abort |= timeout;
+                abort |= timeout;
-			}
+            }
-			tight_loop_contents();
+            tight_loop_contents();
-		} while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS));
+        } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS));
 
-		if (!timeout) {
+        if (!timeout) {
-			abort_reason = i2c->hw->tx_abrt_source;
+            abort_reason = i2c->hw->tx_abrt_source;
-			if (abort_reason) {
+            if (abort_reason) {
-				(void)i2c->hw->clr_tx_abrt;
+                (void)i2c->hw->clr_tx_abrt;
-				abort = true;
+                abort = true;
-			}
+            }
 
-			if (abort || (last && !nostop)) {
+            if (abort || (last && !nostop)) {
-				do {
+                do {
-					if (timeout_check) {
+                    if (timeout_check) {
-						timeout = timeout_check(ts);
+                        timeout = timeout_check(ts);
-						abort |= timeout;
+                        abort |= timeout;
-					}
+                    }
-					tight_loop_contents();
+                    tight_loop_contents();
-				} while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_STOP_DET_BITS));
+                } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_STOP_DET_BITS));
 
-				if (!timeout) (void)i2c->hw->clr_stop_det;
+                if (!timeout) (void)i2c->hw->clr_stop_det;
-				else
+                else
-					// if we had a timeout, send an abort request to the hardware,
+                    // if we had a timeout, send an abort request to the hardware,
-					// so that the bus gets released
+                    // so that the bus gets released
-					i2cex_abort_xfer(i2c);
+                    i2cex_abort_xfer(i2c);
-			}
+            }
-		} else i2cex_abort_xfer(i2c);
+        } else i2cex_abort_xfer(i2c);
 
-		if (abort) break;
+        if (abort) break;
-	}
+    }
 
-	int rval;
+    int rval;
 
-	if (abort) {
+    if (abort) {
-		const int addr_noack = I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS
+        const int addr_noack = I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS
-		                     | I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS
+                             | I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS
-		                     | I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS;
+                             | I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS;
 
-		if (timeout) rval = PICO_ERROR_TIMEOUT;
+        if (timeout) rval = PICO_ERROR_TIMEOUT;
-		else if (!abort_reason || (abort_reason & addr_noack))
+        else if (!abort_reason || (abort_reason & addr_noack))
-			rval = PICO_ERROR_GENERIC;
+            rval = PICO_ERROR_GENERIC;
-		else if (abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS)
+        else if (abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS)
-			rval = byte_ctr;
+            rval = byte_ctr;
-		else rval = PICO_ERROR_GENERIC;
+        else rval = PICO_ERROR_GENERIC;
-	} else rval = byte_ctr;
+    } else rval = byte_ctr;
 
-	i2c->restart_on_next = nostop;
+    i2c->restart_on_next = nostop;
-	return rval;
+    return rval;
 }
 static int i2cex_read_blocking_until(i2c_inst_t* i2c, uint16_t addr, bool a10bit,
-		uint8_t* dst, size_t len, bool nostop, absolute_time_t until) {
+        uint8_t* dst, size_t len, bool nostop, absolute_time_t until) {
-	timeout_state_t ts_;
+    timeout_state_t ts_;
-	struct timeout_state* ts = &ts_;
+    struct timeout_state* ts = &ts_;
-	check_timeout_fn timeout_check = init_single_timeout_until(&ts_, until);
+    check_timeout_fn timeout_check = init_single_timeout_until(&ts_, until);
 
-	if ((int)len < 0) return PICO_ERROR_GENERIC;
+    if ((int)len < 0) return PICO_ERROR_GENERIC;
-	if (a10bit) { // addr too high
+    if (a10bit) { // addr too high
-		if (addr & ~(uint16_t)((1<<10)-1)) return PICO_ERROR_GENERIC;
+        if (addr & ~(uint16_t)((1<<10)-1)) return PICO_ERROR_GENERIC;
-	} else if (addr & 0x80)
+    } else if (addr & 0x80)
-		return PICO_ERROR_GENERIC;
+        return PICO_ERROR_GENERIC;
 
-	i2c->hw->enable = 0;
+    i2c->hw->enable = 0;
-	// enable 10bit mode if requested
+    // enable 10bit mode if requested
-	hw_write_masked(&i2c->hw->con, I2C_IC_CON_IC_10BITADDR_MASTER_BITS, (a10bit
+    hw_write_masked(&i2c->hw->con, I2C_IC_CON_IC_10BITADDR_MASTER_BITS, (a10bit
-			? I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS
+            ? I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS
-			: I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS ) << I2C_IC_CON_IC_10BITADDR_MASTER_LSB);
+            : I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS ) << I2C_IC_CON_IC_10BITADDR_MASTER_LSB);
-	i2c->hw->tar = addr;
+    i2c->hw->tar = addr;
-	i2c->hw->enable = 1;
+    i2c->hw->enable = 1;
 
-	if (len == 0) return i2cex_probe_address(addr, a10bit);
+    if (len == 0) return i2cex_probe_address(addr, a10bit);
 
-	bool abort = false, timeout = false;
+    bool abort = false, timeout = false;
-	uint32_t abort_reason = 0;
+    uint32_t abort_reason = 0;
-	int byte_ctr;
+    int byte_ctr;
 
-	for (byte_ctr = 0; byte_ctr < (int)len; ++byte_ctr) {
+    for (byte_ctr = 0; byte_ctr < (int)len; ++byte_ctr) {
-		bool first = byte_ctr == 0;
+        bool first = byte_ctr == 0;
-		bool last  = byte_ctr == (int)len - 1;
+        bool last  = byte_ctr == (int)len - 1;
 
-		while (!i2c_get_write_available(i2c) && !abort) {
+        while (!i2c_get_write_available(i2c) && !abort) {
-			tight_loop_contents();
+            tight_loop_contents();
-			// ?
+            // ?
-			if (timeout_check) {
+            if (timeout_check) {
-				timeout = timeout_check(ts);
+                timeout = timeout_check(ts);
-				abort |= timeout;
+                abort |= timeout;
-			}
+            }
-		}
+        }
 
-		if (timeout) {
+        if (timeout) {
-			// if we had a timeout, send an abort request to the hardware,
+            // if we had a timeout, send an abort request to the hardware,
-			// so that the bus gets released
+            // so that the bus gets released
-			i2cex_abort_xfer(i2c);
+            i2cex_abort_xfer(i2c);
-		}
+        }
-		if (abort) break;
+        if (abort) break;
 
-		i2c->hw->data_cmd =
+        i2c->hw->data_cmd =
-			bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
+            bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
-			bool_to_bit(last  && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
+            bool_to_bit(last  && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
-			I2C_IC_DATA_CMD_CMD_BITS; // -> 1 for read
+            I2C_IC_DATA_CMD_CMD_BITS; // -> 1 for read
 
-		do {
+        do {
-			abort_reason = i2c->hw->tx_abrt_source;
+            abort_reason = i2c->hw->tx_abrt_source;
-			abort = (bool)i2c->hw->clr_tx_abrt;
+            abort = (bool)i2c->hw->clr_tx_abrt;
 
-			if (timeout_check) {
+            if (timeout_check) {
-				timeout = timeout_check(ts);
+                timeout = timeout_check(ts);
-				abort |= timeout;
+                abort |= timeout;
-			}
+            }
-			tight_loop_contents(); // ?
+            tight_loop_contents(); // ?
-		} while (!abort && !i2c_get_read_available(i2c));
+        } while (!abort && !i2c_get_read_available(i2c));
 
-		if (timeout) {
+        if (timeout) {
-			// if we had a timeout, send an abort request to the hardware,
+            // if we had a timeout, send an abort request to the hardware,
-			// so that the bus gets released
+            // so that the bus gets released
-			i2cex_abort_xfer(i2c);
+            i2cex_abort_xfer(i2c);
-		}
+        }
-		if (abort) break;
+        if (abort) break;
 
-		uint8_t v = (uint8_t)i2c->hw->data_cmd;
+        uint8_t v = (uint8_t)i2c->hw->data_cmd;
-		//printf("\ngot read %02x\n", v);
+        //printf("\ngot read %02x\n", v);
-		*dst++ = v;
+        *dst++ = v;
-	}
+    }
 
-	int rval;
+    int rval;
 
-	if (abort) {
+    if (abort) {
-		//printf("\ngot abrt: ");
+        //printf("\ngot abrt: ");
-		const int addr_noack = I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS
+        const int addr_noack = I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS
-		                     | I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS
+                             | I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS
-		                     | I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS;
+                             | I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS;
 
-		if (timeout) { /*printf("timeout\n");*/ rval = PICO_ERROR_TIMEOUT; }
+        if (timeout) { /*printf("timeout\n");*/ rval = PICO_ERROR_TIMEOUT; }
-		else if (!abort_reason || (abort_reason & addr_noack)) {//printf("disconn\n");
+        else if (!abort_reason || (abort_reason & addr_noack)) {//printf("disconn\n");
-			rval = PICO_ERROR_GENERIC; }
+            rval = PICO_ERROR_GENERIC; }
-		else {/*printf("unk\n");*/ rval = PICO_ERROR_GENERIC;}
+        else {/*printf("unk\n");*/ rval = PICO_ERROR_GENERIC;}
-	} else rval = byte_ctr;
+    } else rval = byte_ctr;
 
-	i2c->restart_on_next = nostop;
+    i2c->restart_on_next = nostop;
-	return rval;
+    return rval;
 }
 static inline int i2cex_write_timeout_us(i2c_inst_t* i2c, uint16_t addr, bool a10bit,
-		const uint8_t* src, size_t len, bool nostop, uint32_t timeout_us) {
+        const uint8_t* src, size_t len, bool nostop, uint32_t timeout_us) {
-	absolute_time_t t = make_timeout_time_us(timeout_us);
+    absolute_time_t t = make_timeout_time_us(timeout_us);
-	return i2cex_write_blocking_until(i2c, addr, a10bit, src, len, nostop, t);
+    return i2cex_write_blocking_until(i2c, addr, a10bit, src, len, nostop, t);
 }
 static inline int i2cex_read_timeout_us(i2c_inst_t* i2c, uint16_t addr, bool a10bit,
-		uint8_t* dst, size_t len, bool nostop, uint32_t timeout_us) {
+        uint8_t* dst, size_t len, bool nostop, uint32_t timeout_us) {
-	absolute_time_t t = make_timeout_time_us(timeout_us);
+    absolute_time_t t = make_timeout_time_us(timeout_us);
-	return i2cex_read_blocking_until(i2c, addr, a10bit, dst, len, nostop, t);
+    return i2cex_read_blocking_until(i2c, addr, a10bit, dst, len, nostop, t);
 }
 
 __attribute__((__const__))
 enum ki2c_funcs i2ctu_get_func(void) {
-	// TODO: SMBUS_EMUL_ALL => I2C_M_RECV_LEN
+    // TODO: SMBUS_EMUL_ALL => I2C_M_RECV_LEN
-	// TODO: maybe also PROTOCOL_MANGLING, NOSTART
+    // TODO: maybe also PROTOCOL_MANGLING, NOSTART
-	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+    return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 }
 
 void i2ctu_init(void) {
-	// default to 100 kHz (SDK example default so should be ok)
+    // default to 100 kHz (SDK example default so should be ok)
-	delay = 10; delay2 = 5;
+    delay = 10; delay2 = 5;
-	i2c_init(PINOUT_I2C_DEV, 100*1000);
+    i2c_init(PINOUT_I2C_DEV, 100*1000);
 
-	gpio_set_function(PINOUT_I2C_SCL, GPIO_FUNC_I2C);
+    gpio_set_function(PINOUT_I2C_SCL, GPIO_FUNC_I2C);
-	gpio_set_function(PINOUT_I2C_SDA, GPIO_FUNC_I2C);
+    gpio_set_function(PINOUT_I2C_SDA, GPIO_FUNC_I2C);
-	gpio_pull_up(PINOUT_I2C_SCL);
+    gpio_pull_up(PINOUT_I2C_SCL);
-	gpio_pull_up(PINOUT_I2C_SDA);
+    gpio_pull_up(PINOUT_I2C_SDA);
 
-	bi_decl(bi_2pins_with_func(PINOUT_I2C_SCL, PINOUT_I2C_SDA, GPIO_FUNC_I2C));
+    bi_decl(bi_2pins_with_func(PINOUT_I2C_SCL, PINOUT_I2C_SDA, GPIO_FUNC_I2C));
 }
 
 uint32_t i2ctu_set_freq(uint32_t freq, uint32_t us) {
-	delay = us;
+    delay = us;
-	delay2 = us >> 1;
+    delay2 = us >> 1;
-	if (!delay2) delay2 = 1;
+    if (!delay2) delay2 = 1;
 
-	return i2c_set_baudrate(PINOUT_I2C_DEV, freq);
+    return i2c_set_baudrate(PINOUT_I2C_DEV, freq);
 }
 
 enum itu_status i2ctu_write(enum ki2c_flags flags, enum itu_command startstopflags,
-		uint16_t addr, const uint8_t* buf, size_t len) {
+        uint16_t addr, const uint8_t* buf, size_t len) {
-	bool nostop = !(startstopflags & ITU_CMD_I2C_IO_END);
+    bool nostop = !(startstopflags & ITU_CMD_I2C_IO_END);
-	//printf("nostop=%c ", nostop?'t':'f');
+    //printf("nostop=%c ", nostop?'t':'f');
-	bool bit10 = flags & I2C_M_TEN;
+    bool bit10 = flags & I2C_M_TEN;
 
-	/*if (len == 0) {
+    /*if (len == 0) {
-		// do a read, that's less hazardous
+        // do a read, that's less hazardous
-		uint8_t stuff = 0;
+        uint8_t stuff = 0;
-		int rv = i2cex_read_timeout_us(PINOUT_I2C_DEV, addr, bit10, &stuff, 1,
+        int rv = i2cex_read_timeout_us(PINOUT_I2C_DEV, addr, bit10, &stuff, 1,
-				nostop, 1000*1000);
+                nostop, 1000*1000);
-		if (rv < 0) return ITU_STATUS_ADDR_NAK;
+        if (rv < 0) return ITU_STATUS_ADDR_NAK;
-		return ITU_STATUS_ADDR_ACK;
+        return ITU_STATUS_ADDR_ACK;
-	} else*/ {
+    } else*/ {
-		int rv = i2cex_write_timeout_us(PINOUT_I2C_DEV, addr, bit10, buf, len,
+        int rv = i2cex_write_timeout_us(PINOUT_I2C_DEV, addr, bit10, buf, len,
-				nostop, 1000*1000);
+                nostop, 1000*1000);
-		if (rv < 0 || (size_t)rv < len) return ITU_STATUS_ADDR_NAK;
+        if (rv < 0 || (size_t)rv < len) return ITU_STATUS_ADDR_NAK;
-		return ITU_STATUS_ADDR_ACK;
+        return ITU_STATUS_ADDR_ACK;
-	}
+    }
 }
 enum itu_status i2ctu_read(enum ki2c_flags flags, enum itu_command startstopflags,
-		uint16_t addr, uint8_t* buf, size_t len) {
+        uint16_t addr, uint8_t* buf, size_t len) {
-	bool nostop = !(startstopflags & ITU_CMD_I2C_IO_END);
+    bool nostop = !(startstopflags & ITU_CMD_I2C_IO_END);
-	//printf("nostop=%c ", nostop?'t':'f');
+    //printf("nostop=%c ", nostop?'t':'f');
-	bool bit10 = flags & I2C_M_TEN;
+    bool bit10 = flags & I2C_M_TEN;
 
-	/*if (len == 0) {
+    /*if (len == 0) {
-		uint8_t stuff = 0;
+        uint8_t stuff = 0;
-		int rv = i2cex_read_timeout_us(PINOUT_I2C_DEV, addr, bit10, &stuff, 1,
+        int rv = i2cex_read_timeout_us(PINOUT_I2C_DEV, addr, bit10, &stuff, 1,
-				nostop, 1000*1000);
+                nostop, 1000*1000);
-		if (rv < 0) return ITU_STATUS_ADDR_NAK;
+        if (rv < 0) return ITU_STATUS_ADDR_NAK;
-		return ITU_STATUS_ADDR_ACK;
+        return ITU_STATUS_ADDR_ACK;
-	} else*/ {
+    } else*/ {
-		int rv = i2cex_read_timeout_us(PINOUT_I2C_DEV, addr, bit10, buf, len,
+        int rv = i2cex_read_timeout_us(PINOUT_I2C_DEV, addr, bit10, buf, len,
-				nostop, 1000*1000);
+                nostop, 1000*1000);
-		//printf("p le rv=%d buf=%02x ", rv, buf[0]);
+        //printf("p le rv=%d buf=%02x ", rv, buf[0]);
-		if (rv < 0 || (size_t)rv < len) return ITU_STATUS_ADDR_NAK;
+        if (rv < 0 || (size_t)rv < len) return ITU_STATUS_ADDR_NAK;
-		return ITU_STATUS_ADDR_ACK;
+        return ITU_STATUS_ADDR_ACK;
-	}
+    }
 }
 

bsp/rp2040/protocfg.h

@@ -9,21 +9,21 @@
 #define DBOARD_HAS_TEMPSENSOR
 
 enum {
-	HID_N_CMSISDAP = 0,
+    HID_N_CMSISDAP = 0,
 
-	HID_N__NITF
+    HID_N__NITF
 };
 enum {
-	CDC_N_UART = 0,
+    CDC_N_UART = 0,
-	CDC_N_SERPROG,
+    CDC_N_SERPROG,
 #ifdef USE_USBCDC_FOR_STDIO
-	CDC_N_STDIO,
+    CDC_N_STDIO,
 #endif
 
-	CDC_N__NITF
+    CDC_N__NITF
 };
 enum {
-	VND_N__NITF = 0
+    VND_N__NITF = 0
 };
 
 #define CFG_TUD_HID 1

bsp/rp2040/spi_serprog.c

@@ -13,62 +13,62 @@
 static bool cs_asserted;
 
 void sp_spi_init(void) {
-	//printf("spi init!\n");
+    //printf("spi init!\n");
 
-	cs_asserted = false;
+    cs_asserted = false;
 
-	spi_init(PINOUT_SPI_DEV, 512*1000); // default to 512 kHz
+    spi_init(PINOUT_SPI_DEV, 512*1000); // default to 512 kHz
 
-	gpio_set_function(PINOUT_SPI_MISO, GPIO_FUNC_SPI);
+    gpio_set_function(PINOUT_SPI_MISO, GPIO_FUNC_SPI);
-	gpio_set_function(PINOUT_SPI_MOSI, GPIO_FUNC_SPI);
+    gpio_set_function(PINOUT_SPI_MOSI, GPIO_FUNC_SPI);
-	gpio_set_function(PINOUT_SPI_SCLK, GPIO_FUNC_SPI);
+    gpio_set_function(PINOUT_SPI_SCLK, GPIO_FUNC_SPI);
 
-	//gpio_set_function(PINOUT_SPI_nCS, GPIO_FUNC_SIO);
+    //gpio_set_function(PINOUT_SPI_nCS, GPIO_FUNC_SIO);
-	gpio_init(PINOUT_SPI_nCS);
+    gpio_init(PINOUT_SPI_nCS);
-	gpio_put(PINOUT_SPI_nCS, 1);
+    gpio_put(PINOUT_SPI_nCS, 1);
-	gpio_set_dir(PINOUT_SPI_nCS, GPIO_OUT);
+    gpio_set_dir(PINOUT_SPI_nCS, GPIO_OUT);
 
-	bi_decl(bi_3pins_with_func(PINOUT_SPI_MISO, PINOUT_SPI_MOSI, PINOUT_SPI_SCLK, GPIO_FUNC_SPI));
+    bi_decl(bi_3pins_with_func(PINOUT_SPI_MISO, PINOUT_SPI_MOSI, PINOUT_SPI_SCLK, GPIO_FUNC_SPI));
-	bi_decl(bi_1pin_with_name(PINOUT_SPI_nCS, "SPI #CS"));
+    bi_decl(bi_1pin_with_name(PINOUT_SPI_nCS, "SPI #CS"));
 }
 uint32_t __not_in_flash_func(sp_spi_set_freq)(uint32_t freq_wanted) {
-	return spi_set_baudrate(PINOUT_SPI_DEV, freq_wanted);
+    return spi_set_baudrate(PINOUT_SPI_DEV, freq_wanted);
 }
 void __not_in_flash_func(sp_spi_cs_deselect)(void) {
-	asm volatile("nop\nnop\nnop"); // idk if this is needed
+    asm volatile("nop\nnop\nnop"); // idk if this is needed
-	gpio_put(PINOUT_SPI_nCS, 1);
+    gpio_put(PINOUT_SPI_nCS, 1);
-	asm volatile("nop\nnop\nnop"); // idk if this is needed
+    asm volatile("nop\nnop\nnop"); // idk if this is needed
-	cs_asserted = false;
+    cs_asserted = false;
 }
 void __not_in_flash_func(sp_spi_cs_select)(void) {
-	asm volatile("nop\nnop\nnop"); // idk if this is needed
+    asm volatile("nop\nnop\nnop"); // idk if this is needed
-	gpio_put(PINOUT_SPI_nCS, 0);
+    gpio_put(PINOUT_SPI_nCS, 0);
-	asm volatile("nop\nnop\nnop"); // idk if this is needed
+    asm volatile("nop\nnop\nnop"); // idk if this is needed
-	cs_asserted = true;
+    cs_asserted = true;
 }
 
 void __not_in_flash_func(sp_spi_op_begin)(void) {
-	//sp_spi_cs_select();
+    //sp_spi_cs_select();
-	if (!cs_asserted) {
+    if (!cs_asserted) {
-		asm volatile("nop\nnop\nnop"); // idk if this is needed
+        asm volatile("nop\nnop\nnop"); // idk if this is needed
-		gpio_put(PINOUT_SPI_nCS, 0);
+        gpio_put(PINOUT_SPI_nCS, 0);
-		asm volatile("nop\nnop\nnop"); // idk if this is needed
+        asm volatile("nop\nnop\nnop"); // idk if this is needed
-	}
+    }
 }
 void __not_in_flash_func(sp_spi_op_end)(void) {
-	//sp_spi_cs_deselect();
+    //sp_spi_cs_deselect();
-	if (!cs_asserted) { // YES, this condition is the intended one!
+    if (!cs_asserted) { // YES, this condition is the intended one!
-		asm volatile("nop\nnop\nnop"); // idk if this is needed
+        asm volatile("nop\nnop\nnop"); // idk if this is needed
-		gpio_put(PINOUT_SPI_nCS, 1);
+        gpio_put(PINOUT_SPI_nCS, 1);
-		asm volatile("nop\nnop\nnop"); // idk if this is needed
+        asm volatile("nop\nnop\nnop"); // idk if this is needed
-	}
+    }
 }
 
 // TODO: use dma?
 void __not_in_flash_func(sp_spi_op_write)(uint32_t write_len, const uint8_t* write_data) {
-	spi_write_blocking(PINOUT_SPI_DEV, write_data, write_len);
+    spi_write_blocking(PINOUT_SPI_DEV, write_data, write_len);
 }
 void __not_in_flash_func(sp_spi_op_read)(uint32_t read_len, uint8_t* read_data) {
-	spi_read_blocking(PINOUT_SPI_DEV, 0, read_data, read_len);
+    spi_read_blocking(PINOUT_SPI_DEV, 0, read_data, read_len);
 }
 

bsp/rp2040/tempsensor.c

@@ -15,29 +15,29 @@
 // convert x.4 fixed to 8.4 fixed
 __attribute__((__const__))
 inline static int16_t trunc_8fix4(int fix) {
-	if (fix >  4095) fix =  4095;
+    if (fix >  4095) fix =  4095;
-	if (fix < -4096) fix = -4096;
+    if (fix < -4096) fix = -4096;
-	return fix;
+    return fix;
 }
 
 void tempsense_dev_init(void) {
-	adc_init();
+    adc_init();
-	adc_set_temp_sensor_enabled(true);
+    adc_set_temp_sensor_enabled(true);
 }
 // 8.4
 int16_t tempsense_dev_get_temp(void) {
-	adc_select_input(4); // select temp sensor
+    adc_select_input(4); // select temp sensor
-	uint16_t result = adc_read();
+    uint16_t result = adc_read();
 
-	float voltage = result * (V_MAX / D_RANGE);
+    float voltage = result * (V_MAX / D_RANGE);
 
-	float tempf = T_OFF + (voltage - T_BIAS) / T_SLOPE;
+    float tempf = T_OFF + (voltage - T_BIAS) / T_SLOPE;
 
-	// FIXME: use fixed point instead! but something's wrong with the formula below
+    // FIXME: use fixed point instead! but something's wrong with the formula below
-	/*int temperature = float2fix(T_OFF - T_BIAS / T_SLOPE)
+    /*int temperature = float2fix(T_OFF - T_BIAS / T_SLOPE)
-		+ (int)result * float2fix(V_MAX / (D_RANGE * T_SLOPE));*/
+        + (int)result * float2fix(V_MAX / (D_RANGE * T_SLOPE));*/
 
-	return trunc_8fix4(/*temperature*/float2fix(tempf));
+    return trunc_8fix4(/*temperature*/float2fix(tempf));
 }
 
 // RP2040 absolute min/max are -20/85

bsp/rp2040/unique.c

@@ -6,36 +6,36 @@
 #include "util.h"
 
 uint8_t get_unique_id_u8(uint8_t *desc_str) {
-	pico_unique_board_id_t uid;
+    pico_unique_board_id_t uid;
-	uint8_t chr_count = 0;
+    uint8_t chr_count = 0;
 
-	pico_get_unique_board_id(&uid);
+    pico_get_unique_board_id(&uid);
 
-	for (int byte = 0; byte < TU_ARRAY_SIZE(uid.id); byte++) {
+    for (int byte = 0; byte < TU_ARRAY_SIZE(uid.id); byte++) {
-		uint8_t tmp = uid.id[byte];
+        uint8_t tmp = uid.id[byte];
-		for (int digit = 0; digit < 2; digit++) {
+        for (int digit = 0; digit < 2; digit++) {
-			desc_str[chr_count++] = nyb2hex(tmp & 0xf);
+            desc_str[chr_count++] = nyb2hex(tmp & 0xf);
-			tmp >>= 4;
+            tmp >>= 4;
-		}
+        }
-	}
+    }
 
-	return chr_count;
+    return chr_count;
 }
 
 uint8_t get_unique_id_u16(uint16_t *desc_str) {
-	pico_unique_board_id_t uid;
+    pico_unique_board_id_t uid;
-	uint8_t chr_count = 0;
+    uint8_t chr_count = 0;
 
-	pico_get_unique_board_id(&uid);
+    pico_get_unique_board_id(&uid);
 
-	for (int byte = 0; byte < TU_ARRAY_SIZE(uid.id); byte++) {
+    for (int byte = 0; byte < TU_ARRAY_SIZE(uid.id); byte++) {
-		uint8_t tmp = uid.id[byte];
+        uint8_t tmp = uid.id[byte];
-		for (int digit = 0; digit < 2; digit++) {
+        for (int digit = 0; digit < 2; digit++) {
-			desc_str[chr_count++] = nyb2hex(tmp & 0xf);
+            desc_str[chr_count++] = nyb2hex(tmp & 0xf);
-			tmp >>= 4;
+            tmp >>= 4;
-		}
+        }
-	}
+    }
 
-	return chr_count;
+    return chr_count;
 }
 

bsp/stm32f072disco/DAP_config.h

@@ -137,9 +137,9 @@ This information includes:
 \return String length.
 */
 __STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
-	const static char vnd[] = INFO_MANUFACTURER;
+    const static char vnd[] = INFO_MANUFACTURER;
-	for (size_t i = 0; i < sizeof(vnd); ++i) str[i] = vnd[i];
+    for (size_t i = 0; i < sizeof(vnd); ++i) str[i] = vnd[i];
-	return sizeof(vnd)-1;
+    return sizeof(vnd)-1;
 }
 
 /** Get Product ID string.
@@ -147,9 +147,9 @@ __STATIC_INLINE uint8_t DAP_GetVendorString (char *str) {
 \return String length.
 */
 __STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
-	const static char prd[] = INFO_PRODUCT(INFO_BOARDNAME);
+    const static char prd[] = INFO_PRODUCT(INFO_BOARDNAME);
-	for (size_t i = 0; i < sizeof(prd); ++i) str[i] = prd[i];
+    for (size_t i = 0; i < sizeof(prd); ++i) str[i] = prd[i];
-	return sizeof(prd)-1;
+    return sizeof(prd)-1;
 }
 
 /** Get Serial Number string.
@@ -157,7 +157,7 @@ __STATIC_INLINE uint8_t DAP_GetProductString (char *str) {
 \return String length.
 */
 __STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) {
-	return get_unique_id_u8(str);
+    return get_unique_id_u8(str);
 }
 
 ///@}
@@ -232,7 +232,7 @@ Configures the DAP Hardware I/O pins for JTAG mode:
  - TDO to input mode.
 */
 __STATIC_INLINE void PORT_JTAG_SETUP (void) {
-	;
+    ;
 }
  
 /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
@@ -241,10 +241,10 @@ Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
  - TDI, nTRST to HighZ mode (pins are unused in SWD mode).
 */
 __STATIC_INLINE void PORT_SWD_SETUP (void) {
-	CLK_ENABLE;
+    CLK_ENABLE;
-	DATA_ENABLE;
+    DATA_ENABLE;
-	SWDIO_INIT;
+    SWDIO_INIT;
-	CLK_HIGH; DATA_HIGH;
+    CLK_HIGH; DATA_HIGH;
 }
 
 /** Disable JTAG/SWD I/O Pins.
@@ -252,9 +252,9 @@ Disables the DAP Hardware I/O pins which configures:
  - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
 */
 __STATIC_INLINE void PORT_OFF (void) {
-	CLK_HIZ;
+    CLK_HIZ;
-	DATA_HIZ;
+    DATA_HIZ;
-	RESET_HIZ;
+    RESET_HIZ;
 }
 
 // SWCLK/TCK I/O pin -------------------------------------
@@ -263,21 +263,21 @@ __STATIC_INLINE void PORT_OFF (void) {
 \return Current status of the SWCLK/TCK DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN  (void) {
-	return (CLK_READ) ? 1 : 0;
+    return (CLK_READ) ? 1 : 0;
 }
 
 /** SWCLK/TCK I/O pin: Set Output to High.
 Set the SWCLK/TCK DAP hardware I/O pin to high level.
 */
 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_SET (void) {
-	CLK_HIGH;
+    CLK_HIGH;
 }
 
 /** SWCLK/TCK I/O pin: Set Output to Low.
 Set the SWCLK/TCK DAP hardware I/O pin to low level.
 */
 __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
-	CLK_LOW;
+    CLK_LOW;
 }
 
 
@@ -287,35 +287,35 @@ __STATIC_FORCEINLINE void     PIN_SWCLK_TCK_CLR (void) {
 \return Current status of the SWDIO/TMS DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN  (void) {
-	return (DATA_READ) ? 1 : 0;
+    return (DATA_READ) ? 1 : 0;
 }
 
 /** SWDIO/TMS I/O pin: Set Output to High.
 Set the SWDIO/TMS DAP hardware I/O pin to high level.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_SET (void) {
-	DATA_HIGH;
+    DATA_HIGH;
 }
 
 /** SWDIO/TMS I/O pin: Set Output to Low.
 Set the SWDIO/TMS DAP hardware I/O pin to low level.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_TMS_CLR (void) {
-	DATA_LOW;
+    DATA_LOW;
 }
 
 /** SWDIO I/O pin: Get Input (used in SWD mode only).
 \return Current status of the SWDIO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN      (void) {
-	return (DATA_READ) ? 1 : 0;
+    return (DATA_READ) ? 1 : 0;
 }
 
 /** SWDIO I/O pin: Set Output (used in SWD mode only).
 \param bit Output value for the SWDIO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT     (uint32_t bit) {
-	if (bit & 1) { DATA_HIGH; } else { DATA_LOW; }
+    if (bit & 1) { DATA_HIGH; } else { DATA_LOW; }
 }
 
 /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
@@ -323,7 +323,7 @@ Configure the SWDIO DAP hardware I/O pin to output mode. This function is
 called prior \ref PIN_SWDIO_OUT function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_ENABLE  (void) {
-	DATA_ENABLE;
+    DATA_ENABLE;
 }
 
 /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
@@ -331,7 +331,7 @@ Configure the SWDIO DAP hardware I/O pin to input mode. This function is
 called prior \ref PIN_SWDIO_IN function calls.
 */
 __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
-	DATA_HIZ;
+    DATA_HIZ;
 }
 
 
@@ -341,14 +341,14 @@ __STATIC_FORCEINLINE void     PIN_SWDIO_OUT_DISABLE (void) {
 \return Current status of the TDI DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_TDI_IN  (void) {
-	return (0U);
+    return (0U);
 }
 
 /** TDI I/O pin: Set Output.
 \param bit Output value for the TDI DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
-	;
+    ;
 }
 
 
@@ -358,7 +358,7 @@ __STATIC_FORCEINLINE void     PIN_TDI_OUT (uint32_t bit) {
 \return Current status of the TDO DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void) {
-	return (0U);
+    return (0U);
 }
 
 
@@ -368,7 +368,7 @@ __STATIC_FORCEINLINE uint32_t PIN_TDO_IN  (void) {
 \return Current status of the nTRST DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void) {
-	return (0U);
+    return (0U);
 }
 
 /** nTRST I/O pin: Set Output.
@@ -377,7 +377,7 @@ __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN   (void) {
            - 1: release JTAG TRST Test Reset.
 */
 __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
-	(void)bit;
+    (void)bit;
 }
 
 // nRESET Pin I/O------------------------------------------
@@ -386,7 +386,7 @@ __STATIC_FORCEINLINE void     PIN_nTRST_OUT  (uint32_t bit) {
 \return Current status of the nRESET DAP hardware I/O pin.
 */
 __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void) {
-	return (RESET_READ) ? 1 : 0;
+    return (RESET_READ) ? 1 : 0;
 }
 
 /** nRESET I/O pin: Set Output.
@@ -395,7 +395,7 @@ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN  (void) {
            - 1: release device hardware reset.
 */
 __STATIC_FORCEINLINE void     PIN_nRESET_OUT (uint32_t bit) {
-	if (bit & 1) { RESET_HIGH; } else { RESET_LOW; }
+    if (bit & 1) { RESET_HIGH; } else { RESET_LOW; }
 }
 
 ///@}
@@ -420,7 +420,7 @@ It is recommended to provide the following LEDs for status indication:
            - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
 */
 __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
-	(void)bit;
+    (void)bit;
 }
 
 /** Debug Unit: Set status Target Running LED.
@@ -429,7 +429,7 @@ __STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) {
            - 0: Target Running LED OFF: program execution in target stopped.
 */
 __STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) {
-	(void)bit;
+    (void)bit;
 }
 
 ///@}
@@ -452,9 +452,9 @@ default, the DWT timer is used.  The frequency of this timer is configured with
 */
 __STATIC_INLINE uint32_t TIMESTAMP_GET (void) {
 #if TIMESTAMP_CLOCK > 0
-	return (DWT->CYCCNT);
+    return (DWT->CYCCNT);
 #else
-	return 0;
+    return 0;
 #endif
 }
 
@@ -479,7 +479,7 @@ Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled an
  - LED output pins are enabled and LEDs are turned off.
 */
 __STATIC_INLINE void DAP_SETUP (void) {
-	;
+    ;
 }
 
 /** Reset Target Device with custom specific I/O pin or command sequence.
@@ -490,7 +490,7 @@ when a device needs a time-critical unlock sequence that enables the debug port.
         1 = a device specific reset sequence is implemented.
 */
 __STATIC_INLINE uint8_t RESET_TARGET (void) {
-	return (0U);             // change to '1' when a device reset sequence is implemented
+    return (0U);             // change to '1' when a device reset sequence is implemented
 }
 
 ///@}

bsp/stm32f072disco/cdc_stdio.c

@@ -2,6 +2,6 @@
 #include "protos.h"
 
 bool stdio_usb_init(void) {
-	return true;
+    return true;
 }
 

bsp/stm32f072disco/i2c_tinyusb.c

@@ -4,22 +4,22 @@
 
 __attribute__((__const__))
 enum ki2c_funcs i2ctu_get_func(void) {
-	return 0;
+    return 0;
 }
 
 void i2ctu_init(void) {
 }
 
 uint32_t i2ctu_set_freq(uint32_t freq) {
-	return 0;
+    return 0;
 }
 
 enum itu_status i2ctu_write(enum ki2c_flags flags, enum itu_command startstopflags,
-		uint16_t addr, const uint8_t* buf, size_t len) {
+        uint16_t addr, const uint8_t* buf, size_t len) {
-	return ITU_STATUS_IDLE;
+    return ITU_STATUS_IDLE;
 }
 enum itu_status i2ctu_read(enum ki2c_flags flags, enum itu_command startstopflags,
-		uint16_t addr, uint8_t* buf, size_t len) {
+        uint16_t addr, uint8_t* buf, size_t len) {
-	return ITU_STATUS_IDLE;
+    return ITU_STATUS_IDLE;
 }
 

bsp/stm32f072disco/protocfg.h

@@ -8,15 +8,15 @@
 /*#define DBOARD_HAS_TINYI2C*/
 
 enum {
-	HID_N_CMSISDAP = 0,
+    HID_N_CMSISDAP = 0,
 
-	HID_N__NITF
+    HID_N__NITF
 };
 enum {
-	CDC_N__NITF
+    CDC_N__NITF
 };
 enum {
-	VND_N__NITF = 0
+    VND_N__NITF = 0
 };
 
 #define CFG_TUD_HID 1

bsp/stm32f072disco/spi_serprog.c

@@ -4,7 +4,7 @@
 void sp_spi_init(void) {
 }
 uint32_t sp_spi_set_freq(uint32_t freq_wanted) {
-	return 0;
+    return 0;
 }
 void sp_spi_cs_deselect(void) {
 }

bsp/stm32f072disco/unique.c

@@ -4,30 +4,30 @@
 #include "util.h"
 
 uint8_t get_unique_id_u8(uint8_t *desc_str) {
-	const uint32_t *idpnt = (uint32_t*)(0x1FFFF7AC); /*DEVICE_ID1*/
+    const uint32_t *idpnt = (uint32_t*)(0x1FFFF7AC); /*DEVICE_ID1*/
-	uint32_t tmp = 0;
+    uint32_t tmp = 0;
-	uint8_t chr_count = 0;
+    uint8_t chr_count = 0;
 
-	for (int digit = 0; digit < 24; digit++) {
+    for (int digit = 0; digit < 24; digit++) {
-		if (0 == (digit & 7)) tmp = *idpnt++;
+        if (0 == (digit & 7)) tmp = *idpnt++;
-		desc_str[chr_count++] = nyb2hex(tmp & 0xf);
+        desc_str[chr_count++] = nyb2hex(tmp & 0xf);
-		tmp >>= 4;
+        tmp >>= 4;
-	}
+    }
 
-	return chr_count;
+    return chr_count;
 }
 
 uint8_t get_unique_id_u16(uint16_t *desc_str) {
-	const uint32_t *idpnt = (uint32_t*)(0x1FFFF7AC); /*DEVICE_ID1*/
+    const uint32_t *idpnt = (uint32_t*)(0x1FFFF7AC); /*DEVICE_ID1*/
-	uint32_t tmp = 0;
+    uint32_t tmp = 0;
-	uint8_t chr_count = 0;
+    uint8_t chr_count = 0;
 
-	for (int digit = 0; digit < 24; digit++) {
+    for (int digit = 0; digit < 24; digit++) {
-		if (0 == (digit & 7)) tmp = *idpnt++;
+        if (0 == (digit & 7)) tmp = *idpnt++;
-		desc_str[chr_count++] = nyb2hex(tmp & 0xf);
+        desc_str[chr_count++] = nyb2hex(tmp & 0xf);
-		tmp >>= 4;
+        tmp >>= 4;
-	}
+    }
 
-	return chr_count;
+    return chr_count;
 }
 

dmctl.py

@@ -7,7 +7,7 @@ def auto_int(x):
     return int(x, 0)
 
 class RTOpt(NamedTuple):
-    type: bool
+    type: Callable[[Any], Any]
     optid: int
     desc: str
 

i2c-tiny-usb-misc/i2c-tiny-usb.c

@@ -34,13 +34,13 @@
 static unsigned short delay = 10;
 module_param(delay, ushort, 0);
 MODULE_PARM_DESC(delay, "bit delay in microseconds "
-		 "(default is 10us for 100kHz max)");
+         "(default is 10us for 100kHz max)");
 
 static int usb_read(struct i2c_adapter *adapter, int cmd,
-		    int value, int index, void *data, int len);
+            int value, int index, void *data, int len);
 
 static int usb_write(struct i2c_adapter *adapter, int cmd,
-		     int value, int index, void *data, int len);
+             int value, int index, void *data, int len);
 
 /* ----- begin of i2c layer ---------------------------------------------- */
 
@@ -50,102 +50,102 @@ static int usb_write(struct i2c_adapter *adapter, int cmd,
 
 static int usb_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
 {
-	unsigned char *pstatus;
+    unsigned char *pstatus;
-	struct i2c_msg *pmsg;
+    struct i2c_msg *pmsg;
-	int i, ret, r;
+    int i, ret, r;
 
-	dev_dbg(&adapter->dev, "master xfer %d messages:\n", num);
+    dev_dbg(&adapter->dev, "master xfer %d messages:\n", num);
 
-	pstatus = kmalloc(sizeof(*pstatus), GFP_KERNEL);
+    pstatus = kmalloc(sizeof(*pstatus), GFP_KERNEL);
-	if (!pstatus)
+    if (!pstatus)
-		return -ENOMEM;
+        return -ENOMEM;
 
-	for (i = 0 ; i < num ; i++) {
+    for (i = 0 ; i < num ; i++) {
-		int cmd = CMD_I2C_IO;
+        int cmd = CMD_I2C_IO;
 
-		if (i == 0)
+        if (i == 0)
-			cmd |= CMD_I2C_IO_BEGIN;
+            cmd |= CMD_I2C_IO_BEGIN;
 
-		if (i == num-1)
+        if (i == num-1)
-			cmd |= CMD_I2C_IO_END;
+            cmd |= CMD_I2C_IO_END;
 
-		pmsg = &msgs[i];
+        pmsg = &msgs[i];
 
-		dev_dbg(&adapter->dev,
+        dev_dbg(&adapter->dev,
-			"  %d: %s (flags %d) %d bytes to 0x%02x\n",
+            "  %d: %s (flags %d) %d bytes to 0x%02x\n",
-			i, pmsg->flags & I2C_M_RD ? "read" : "write",
+            i, pmsg->flags & I2C_M_RD ? "read" : "write",
-			pmsg->flags, pmsg->len, pmsg->addr);
+            pmsg->flags, pmsg->len, pmsg->addr);
 
-		/* and directly send the message */
+        /* and directly send the message */
-		if (pmsg->flags & I2C_M_RD) {
+        if (pmsg->flags & I2C_M_RD) {
-			/* read data */
+            /* read data */
-			if ((r = usb_read(adapter, cmd,
+            if ((r = usb_read(adapter, cmd,
-				     pmsg->flags, pmsg->addr,
+                     pmsg->flags, pmsg->addr,
-				     pmsg->buf, pmsg->len)) != pmsg->len) {
+                     pmsg->buf, pmsg->len)) != pmsg->len) {
-				dev_err(&adapter->dev,
+                dev_err(&adapter->dev,
-					"failure reading data: %i\n", r);
+                    "failure reading data: %i\n", r);
-				ret = -EIO;
+                ret = -EIO;
-				goto out;
+                goto out;
-			}
+            }
-		} else {
+        } else {
-			/* write data */
+            /* write data */
-			if ((r = usb_write(adapter, cmd,
+            if ((r = usb_write(adapter, cmd,
-				      pmsg->flags, pmsg->addr,
+                      pmsg->flags, pmsg->addr,
-				      pmsg->buf, pmsg->len)) != pmsg->len) {
+                      pmsg->buf, pmsg->len)) != pmsg->len) {
-				dev_err(&adapter->dev,
+                dev_err(&adapter->dev,
-					"failure writing data: %i\n", r);
+                    "failure writing data: %i\n", r);
-				ret = -EIO;
+                ret = -EIO;
-				goto out;
+                goto out;
-			}
+            }
-		}
+        }
 
-		/* read status */
+        /* read status */
-		if ((r = usb_read(adapter, CMD_GET_STATUS, 0, 0, pstatus, 1)) != 1) {
+        if ((r = usb_read(adapter, CMD_GET_STATUS, 0, 0, pstatus, 1)) != 1) {
-			dev_err(&adapter->dev, "failure reading status: %i\n", r);
+            dev_err(&adapter->dev, "failure reading status: %i\n", r);
-			ret = -EIO;
+            ret = -EIO;
-			goto out;
+            goto out;
-		}
+        }
 
-		dev_dbg(&adapter->dev, "  status = %d\n", *pstatus);
+        dev_dbg(&adapter->dev, "  status = %d\n", *pstatus);
-		if (*pstatus == STATUS_ADDRESS_NAK) {
+        if (*pstatus == STATUS_ADDRESS_NAK) {
-			ret = -ENXIO;
+            ret = -ENXIO;
-			goto out;
+            goto out;
-		}
+        }
-	}
+    }
 
-	ret = i;
+    ret = i;
 out:
-	kfree(pstatus);
+    kfree(pstatus);
-	return ret;
+    return ret;
 }
 
 static u32 usb_func(struct i2c_adapter *adapter)
 {
-	__le32 *pfunc;
+    __le32 *pfunc;
-	u32 ret;
+    u32 ret;
-	int i=-1;
+    int i=-1;
 
-	pfunc = kmalloc(sizeof(*pfunc), GFP_KERNEL);
+    pfunc = kmalloc(sizeof(*pfunc), GFP_KERNEL);
 
-	/* get functionality from adapter */
+    /* get functionality from adapter */
-	if (!pfunc || (i=usb_read(adapter, CMD_GET_FUNC, 0, 0, pfunc,
+    if (!pfunc || (i=usb_read(adapter, CMD_GET_FUNC, 0, 0, pfunc,
-			       sizeof(*pfunc))) != sizeof(*pfunc)) {
+                   sizeof(*pfunc))) != sizeof(*pfunc)) {
-		dev_err(&adapter->dev, "failure reading functionality: %i\n", i);
+        dev_err(&adapter->dev, "failure reading functionality: %i\n", i);
-		ret = 0;
+        ret = 0;
-		goto out;
+        goto out;
-	}
+    }
 
-	ret = le32_to_cpup(pfunc);
+    ret = le32_to_cpup(pfunc);
-	//dev_warn(&adapter->dev, "itu func=%08x\n", ret);
+    //dev_warn(&adapter->dev, "itu func=%08x\n", ret);
 out:
-	kfree(pfunc);
+    kfree(pfunc);
-	return ret;
+    return ret;
 }
 
 /* This is the actual algorithm we define */
 static const struct i2c_algorithm usb_algorithm = {
-	.master_xfer	= usb_xfer,
+    .master_xfer	= usb_xfer,
-	.functionality	= usb_func,
+    .functionality	= usb_func,
 };
 
 /* ----- end of i2c layer ------------------------------------------------ */
@@ -158,152 +158,152 @@ static const struct i2c_algorithm usb_algorithm = {
  * bought from EZPrototypes
  */
 static const struct usb_device_id i2c_tiny_usb_table[] = {
-	{ USB_DEVICE(0x0403, 0xc631) },   /* FTDI */
+    { USB_DEVICE(0x0403, 0xc631) },   /* FTDI */
-	{ USB_DEVICE(0x1c40, 0x0534) },   /* EZPrototypes */
+    { USB_DEVICE(0x1c40, 0x0534) },   /* EZPrototypes */
-	{ /* TinyUSB DapperMime: we want the Vendor interface on I2C-enabled ones */
+    { /* TinyUSB DapperMime: we want the Vendor interface on I2C-enabled ones */
-	  .match_flags = USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION | USB_DEVICE_ID_MATCH_INT_CLASS,
+      .match_flags = USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION | USB_DEVICE_ID_MATCH_INT_CLASS,
-	  .idVendor = 0xcafe, .idProduct = 0x1312,
+      .idVendor = 0xcafe, .idProduct = 0x1312,
-	  .bcdDevice_lo = 0x6000, .bcdDevice_hi = 0x6fff,
+      .bcdDevice_lo = 0x6000, .bcdDevice_hi = 0x6fff,
-	  .bInterfaceClass = 0
+      .bInterfaceClass = 0
-	},
+    },
-	{ }                               /* Terminating entry */
+    { }                               /* Terminating entry */
 };
 
 MODULE_DEVICE_TABLE(usb, i2c_tiny_usb_table);
 
 /* Structure to hold all of our device specific stuff */
 struct i2c_tiny_usb {
-	struct usb_device *usb_dev; /* the usb device for this device */
+    struct usb_device *usb_dev; /* the usb device for this device */
-	struct usb_interface *interface; /* the interface for this device */
+    struct usb_interface *interface; /* the interface for this device */
-	struct i2c_adapter adapter; /* i2c related things */
+    struct i2c_adapter adapter; /* i2c related things */
 };
 
 static int usb_read(struct i2c_adapter *adapter, int cmd,
-		    int value, int index, void *data, int len)
+            int value, int index, void *data, int len)
 {
-	struct i2c_tiny_usb *dev = (struct i2c_tiny_usb *)adapter->algo_data;
+    struct i2c_tiny_usb *dev = (struct i2c_tiny_usb *)adapter->algo_data;
-	uint8_t *dmadata;
+    uint8_t *dmadata;
-	int ret;
+    int ret;
 
-	dmadata = kmalloc(len, GFP_KERNEL);
+    dmadata = kmalloc(len, GFP_KERNEL);
 
-	if (!dmadata)
+    if (!dmadata)
-		return -ENOMEM;
+        return -ENOMEM;
 
-	/* do control transfer */
+    /* do control transfer */
-	ret = usb_control_msg(dev->usb_dev, usb_rcvctrlpipe(dev->usb_dev, 0),
+    ret = usb_control_msg(dev->usb_dev, usb_rcvctrlpipe(dev->usb_dev, 0),
-			cmd, USB_TYPE_VENDOR | USB_RECIP_INTERFACE | USB_DIR_IN,
+            cmd, USB_TYPE_VENDOR | USB_RECIP_INTERFACE | USB_DIR_IN,
-			value, index, dmadata, len, 2000);
+            value, index, dmadata, len, 2000);
 
-	memcpy(data, dmadata, len);
+    memcpy(data, dmadata, len);
 
-	kfree(dmadata);
+    kfree(dmadata);
-	return ret;
+    return ret;
 }
 
 static int usb_write(struct i2c_adapter *adapter, int cmd,
-		     int value, int index, void *data, int len)
+             int value, int index, void *data, int len)
 {
-	struct i2c_tiny_usb *dev = (struct i2c_tiny_usb *)adapter->algo_data;
+    struct i2c_tiny_usb *dev = (struct i2c_tiny_usb *)adapter->algo_data;
-	uint8_t *dmadata;
+    uint8_t *dmadata;
-	int ret;
+    int ret;
 
-	dmadata = (uint8_t*)kmemdup(data, len, GFP_KERNEL);
+    dmadata = (uint8_t*)kmemdup(data, len, GFP_KERNEL);
-	if (!dmadata)
+    if (!dmadata)
-		return -ENOMEM;
+        return -ENOMEM;
 
-	/* do control transfer */
+    /* do control transfer */
-	ret = usb_control_msg(dev->usb_dev, usb_sndctrlpipe(dev->usb_dev, 0),
+    ret = usb_control_msg(dev->usb_dev, usb_sndctrlpipe(dev->usb_dev, 0),
-			cmd, USB_TYPE_VENDOR | USB_RECIP_INTERFACE,
+            cmd, USB_TYPE_VENDOR | USB_RECIP_INTERFACE,
-			value, index, dmadata, len, 2000);
+            value, index, dmadata, len, 2000);
 
-	kfree(dmadata);
+    kfree(dmadata);
-	return ret;
+    return ret;
 }
 
 static void i2c_tiny_usb_free(struct i2c_tiny_usb *dev)
 {
-	usb_put_dev(dev->usb_dev);
+    usb_put_dev(dev->usb_dev);
-	kfree(dev);
+    kfree(dev);
 }
 
 static int i2c_tiny_usb_probe(struct usb_interface *interface,
-			      const struct usb_device_id *id)
+                  const struct usb_device_id *id)
 {
-	struct i2c_tiny_usb *dev;
+    struct i2c_tiny_usb *dev;
-	int retval = -ENOMEM;
+    int retval = -ENOMEM;
-	u16 version;
+    u16 version;
 
-	dev_dbg(&interface->dev, "probing usb device\n");
+    dev_dbg(&interface->dev, "probing usb device\n");
 
-	/* allocate memory for our device state and initialize it */
+    /* allocate memory for our device state and initialize it */
-	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+    dev = kzalloc(sizeof(*dev), GFP_KERNEL);
-	if (dev == NULL) {
+    if (dev == NULL) {
-		dev_err(&interface->dev, "Out of memory\n");
+        dev_err(&interface->dev, "Out of memory\n");
-		goto error;
+        goto error;
-	}
+    }
 
-	dev->usb_dev = usb_get_dev(interface_to_usbdev(interface));
+    dev->usb_dev = usb_get_dev(interface_to_usbdev(interface));
-	dev->interface = interface;
+    dev->interface = interface;
 
-	/* save our data pointer in this interface device */
+    /* save our data pointer in this interface device */
-	usb_set_intfdata(interface, dev);
+    usb_set_intfdata(interface, dev);
 
-	version = le16_to_cpu(dev->usb_dev->descriptor.bcdDevice);
+    version = le16_to_cpu(dev->usb_dev->descriptor.bcdDevice);
-	dev_info(&interface->dev,
+    dev_info(&interface->dev,
-		 "version %x.%02x found at bus %03d address %03d\n",
+         "version %x.%02x found at bus %03d address %03d\n",
-		 version >> 8, version & 0xff,
+         version >> 8, version & 0xff,
-		 dev->usb_dev->bus->busnum, dev->usb_dev->devnum);
+         dev->usb_dev->bus->busnum, dev->usb_dev->devnum);
 
-	/* setup i2c adapter description */
+    /* setup i2c adapter description */
-	dev->adapter.owner = THIS_MODULE;
+    dev->adapter.owner = THIS_MODULE;
-	dev->adapter.class = I2C_CLASS_HWMON;
+    dev->adapter.class = I2C_CLASS_HWMON;
-	dev->adapter.algo = &usb_algorithm;
+    dev->adapter.algo = &usb_algorithm;
-	dev->adapter.algo_data = dev;
+    dev->adapter.algo_data = dev;
-	snprintf(dev->adapter.name, sizeof(dev->adapter.name),
+    snprintf(dev->adapter.name, sizeof(dev->adapter.name),
-		 "i2c-tiny-usb at bus %03d device %03d",
+         "i2c-tiny-usb at bus %03d device %03d",
-		 dev->usb_dev->bus->busnum, dev->usb_dev->devnum);
+         dev->usb_dev->bus->busnum, dev->usb_dev->devnum);
 
-	if (usb_write(&dev->adapter, CMD_SET_DELAY, delay, 0, NULL, 0) != 0) {
+    if (usb_write(&dev->adapter, CMD_SET_DELAY, delay, 0, NULL, 0) != 0) {
-		dev_err(/*&dev->adapter.dev*/ &dev->usb_dev->dev, /* adapter.dev is null at this point */
+        dev_err(/*&dev->adapter.dev*/ &dev->usb_dev->dev, /* adapter.dev is null at this point */
-			"failure setting delay to %dus\n", delay);
+            "failure setting delay to %dus\n", delay);
-		retval = -EIO;
+        retval = -EIO;
-		goto error;
+        goto error;
-	}
+    }
 
-	dev->adapter.dev.parent = &dev->interface->dev;
+    dev->adapter.dev.parent = &dev->interface->dev;
 
-	/* and finally attach to i2c layer */
+    /* and finally attach to i2c layer */
-	i2c_add_adapter(&dev->adapter);
+    i2c_add_adapter(&dev->adapter);
 
-	/* inform user about successful attachment to i2c layer */
+    /* inform user about successful attachment to i2c layer */
-	dev_info(&dev->adapter.dev, "connected i2c-tiny-usb device\n");
+    dev_info(&dev->adapter.dev, "connected i2c-tiny-usb device\n");
 
-	return 0;
+    return 0;
 
  error:
-	if (dev)
+    if (dev)
-		i2c_tiny_usb_free(dev);
+        i2c_tiny_usb_free(dev);
 
-	return retval;
+    return retval;
 }
 
 static void i2c_tiny_usb_disconnect(struct usb_interface *interface)
 {
-	struct i2c_tiny_usb *dev = usb_get_intfdata(interface);
+    struct i2c_tiny_usb *dev = usb_get_intfdata(interface);
 
-	i2c_del_adapter(&dev->adapter);
+    i2c_del_adapter(&dev->adapter);
-	usb_set_intfdata(interface, NULL);
+    usb_set_intfdata(interface, NULL);
-	i2c_tiny_usb_free(dev);
+    i2c_tiny_usb_free(dev);
 
-	dev_dbg(&interface->dev, "disconnected\n");
+    dev_dbg(&interface->dev, "disconnected\n");
 }
 
 static struct usb_driver i2c_tiny_usb_driver = {
-	.name		= "i2c-tiny-usb",
+    .name		= "i2c-tiny-usb",
-	.probe		= i2c_tiny_usb_probe,
+    .probe		= i2c_tiny_usb_probe,
-	.disconnect	= i2c_tiny_usb_disconnect,
+    .disconnect	= i2c_tiny_usb_disconnect,
-	.id_table	= i2c_tiny_usb_table,
+    .id_table	= i2c_tiny_usb_table,
 };
 
 module_usb_driver(i2c_tiny_usb_driver);

scripts/configure_haskal.sh

@@ -0,0 +1,14 @@
+#!/bin/bash
+
+set -eo pipefail
+
+SCRIPTPATH="$(cd -- "$(dirname "$0")" >/dev/null 2>&1; pwd -P)"
+SRCPATH=$(readlink -e "$SCRIPTPATH/..")
+cd "$SRCPATH"
+[ -d "build" ] || mkdir build
+cd build
+
+set -x
+exec cmake -G Ninja -DBOARD=raspberry_pi_pico -DFAMILY=rp2040 -DCMAKE_BUILD_TYPE=RelWithDebInfo \
+    -DPICO_NO_FLASH=On -DUSE_USBCDC_FOR_STDIO=On -DUSE_SYSTEMWIDE_PICOSDK=On \
+    $SRCPATH

scripts/fix_clang_db.py

@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+
+import json
+import sys
+
+with open("compile_commands.json", "r") as f:
+    data = json.load(f)
+
+include = " -I/usr/arm-none-eabi/include"
+
+for i in range(len(data)):
+    if include not in data[i]["command"]:
+        data[i]["command"] += include
+
+with open("compile_commands.json", "w") as f:
+    json.dump(data, f)

src/cdc_serprog.c

@@ -23,19 +23,19 @@
 // so leaving it here for now
 
 static const uint8_t serprog_cmdmap[32] = {
-	0x3f, // cmd 00..05 not 0x06 (Q_CHIPSIZE) and 0x07 (Q_OPBUF), as this is a SPI-only device
+    0x3f, // cmd 00..05 not 0x06 (Q_CHIPSIZE) and 0x07 (Q_OPBUF), as this is a SPI-only device
-	0x01, // only cmd 08
+    0x01, // only cmd 08
-	0x1f, // cmd 10..15 supported
+    0x1f, // cmd 10..15 supported
-	0, // 18..1f
+    0, // 18..1f
-	0, // 20..27
+    0, // 20..27
-	0, // 28..2f
+    0, // 28..2f
-	0, // 30..37
+    0, // 30..37
-	0, // 38..3f
+    0, // 38..3f
-	0, // 40..47
+    0, // 40..47
-	0, // 48..4f
+    0, // 48..4f
-	(1<<3), // 50..57: enable 0x53
+    (1<<3), // 50..57: enable 0x53
-	0, // 58..5f
+    0, // 58..5f
-	0, // rest is 0
+    0, // rest is 0
 };
 static const char serprog_pgmname[16] = INFO_PRODUCT_BARE;
 
@@ -45,194 +45,194 @@ static uint8_t tx_buf[CFG_TUD_CDC_TX_BUFSIZE];
 static uint32_t rxavail, rxpos;
 
 void cdc_serprog_init(void) {
-	rxavail = 0;
+    rxavail = 0;
-	rxpos = 0;
+    rxpos = 0;
 
-	sp_spi_init();
+    sp_spi_init();
 }
 
 static uint8_t read_byte(void) {
-	while (rxavail <= 0) {
+    while (rxavail <= 0) {
-		if (!tud_cdc_n_connected(CDC_N_SERPROG) || !tud_cdc_n_available(CDC_N_SERPROG)) {
+        if (!tud_cdc_n_connected(CDC_N_SERPROG) || !tud_cdc_n_available(CDC_N_SERPROG)) {
-			thread_yield();
+            thread_yield();
-			continue;
+            continue;
-		}
+        }
 
-		rxpos = 0;
+        rxpos = 0;
-		rxavail = tud_cdc_n_read(CDC_N_SERPROG, rx_buf, sizeof rx_buf);
+        rxavail = tud_cdc_n_read(CDC_N_SERPROG, rx_buf, sizeof rx_buf);
 
-		if (rxavail == 0) thread_yield();
+        if (rxavail == 0) thread_yield();
-	}
+    }
 
-	uint8_t rv = rx_buf[rxpos];
+    uint8_t rv = rx_buf[rxpos];
-	++rxpos;
+    ++rxpos;
-	--rxavail;
+    --rxavail;
-	return rv;
+    return rv;
 }
 
 static void handle_cmd(void) {
 uint32_t nresp = 0;
 
 uint8_t cmd = read_byte();
-	switch (cmd) {
+    switch (cmd) {
-	case S_CMD_NOP:
+    case S_CMD_NOP:
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		nresp = 1;
+        nresp = 1;
-		break;
+        break;
-	case S_CMD_SYNCNOP:
+    case S_CMD_SYNCNOP:
-		tx_buf[0] = S_NAK;
+        tx_buf[0] = S_NAK;
-		tx_buf[1] = S_ACK;
+        tx_buf[1] = S_ACK;
-		nresp = 2;
+        nresp = 2;
-		break;
+        break;
-	case S_CMD_Q_IFACE:
+    case S_CMD_Q_IFACE:
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		tx_buf[1] =  SERPROG_IFACE_VERSION       & 0xff;
+        tx_buf[1] =  SERPROG_IFACE_VERSION       & 0xff;
-		tx_buf[2] = (SERPROG_IFACE_VERSION >> 8) & 0xff;
+        tx_buf[2] = (SERPROG_IFACE_VERSION >> 8) & 0xff;
-		nresp = 3;
+        nresp = 3;
-		break;
+        break;
-	case S_CMD_Q_CMDMAP:
+    case S_CMD_Q_CMDMAP:
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		memcpy(&tx_buf[1], serprog_cmdmap, sizeof serprog_cmdmap);
+        memcpy(&tx_buf[1], serprog_cmdmap, sizeof serprog_cmdmap);
-		nresp = sizeof(serprog_cmdmap) + 1;
+        nresp = sizeof(serprog_cmdmap) + 1;
-		break;
+        break;
-	case S_CMD_Q_PGMNAME:
+    case S_CMD_Q_PGMNAME:
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		memcpy(&tx_buf[1], serprog_pgmname, sizeof serprog_pgmname);
+        memcpy(&tx_buf[1], serprog_pgmname, sizeof serprog_pgmname);
-		nresp = sizeof(serprog_pgmname) + 1;
+        nresp = sizeof(serprog_pgmname) + 1;
-		break;
+        break;
-	case S_CMD_Q_SERBUF:
+    case S_CMD_Q_SERBUF:
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		tx_buf[1] =  sizeof(rx_buf)       & 0xff;
+        tx_buf[1] =  sizeof(rx_buf)       & 0xff;
-		tx_buf[2] = (sizeof(rx_buf) >> 8) & 0xff;
+        tx_buf[2] = (sizeof(rx_buf) >> 8) & 0xff;
-		nresp = 3;
+        nresp = 3;
-		break;
+        break;
-	case S_CMD_Q_BUSTYPE:
+    case S_CMD_Q_BUSTYPE:
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		tx_buf[1] = 1<<3; // SPI only
+        tx_buf[1] = 1<<3; // SPI only
-		nresp = 2;
+        nresp = 2;
-		break;
+        break;
-	case S_CMD_Q_WRNMAXLEN:
+    case S_CMD_Q_WRNMAXLEN:
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		tx_buf[1] =  (sizeof(tx_buf)-1)       & 0xff;
+        tx_buf[1] =  (sizeof(tx_buf)-1)       & 0xff;
-		tx_buf[2] = ((sizeof(tx_buf)-1) >> 8) & 0xff;
+        tx_buf[2] = ((sizeof(tx_buf)-1) >> 8) & 0xff;
-		tx_buf[3] = ((sizeof(tx_buf)-1) >>16) & 0xff;
+        tx_buf[3] = ((sizeof(tx_buf)-1) >>16) & 0xff;
-		nresp = 4;
+        nresp = 4;
-		break;
+        break;
-	case S_CMD_Q_RDNMAXLEN:
+    case S_CMD_Q_RDNMAXLEN:
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		tx_buf[1] =  (sizeof(rx_buf)-1)       & 0xff;
+        tx_buf[1] =  (sizeof(rx_buf)-1)       & 0xff;
-		tx_buf[2] = ((sizeof(rx_buf)-1) >> 8) & 0xff;
+        tx_buf[2] = ((sizeof(rx_buf)-1) >> 8) & 0xff;
-		tx_buf[3] = ((sizeof(rx_buf)-1) >>16) & 0xff;
+        tx_buf[3] = ((sizeof(rx_buf)-1) >>16) & 0xff;
-		nresp = 4;
+        nresp = 4;
-		break;
+        break;
-	case S_CMD_S_BUSTYPE:
+    case S_CMD_S_BUSTYPE:
-		if (read_byte()/* bus type to set */ == (1<<3)) {
+        if (read_byte()/* bus type to set */ == (1<<3)) {
-			tx_buf[0] = S_ACK;
+            tx_buf[0] = S_ACK;
-		} else {
+        } else {
-			tx_buf[0] = S_NAK;
+            tx_buf[0] = S_NAK;
-		}
+        }
-		nresp = 1;
+        nresp = 1;
-		break;
+        break;
 
-	case S_CMD_SPIOP: {
+    case S_CMD_SPIOP: {
-		uint32_t slen, rlen;
+        uint32_t slen, rlen;
-		slen  = (uint32_t)read_byte();
+        slen  = (uint32_t)read_byte();
-		slen |= (uint32_t)read_byte() <<  8;
+        slen |= (uint32_t)read_byte() <<  8;
-		slen |= (uint32_t)read_byte() << 16;
+        slen |= (uint32_t)read_byte() << 16;
-		rlen  = (uint32_t)read_byte();
+        rlen  = (uint32_t)read_byte();
-		rlen |= (uint32_t)read_byte() <<  8;
+        rlen |= (uint32_t)read_byte() <<  8;
-		rlen |= (uint32_t)read_byte() << 16;
+        rlen |= (uint32_t)read_byte() << 16;
 
-		sp_spi_op_begin();
+        sp_spi_op_begin();
-		size_t this_batch;
+        size_t this_batch;
 
-		// 1. write slen data bytes
+        // 1. write slen data bytes
-		// we're going to use the tx buf for all operations here
+        // we're going to use the tx buf for all operations here
-		while (slen > 0) {
+        while (slen > 0) {
-			this_batch = sizeof(tx_buf);
+            this_batch = sizeof(tx_buf);
-			if (this_batch > slen) this_batch = slen;
+            if (this_batch > slen) this_batch = slen;
 
-			for (size_t i = 0; i < this_batch; ++i) tx_buf[i] = read_byte();
+            for (size_t i = 0; i < this_batch; ++i) tx_buf[i] = read_byte();
-			sp_spi_op_write(this_batch, tx_buf);
+            sp_spi_op_write(this_batch, tx_buf);
 
-			slen -= this_batch;
+            slen -= this_batch;
-		}
+        }
 
-		// 2. write data
+        // 2. write data
-		// first, do a batch of 63, because we also need to send an ACK byte
+        // first, do a batch of 63, because we also need to send an ACK byte
-		this_batch = sizeof(tx_buf)-1;
+        this_batch = sizeof(tx_buf)-1;
-		if (this_batch > rlen) this_batch = rlen;
+        if (this_batch > rlen) this_batch = rlen;
-		sp_spi_op_read(this_batch, &tx_buf[1]);
+        sp_spi_op_read(this_batch, &tx_buf[1]);
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		tud_cdc_n_write(CDC_N_SERPROG, tx_buf, this_batch+1);
+        tud_cdc_n_write(CDC_N_SERPROG, tx_buf, this_batch+1);
-		rlen -= this_batch;
+        rlen -= this_batch;
 
-		// now do in batches of 64
+        // now do in batches of 64
-		while (rlen > 0) {
+        while (rlen > 0) {
-			this_batch = sizeof(tx_buf);
+            this_batch = sizeof(tx_buf);
-			if (this_batch > rlen) this_batch = rlen;
+            if (this_batch > rlen) this_batch = rlen;
 
-			sp_spi_op_read(this_batch, tx_buf);
+            sp_spi_op_read(this_batch, tx_buf);
-			tud_cdc_n_write(CDC_N_SERPROG, tx_buf, this_batch);
+            tud_cdc_n_write(CDC_N_SERPROG, tx_buf, this_batch);
 
-			rlen -= this_batch;
+            rlen -= this_batch;
-		}
+        }
-		tud_cdc_n_write_flush(CDC_N_SERPROG);
+        tud_cdc_n_write_flush(CDC_N_SERPROG);
 
-		// that's it!
+        // that's it!
-		sp_spi_op_end();
+        sp_spi_op_end();
-		nresp = 0; // we sent our own response manually
+        nresp = 0; // we sent our own response manually
-		}
+        }
-		break;
+        break;
-	case S_CMD_S_SPI_FREQ: {
+    case S_CMD_S_SPI_FREQ: {
-		uint32_t freq;
+        uint32_t freq;
-		freq  = (uint32_t)read_byte();
+        freq  = (uint32_t)read_byte();
-		freq |= (uint32_t)read_byte() <<  8;
+        freq |= (uint32_t)read_byte() <<  8;
-		freq |= (uint32_t)read_byte() << 16;
+        freq |= (uint32_t)read_byte() << 16;
-		freq |= (uint32_t)read_byte() << 24;
+        freq |= (uint32_t)read_byte() << 24;
 
-		uint32_t nfreq = sp_spi_set_freq(freq);
+        uint32_t nfreq = sp_spi_set_freq(freq);
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		tx_buf[1] =  nfreq        & 0xff;
+        tx_buf[1] =  nfreq        & 0xff;
-		tx_buf[2] = (nfreq >>  8) & 0xff;
+        tx_buf[2] = (nfreq >>  8) & 0xff;
-		tx_buf[3] = (nfreq >> 16) & 0xff;
+        tx_buf[3] = (nfreq >> 16) & 0xff;
-		tx_buf[4] = (nfreq >> 24) & 0xff;
+        tx_buf[4] = (nfreq >> 24) & 0xff;
-		nresp = 5;
+        nresp = 5;
-		}
+        }
-		break;
+        break;
-	case S_CMD_S_PINSTATE: {
+    case S_CMD_S_PINSTATE: {
-		if (read_byte() == 0) sp_spi_cs_deselect();
+        if (read_byte() == 0) sp_spi_cs_deselect();
-		else sp_spi_cs_select();
+        else sp_spi_cs_select();
 
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		nresp = 1;
+        nresp = 1;
-		}
+        }
-		break;
+        break;
 
-	case S_CMD_MAGIC_SETTINGS: {
+    case S_CMD_MAGIC_SETTINGS: {
-		uint8_t a = read_byte();
+        uint8_t a = read_byte();
-		uint8_t b = read_byte();
+        uint8_t b = read_byte();
 
-		tx_buf[0] = S_ACK;
+        tx_buf[0] = S_ACK;
-		tx_buf[1] = rtconf_do(a, b);
+        tx_buf[1] = rtconf_do(a, b);
-		nresp = 2;
+        nresp = 2;
-		}
+        }
-		break;
+        break;
 
-	default:
+    default:
-		tx_buf[0] = S_NAK;
+        tx_buf[0] = S_NAK;
-		nresp = 1;
+        nresp = 1;
-		break;
+        break;
-	}
+    }
 
-	if (nresp > 0) {
+    if (nresp > 0) {
-		tud_cdc_n_write(CDC_N_SERPROG, tx_buf, nresp);
+        tud_cdc_n_write(CDC_N_SERPROG, tx_buf, nresp);
-		tud_cdc_n_write_flush(CDC_N_SERPROG);
+        tud_cdc_n_write_flush(CDC_N_SERPROG);
-	}
+    }
 }
 
 void cdc_serprog_task(void) {
-	handle_cmd();
+    handle_cmd();
 }
 
 #endif /* DBOARD_HAS_SERPROG */

src/i2ctinyusb.h

@@ -9,87 +9,87 @@
 #include "protocfg.h"
 
 enum itu_command {
-	ITU_CMD_ECHO       = 0,
+    ITU_CMD_ECHO       = 0,
-	ITU_CMD_GET_FUNC   = 1,
+    ITU_CMD_GET_FUNC   = 1,
-	ITU_CMD_SET_DELAY  = 2,
+    ITU_CMD_SET_DELAY  = 2,
-	ITU_CMD_GET_STATUS = 3,
+    ITU_CMD_GET_STATUS = 3,
 
-	ITU_CMD_I2C_IO_BEGIN_F = (1<<0),
+    ITU_CMD_I2C_IO_BEGIN_F = (1<<0),
-	ITU_CMD_I2C_IO_END_F   = (1<<1),
+    ITU_CMD_I2C_IO_END_F   = (1<<1),
-	ITU_CMD_I2C_IO_DIR_MASK = ITU_CMD_I2C_IO_BEGIN_F | ITU_CMD_I2C_IO_END_F,
+    ITU_CMD_I2C_IO_DIR_MASK = ITU_CMD_I2C_IO_BEGIN_F | ITU_CMD_I2C_IO_END_F,
 
-	ITU_CMD_I2C_IO          = 4,
+    ITU_CMD_I2C_IO          = 4,
-	ITU_CMD_I2C_IO_BEGIN    = 4 | ITU_CMD_I2C_IO_BEGIN_F,
+    ITU_CMD_I2C_IO_BEGIN    = 4 | ITU_CMD_I2C_IO_BEGIN_F,
-	ITU_CMD_I2C_IO_END      = 4 | ITU_CMD_I2C_IO_END_F  ,
+    ITU_CMD_I2C_IO_END      = 4 | ITU_CMD_I2C_IO_END_F  ,
-	ITU_CMD_I2C_IO_BEGINEND = 4 | ITU_CMD_I2C_IO_BEGIN_F | ITU_CMD_I2C_IO_END_F,
+    ITU_CMD_I2C_IO_BEGINEND = 4 | ITU_CMD_I2C_IO_BEGIN_F | ITU_CMD_I2C_IO_END_F,
 };
 
 enum itu_status {
-	ITU_STATUS_IDLE     = 0,
+    ITU_STATUS_IDLE     = 0,
-	ITU_STATUS_ADDR_ACK = 1,
+    ITU_STATUS_ADDR_ACK = 1,
-	ITU_STATUS_ADDR_NAK = 2
+    ITU_STATUS_ADDR_NAK = 2
 };
 
 // these two are lifted straight from the linux kernel, lmao
 enum ki2c_flags {
-	I2C_M_RD           = 0x0001, /* guaranteed to be 0x0001! */
+    I2C_M_RD           = 0x0001, /* guaranteed to be 0x0001! */
-	I2C_M_TEN          = 0x0010, /* use only if I2C_FUNC_10BIT_ADDR */
+    I2C_M_TEN          = 0x0010, /* use only if I2C_FUNC_10BIT_ADDR */
-	I2C_M_DMA_SAFE     = 0x0200, /* use only in kernel space */
+    I2C_M_DMA_SAFE     = 0x0200, /* use only in kernel space */
-	I2C_M_RECV_LEN     = 0x0400, /* use only if I2C_FUNC_SMBUS_READ_BLOCK_DATA */
+    I2C_M_RECV_LEN     = 0x0400, /* use only if I2C_FUNC_SMBUS_READ_BLOCK_DATA */
-	I2C_M_NO_RD_ACK    = 0x0800, /* use only if I2C_FUNC_PROTOCOL_MANGLING */
+    I2C_M_NO_RD_ACK    = 0x0800, /* use only if I2C_FUNC_PROTOCOL_MANGLING */
-	I2C_M_IGNORE_NAK   = 0x1000, /* use only if I2C_FUNC_PROTOCOL_MANGLING */
+    I2C_M_IGNORE_NAK   = 0x1000, /* use only if I2C_FUNC_PROTOCOL_MANGLING */
-	I2C_M_REV_DIR_ADDR = 0x2000, /* use only if I2C_FUNC_PROTOCOL_MANGLING */
+    I2C_M_REV_DIR_ADDR = 0x2000, /* use only if I2C_FUNC_PROTOCOL_MANGLING */
-	I2C_M_NOSTART      = 0x4000, /* use only if I2C_FUNC_NOSTART */
+    I2C_M_NOSTART      = 0x4000, /* use only if I2C_FUNC_NOSTART */
-	I2C_M_STOP         = 0x8000, /* use only if I2C_FUNC_PROTOCOL_MANGLING */
+    I2C_M_STOP         = 0x8000, /* use only if I2C_FUNC_PROTOCOL_MANGLING */
 };
 
 enum ki2c_funcs {
-	I2C_FUNC_I2C                        = 0x00000001,
+    I2C_FUNC_I2C                        = 0x00000001,
-	I2C_FUNC_10BIT_ADDR                 = 0x00000002, /* required for I2C_M_TEN */
+    I2C_FUNC_10BIT_ADDR                 = 0x00000002, /* required for I2C_M_TEN */
-	I2C_FUNC_PROTOCOL_MANGLING          = 0x00000004, /* required for I2C_M_IGNORE_NAK etc. */
+    I2C_FUNC_PROTOCOL_MANGLING          = 0x00000004, /* required for I2C_M_IGNORE_NAK etc. */
-	I2C_FUNC_SMBUS_PEC                  = 0x00000008,
+    I2C_FUNC_SMBUS_PEC                  = 0x00000008,
-	I2C_FUNC_NOSTART                    = 0x00000010, /* required for I2C_M_NOSTART */
+    I2C_FUNC_NOSTART                    = 0x00000010, /* required for I2C_M_NOSTART */
-	I2C_FUNC_SLAVE                      = 0x00000020,
+    I2C_FUNC_SLAVE                      = 0x00000020,
-	I2C_FUNC_SMBUS_BLOCK_PROC_CALL      = 0x00008000, /* SMBus 2.0 or later */
+    I2C_FUNC_SMBUS_BLOCK_PROC_CALL      = 0x00008000, /* SMBus 2.0 or later */
-	I2C_FUNC_SMBUS_QUICK                = 0x00010000,
+    I2C_FUNC_SMBUS_QUICK                = 0x00010000,
-	I2C_FUNC_SMBUS_READ_BYTE            = 0x00020000,
+    I2C_FUNC_SMBUS_READ_BYTE            = 0x00020000,
-	I2C_FUNC_SMBUS_WRITE_BYTE           = 0x00040000,
+    I2C_FUNC_SMBUS_WRITE_BYTE           = 0x00040000,
-	I2C_FUNC_SMBUS_READ_BYTE_DATA       = 0x00080000,
+    I2C_FUNC_SMBUS_READ_BYTE_DATA       = 0x00080000,
-	I2C_FUNC_SMBUS_WRITE_BYTE_DATA      = 0x00100000,
+    I2C_FUNC_SMBUS_WRITE_BYTE_DATA      = 0x00100000,
-	I2C_FUNC_SMBUS_READ_WORD_DATA       = 0x00200000,
+    I2C_FUNC_SMBUS_READ_WORD_DATA       = 0x00200000,
-	I2C_FUNC_SMBUS_WRITE_WORD_DATA      = 0x00400000,
+    I2C_FUNC_SMBUS_WRITE_WORD_DATA      = 0x00400000,
-	I2C_FUNC_SMBUS_PROC_CALL            = 0x00800000,
+    I2C_FUNC_SMBUS_PROC_CALL            = 0x00800000,
-	I2C_FUNC_SMBUS_READ_BLOCK_DATA      = 0x01000000, /* required for I2C_M_RECV_LEN */
+    I2C_FUNC_SMBUS_READ_BLOCK_DATA      = 0x01000000, /* required for I2C_M_RECV_LEN */
-	I2C_FUNC_SMBUS_WRITE_BLOCK_DATA     = 0x02000000,
+    I2C_FUNC_SMBUS_WRITE_BLOCK_DATA     = 0x02000000,
-	I2C_FUNC_SMBUS_READ_I2C_BLOCK       = 0x04000000, /* I2C-like block xfer  */
+    I2C_FUNC_SMBUS_READ_I2C_BLOCK       = 0x04000000, /* I2C-like block xfer  */
-	I2C_FUNC_SMBUS_WRITE_I2C_BLOCK      = 0x08000000, /* w/ 1-byte reg. addr. */
+    I2C_FUNC_SMBUS_WRITE_I2C_BLOCK      = 0x08000000, /* w/ 1-byte reg. addr. */
-	I2C_FUNC_SMBUS_READ_I2C_BLOCK_2     = 0x10000000, /* I2C-like block xfer */
+    I2C_FUNC_SMBUS_READ_I2C_BLOCK_2     = 0x10000000, /* I2C-like block xfer */
-	I2C_FUNC_SMBUS_WRITE_I2C_BLOCK_2    = 0x20000000, /* w/ 2-byte reg. addr. */
+    I2C_FUNC_SMBUS_WRITE_I2C_BLOCK_2    = 0x20000000, /* w/ 2-byte reg. addr. */
-	I2C_FUNC_SMBUS_READ_BLOCK_DATA_PEC  = 0x40000000, /* SMBus 2.0 or later */
+    I2C_FUNC_SMBUS_READ_BLOCK_DATA_PEC  = 0x40000000, /* SMBus 2.0 or later */
-	I2C_FUNC_SMBUS_WRITE_BLOCK_DATA_PEC = 0x80000000, /* SMBus 2.0 or later */
+    I2C_FUNC_SMBUS_WRITE_BLOCK_DATA_PEC = 0x80000000, /* SMBus 2.0 or later */
 
-	I2C_FUNC_SMBUS_BYTE       = (I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE),
+    I2C_FUNC_SMBUS_BYTE       = (I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE),
-	I2C_FUNC_SMBUS_BYTE_DATA  = (I2C_FUNC_SMBUS_READ_BYTE_DATA | I2C_FUNC_SMBUS_WRITE_BYTE_DATA),
+    I2C_FUNC_SMBUS_BYTE_DATA  = (I2C_FUNC_SMBUS_READ_BYTE_DATA | I2C_FUNC_SMBUS_WRITE_BYTE_DATA),
-	I2C_FUNC_SMBUS_WORD_DATA  = (I2C_FUNC_SMBUS_READ_WORD_DATA | I2C_FUNC_SMBUS_WRITE_WORD_DATA),
+    I2C_FUNC_SMBUS_WORD_DATA  = (I2C_FUNC_SMBUS_READ_WORD_DATA | I2C_FUNC_SMBUS_WRITE_WORD_DATA),
-	I2C_FUNC_SMBUS_BLOCK_DATA = (I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_BLOCK_DATA),
+    I2C_FUNC_SMBUS_BLOCK_DATA = (I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_BLOCK_DATA),
-	I2C_FUNC_SMBUS_I2C_BLOCK  = (I2C_FUNC_SMBUS_READ_I2C_BLOCK | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK),
+    I2C_FUNC_SMBUS_I2C_BLOCK  = (I2C_FUNC_SMBUS_READ_I2C_BLOCK | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK),
 
-	I2C_FUNC_SMBUS_EMUL =  (I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | \
+    I2C_FUNC_SMBUS_EMUL =  (I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | \
-						I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | \
+                        I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | \
-						I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \
+                        I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \
-						I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_PEC),
+                        I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_PEC),
 
-	/* if I2C_M_RECV_LEN is also supported */
+    /* if I2C_M_RECV_LEN is also supported */
-	I2C_FUNC_SMBUS_EMUL_ALL = (I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_READ_BLOCK_DATA | \
+    I2C_FUNC_SMBUS_EMUL_ALL = (I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_READ_BLOCK_DATA | \
-					 I2C_FUNC_SMBUS_BLOCK_PROC_CALL),
+                     I2C_FUNC_SMBUS_BLOCK_PROC_CALL),
 };
 
 __attribute__((__packed__))
 struct itu_cmd {
-	uint16_t flags;
+    uint16_t flags;
-	uint16_t addr;
+    uint16_t addr;
-	uint16_t len;
+    uint16_t len;
-	uint8_t cmd;
+    uint8_t cmd;
 };
 
 #ifdef DBOARD_HAS_I2C
@@ -98,9 +98,9 @@ enum ki2c_funcs i2ctu_get_func(void);
 void i2ctu_init(void);
 uint32_t i2ctu_set_freq(uint32_t freq, uint32_t us); // returns selected frequency, or 0 on error
 enum itu_status i2ctu_write(enum ki2c_flags flags, enum itu_command startstopflags,
-		uint16_t addr, const uint8_t* buf, size_t len);
+        uint16_t addr, const uint8_t* buf, size_t len);
 enum itu_status i2ctu_read(enum ki2c_flags flags, enum itu_command startstopflags,
-		uint16_t addr, uint8_t* buf, size_t len);
+        uint16_t addr, uint8_t* buf, size_t len);
 #endif
 
 #endif

src/main.c

@@ -49,7 +49,7 @@
 static cothread_t mainthread;
 
 void thread_yield(void) {
-	co_switch(mainthread);
+    co_switch(mainthread);
 }
 
 #define DEFAULT_STACK_SIZE 1024
@@ -59,12 +59,12 @@ static cothread_t uartthread;
 static uint8_t uartstack[DEFAULT_STACK_SIZE];
 
 static void uart_thread_fn(void) {
-	cdc_uart_init();
+    cdc_uart_init();
-	thread_yield();
+    thread_yield();
-	while (1) {
+    while (1) {
-		cdc_uart_task();
+        cdc_uart_task();
-		thread_yield();
+        thread_yield();
-	}
+    }
 }
 #endif
 
@@ -89,59 +89,59 @@ extern cothread_t co_active_handle;
 cothread_t co_active_handle;
 
 int main(void) {
-	mainthread = co_active();
+    mainthread = co_active();
 
-	// TODO: split this out in a bsp-specific file
+    // TODO: split this out in a bsp-specific file
 #if defined(PICO_BOARD) && !defined(USE_USBCDC_FOR_STDIO)
-	// use hardcoded values from TinyUSB board.h
+    // use hardcoded values from TinyUSB board.h
-	bi_decl(bi_2pins_with_func(0, 1, GPIO_FUNC_UART));
+    bi_decl(bi_2pins_with_func(0, 1, GPIO_FUNC_UART));
-	/*i2c_init(PINOUT_I2C_DEV, 100*1000);
+    /*i2c_init(PINOUT_I2C_DEV, 100*1000);
 
-	gpio_set_function(PINOUT_I2C_SCL, GPIO_FUNC_I2C);
+    gpio_set_function(PINOUT_I2C_SCL, GPIO_FUNC_I2C);
-	gpio_set_function(PINOUT_I2C_SDA, GPIO_FUNC_I2C);
+    gpio_set_function(PINOUT_I2C_SDA, GPIO_FUNC_I2C);
-	gpio_pull_up(PINOUT_I2C_SCL);
+    gpio_pull_up(PINOUT_I2C_SCL);
-	gpio_pull_up(PINOUT_I2C_SDA);
+    gpio_pull_up(PINOUT_I2C_SDA);
 
-	bi_decl(bi_2pins_with_func(PINOUT_I2C_SCL, PINOUT_I2C_SDA, GPIO_FUNC_I2C));*/
+    bi_decl(bi_2pins_with_func(PINOUT_I2C_SCL, PINOUT_I2C_SDA, GPIO_FUNC_I2C));*/
 #endif
-	board_init();
+    board_init();
 
 #ifdef DBOARD_HAS_UART
-	uartthread = co_derive(uartstack, sizeof uartstack, uart_thread_fn);
+    uartthread = co_derive(uartstack, sizeof uartstack, uart_thread_fn);
-	co_switch(uartthread); // will call cdc_uart_init() on correct thread
+    co_switch(uartthread); // will call cdc_uart_init() on correct thread
 #endif
 #ifdef DBOARD_HAS_SERPROG
-	serprogthread = co_derive(serprogstack, sizeof serprogstack, serprog_thread_fn);
+    serprogthread = co_derive(serprogstack, sizeof serprogstack, serprog_thread_fn);
-	co_switch(serprogthread); // will call cdc_serprog_init() on correct thread
+    co_switch(serprogthread); // will call cdc_serprog_init() on correct thread
 #endif
 #ifdef DBOARD_HAS_CMSISDAP
-	DAP_Setup();
+    DAP_Setup();
 #endif
 
-	tusb_init();
+    tusb_init();
 
 #ifdef USE_USBCDC_FOR_STDIO
-	stdio_usb_init();
+    stdio_usb_init();
 #endif
 
-	while (1) {
+    while (1) {
-		/*uint8_t val = 0x12;
+        /*uint8_t val = 0x12;
-		i2c_write_timeout_us(PINOUT_I2C_DEV, 0x13, &val, 1, false, 1000*1000);*/
+        i2c_write_timeout_us(PINOUT_I2C_DEV, 0x13, &val, 1, false, 1000*1000);*/
 
-		tud_task(); // tinyusb device task
+        tud_task(); // tinyusb device task
 #ifdef DBOARD_HAS_UART
-		co_switch(uartthread);
+        co_switch(uartthread);
 #endif
 
-		//i2c_write_timeout_us(PINOUT_I2C_DEV, 0x13, &val, 1, false, 1000*1000);
+        //i2c_write_timeout_us(PINOUT_I2C_DEV, 0x13, &val, 1, false, 1000*1000);
 
-		tud_task(); // tinyusb device task
+        tud_task(); // tinyusb device task
 #ifdef DBOARD_HAS_SERPROG
-		co_switch(serprogthread);
+        co_switch(serprogthread);
 #endif
-	}
+    }
 
-	return 0;
+    return 0;
 }
 
 //--------------------------------------------------------------------+
@@ -152,31 +152,31 @@ int main(void) {
 // Application must fill buffer report's content and return its length.
 // Return zero will cause the stack to STALL request
 uint16_t tud_hid_get_report_cb(uint8_t instance, uint8_t report_id,
-		hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen) {
+        hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen) {
-	// TODO not Implemented
+    // TODO not Implemented
-	(void) instance;
+    (void) instance;
-	(void) report_id;
+    (void) report_id;
-	(void) report_type;
+    (void) report_type;
-	(void) buffer;
+    (void) buffer;
-	(void) reqlen;
+    (void) reqlen;
 
-	return 0;
+    return 0;
 }
 
 void tud_hid_set_report_cb(uint8_t instance, uint8_t report_id,
-		hid_report_type_t report_type, uint8_t const* RxDataBuffer, uint16_t bufsize) {
+        hid_report_type_t report_type, uint8_t const* RxDataBuffer, uint16_t bufsize) {
-	static uint8_t TxDataBuffer[CFG_TUD_HID_EP_BUFSIZE];
+    static uint8_t TxDataBuffer[CFG_TUD_HID_EP_BUFSIZE];
-	uint32_t response_size = TU_MIN(CFG_TUD_HID_EP_BUFSIZE, bufsize);
+    uint32_t response_size = TU_MIN(CFG_TUD_HID_EP_BUFSIZE, bufsize);
 
-	// This doesn't use multiple report and report ID
+    // This doesn't use multiple report and report ID
-	(void) instance;
+    (void) instance;
-	(void) report_id;
+    (void) report_id;
-	(void) report_type;
+    (void) report_type;
 
 #ifdef DBOARD_HAS_CMSISDAP
-	DAP_ProcessCommand(RxDataBuffer, TxDataBuffer);
+    DAP_ProcessCommand(RxDataBuffer, TxDataBuffer);
 #endif
 
-	tud_hid_report(0, TxDataBuffer, response_size);
+    tud_hid_report(0, TxDataBuffer, response_size);
 }
 

src/rtconf.c

@@ -8,52 +8,52 @@
 #include "tempsensor.h"
 
 enum {
-	implmap_val = 0
+    implmap_val = 0
 #ifdef DBOARD_HAS_CMSISDAP
-		| 1
+        | 1
 #endif
 #ifdef DBOARD_HAS_UART
-		| 2
+        | 2
 #endif
-	// always true
+    // always true
 /*#ifdef DBOARD_HAS_SERPROG
-		| 4
+        | 4
 #endif*/
 #ifdef DBOARD_HAS_I2C
-		| 4
+        | 4
 #endif
 #ifdef DBOARD_HAS_TEMPSENSOR
-		| 8
+        | 8
 #endif
 
 #ifdef USE_USBCDC_FOR_STDIO
-		| 128
+        | 128
 #endif
 };
 
 uint8_t rtconf_do(uint8_t a, uint8_t b) {
-	switch ((enum rtconf_opt)a) {
+    switch ((enum rtconf_opt)a) {
 #ifdef DBOARD_HAS_UART
-	case opt_uart_hwfc_endis:
+    case opt_uart_hwfc_endis:
-		cdc_uart_set_hwflow(b != 0);
+        cdc_uart_set_hwflow(b != 0);
-		return 0;
+        return 0;
 #endif
 #ifdef DBOARD_HAS_TEMPSENSOR
-	case opt_tempsense_enaddr: {
+    case opt_tempsense_enaddr: {
-		bool act = tempsense_get_active();
+        bool act = tempsense_get_active();
-		uint8_t addr = tempsense_get_addr();
+        uint8_t addr = tempsense_get_addr();
-		printf("act=%c addr=%02x arg=%02x\n", act?'t':'f', addr, b);
+        printf("act=%c addr=%02x arg=%02x\n", act?'t':'f', addr, b);
-		uint8_t rv = tempsense_get_active() ? tempsense_get_addr() : 0xff;
+        uint8_t rv = tempsense_get_active() ? tempsense_get_addr() : 0xff;
-		if (b == 0x00) return rv;
+        if (b == 0x00) return rv;
-		else if (b == 0xff) tempsense_set_active(false);
+        else if (b == 0xff) tempsense_set_active(false);
-		else tempsense_set_addr(b);
+        else tempsense_set_addr(b);
-		return rv;
+        return rv;
-		}
+        }
 #endif
-	case opt_get_implmap:
+    case opt_get_implmap:
-		return implmap_val;
+        return implmap_val;
-	default:
+    default:
-		return 0xff;
+        return 0xff;
-	}
+    }
 }
 

src/rtconf.h

@@ -8,19 +8,19 @@
 
 enum rtconf_opt {
 #ifdef DBOARD_HAS_UART
-	// enable_disable UART flow control
+    // enable_disable UART flow control
-	// b: 0 -> disable, nonzero -> enable
+    // b: 0 -> disable, nonzero -> enable
-	// return: 0
+    // return: 0
-	opt_uart_hwfc_endis = 1,
+    opt_uart_hwfc_endis = 1,
 #endif
 #ifdef DBOARD_HAS_TEMPSENSOR
-	// 0x00: get I2C address or enable/disable status
+    // 0x00: get I2C address or enable/disable status
-	// 0xff: disable
+    // 0xff: disable
-	//other: set I2C address
+    //other: set I2C address
-	opt_tempsense_enaddr = 2,
+    opt_tempsense_enaddr = 2,
 #endif
 
-	opt_get_implmap = 0xff
+    opt_get_implmap = 0xff
 };
 
 uint8_t rtconf_do(uint8_t a, uint8_t b);

src/serprog.h

@@ -3,35 +3,35 @@
 #define SERPROG_H_
 
 enum serprog_cmd {
-	S_CMD_NOP         = 0x00,
+    S_CMD_NOP         = 0x00,
-	S_CMD_Q_IFACE     = 0x01,
+    S_CMD_Q_IFACE     = 0x01,
-	S_CMD_Q_CMDMAP    = 0x02,
+    S_CMD_Q_CMDMAP    = 0x02,
-	S_CMD_Q_PGMNAME   = 0x03,
+    S_CMD_Q_PGMNAME   = 0x03,
-	S_CMD_Q_SERBUF    = 0x04,
+    S_CMD_Q_SERBUF    = 0x04,
-	S_CMD_Q_BUSTYPE   = 0x05,
+    S_CMD_Q_BUSTYPE   = 0x05,
-	S_CMD_Q_CHIPSIZE  = 0x06,
+    S_CMD_Q_CHIPSIZE  = 0x06,
-	S_CMD_Q_OPBUF     = 0x07,
+    S_CMD_Q_OPBUF     = 0x07,
-	S_CMD_Q_WRNMAXLEN = 0x08,
+    S_CMD_Q_WRNMAXLEN = 0x08,
-	S_CMD_R_BYTE      = 0x09,
+    S_CMD_R_BYTE      = 0x09,
-	S_CMD_R_NBYTES    = 0x0a,
+    S_CMD_R_NBYTES    = 0x0a,
-	S_CMD_O_INIT      = 0x0b,
+    S_CMD_O_INIT      = 0x0b,
-	S_CMD_O_WRITEB    = 0x0c,
+    S_CMD_O_WRITEB    = 0x0c,
-	S_CMD_O_WRITEN    = 0x0d,
+    S_CMD_O_WRITEN    = 0x0d,
-	S_CMD_O_DELAY     = 0x0e,
+    S_CMD_O_DELAY     = 0x0e,
-	S_CMD_O_EXEC      = 0x0f,
+    S_CMD_O_EXEC      = 0x0f,
-	S_CMD_SYNCNOP     = 0x10,
+    S_CMD_SYNCNOP     = 0x10,
-	S_CMD_Q_RDNMAXLEN = 0x11,
+    S_CMD_Q_RDNMAXLEN = 0x11,
-	S_CMD_S_BUSTYPE   = 0x12,
+    S_CMD_S_BUSTYPE   = 0x12,
-	S_CMD_SPIOP       = 0x13,
+    S_CMD_SPIOP       = 0x13,
-	S_CMD_S_SPI_FREQ  = 0x14,
+    S_CMD_S_SPI_FREQ  = 0x14,
-	S_CMD_S_PINSTATE  = 0x15,
+    S_CMD_S_PINSTATE  = 0x15,
 
-	S_CMD_MAGIC_SETTINGS = 0x53
+    S_CMD_MAGIC_SETTINGS = 0x53
 };
 
 enum serprog_response {
-	S_ACK = 0x06,
+    S_ACK = 0x06,
-	S_NAK = 0x15
+    S_NAK = 0x15
 };
 
 #define SERPROG_IFACE_VERSION 0x0001
@@ -46,11 +46,11 @@ void sp_spi_op_read(uint32_t read_len, uint8_t* read_data);
 void sp_spi_op_end(void);
 
 static inline void sp_spi_op_do(uint32_t write_len, const uint8_t* write_data,
-		uint32_t read_len, uint8_t* read_data) {
+        uint32_t read_len, uint8_t* read_data) {
-	sp_spi_op_begin();
+    sp_spi_op_begin();
-	sp_spi_op_write(write_len, write_data);
+    sp_spi_op_write(write_len, write_data);
-	sp_spi_op_write(read_len, read_data);
+    sp_spi_op_write(read_len, read_data);
-	sp_spi_op_end();
+    sp_spi_op_end();
 }
 
 #endif

src/t/tstest.c

@@ -14,54 +14,54 @@ static inline int16_t tempsense_dev_get_crit (void) { return 80 << 4; }
 #include "../tempsensor.c"
 
 static int do_pkt(uint8_t cmd, bool read, uint16_t addr, uint16_t len, uint8_t* buf) {
-	int rv;
+    int rv;
 
-	if (cmd & 1) tempsense_do_start();
+    if (cmd & 1) tempsense_do_start();
 
-	if (read) {
+    if (read) {
-		rv = tempsense_do_read(len, buf);
+        rv = tempsense_do_read(len, buf);
-	} else {
+    } else {
-		rv = tempsense_do_write(len, buf);
+        rv = tempsense_do_write(len, buf);
-	}
+    }
 
-	if (cmd & 2) tempsense_do_stop();
+    if (cmd & 2) tempsense_do_stop();
 
-	printf("-> %d: %s\n", rv, (rv < 0 || rv != len) ? "nak" : "ack");
+    printf("-> %d: %s\n", rv, (rv < 0 || rv != len) ? "nak" : "ack");
 
-	return rv;
+    return rv;
 }
 
 static void pbuf(size_t len, const uint8_t* buf) {
-	printf("--> ");
+    printf("--> ");
-	size_t i;
+    size_t i;
-	for (i = 0; i < len; ++i) {
+    for (i = 0; i < len; ++i) {
-		printf("%02x ", buf[i]);
+        printf("%02x ", buf[i]);
-		if ((i & 0xf) == 0xf) printf("%c", '\n');
+        if ((i & 0xf) == 0xf) printf("%c", '\n');
-	}
+    }
-	if ((i & 0xf) != 0x0) printf("%c", '\n');
+    if ((i & 0xf) != 0x0) printf("%c", '\n');
 }
 
 int main(int argc, char* argv[]) {
-	tempsense_init();
+    tempsense_init();
 
-	tempsense_set_addr(0x18);
+    tempsense_set_addr(0x18);
 
-	// initial probe
+    // initial probe
-	uint8_t pk1[1] = {0}; do_pkt(0x05, false, 0x18, 1, pk1);
+    uint8_t pk1[1] = {0}; do_pkt(0x05, false, 0x18, 1, pk1);
-	uint8_t pk2[2];       do_pkt(0x06, true , 0x18, 2, pk2); pbuf(2, pk2);
+    uint8_t pk2[2];       do_pkt(0x06, true , 0x18, 2, pk2); pbuf(2, pk2);
 
-	uint8_t pk3[1] = {1}; do_pkt(0x05, false, 0x18, 1, pk3);
+    uint8_t pk3[1] = {1}; do_pkt(0x05, false, 0x18, 1, pk3);
-	uint8_t pk4[2];       do_pkt(0x06, true , 0x18, 2, pk4); pbuf(2, pk4);
+    uint8_t pk4[2];       do_pkt(0x06, true , 0x18, 2, pk4); pbuf(2, pk4);
 
-	// sensor data get
+    // sensor data get
 
-	// out 0x05 cmd5
+    // out 0x05 cmd5
-	// in 2byte cmd6
+    // in 2byte cmd6
-	// out 0x04 cmd5
+    // out 0x04 cmd5
-	// in 2byte cmd6
+    // in 2byte cmd6
-	// out 0x03 cmd5
+    // out 0x03 cmd5
-	// in 2byte cmd6
+    // in 2byte cmd6
-	// out 0x02 cmd5
+    // out 0x02 cmd5
-	// in 2byte cmd6
+    // in 2byte cmd6
 }
 

src/tempsensor.c

@@ -20,204 +20,204 @@ static size_t index;
 static bool instartstop, hasreg;
 
 enum regid {
-	cap = 0,
+    cap = 0,
-	config,
+    config,
-	t_upper,
+    t_upper,
-	t_lower,
+    t_lower,
-	t_crit,
+    t_crit,
-	t_a,
+    t_a,
-	manuf_id,
+    manuf_id,
-	dev_idrev,
+    dev_idrev,
-	reso
+    reso
 };
 
 #define MANUF_ID  0x0054
 #define DEV_IDREV 0x0400
 
 struct {
-	uint16_t config;
+    uint16_t config;
-	uint16_t t_upper, t_lower, t_crit;
+    uint16_t t_upper, t_lower, t_crit;
-	uint8_t reso;
+    uint8_t reso;
 } mcp9808;
 
 #define float2fix(x) (int)((x)*(1<<4))
 __attribute__((__const__))
 inline static int16_t trunc_8fix4(int fix) {
-	if (fix >  4095) fix =  4095;
+    if (fix >  4095) fix =  4095;
-	if (fix < -4096) fix = -4096;
+    if (fix < -4096) fix = -4096;
-	return fix;
+    return fix;
 }
 void tempsense_init(void) {
-	active = false;
+    active = false;
-	addr = 0xff;
+    addr = 0xff;
-	reg = 0;
+    reg = 0;
-	index = 0;
+    index = 0;
-	instartstop = false;
+    instartstop = false;
-	hasreg = false;
+    hasreg = false;
 
-	tempsense_dev_init();
+    tempsense_dev_init();
 
-	mcp9808.t_lower = tempsense_dev_get_lower();
+    mcp9808.t_lower = tempsense_dev_get_lower();
-	mcp9808.t_upper = tempsense_dev_get_upper();
+    mcp9808.t_upper = tempsense_dev_get_upper();
-	mcp9808.t_crit  = tempsense_dev_get_crit ();
+    mcp9808.t_crit  = tempsense_dev_get_crit ();
 }
 
 bool tempsense_get_active(void) { return active; }
 void tempsense_set_active(bool act) { active = act; if (!act) addr = 0xff; }
 uint8_t tempsense_get_addr(void) { return addr; }
 void tempsense_set_addr(uint8_t a) {
-	addr = a;
+    addr = a;
-	active = addr >= 0x8 && addr <= 0x77;
+    active = addr >= 0x8 && addr <= 0x77;
-	printf("set: ad=%02x ac=%c\n", addr, active?'t':'f');
+    printf("set: ad=%02x ac=%c\n", addr, active?'t':'f');
 }
 
 void tempsense_do_start(void) {
-	printf("ts start\n");
+    printf("ts start\n");
-	//reg = 0;
+    //reg = 0;
-	index = 0;
+    index = 0;
-	instartstop = true;
+    instartstop = true;
-	hasreg = false;
+    hasreg = false;
 }
 void tempsense_do_stop(void) {
-	printf("ts stop\n");
+    printf("ts stop\n");
-	instartstop = false;
+    instartstop = false;
 }
 
 int tempsense_do_read(int length, uint8_t* buf) {
-	printf("read l=%d reg=%02x ", length, reg);
+    printf("read l=%d reg=%02x ", length, reg);
 
-	if (!instartstop || length < 0) return -1; // nak
+    if (!instartstop || length < 0) return -1; // nak
-	if (length == 0) return 0; // ack
+    if (length == 0) return 0; // ack
-	//if (!hasreg) return -1; // nak
+    //if (!hasreg) return -1; // nak
 
-	int i;
+    int i;
-	for (i = 0; i < length; ++i, ++index) {
+    for (i = 0; i < length; ++i, ++index) {
-		switch (reg) {
+        switch (reg) {
-			// TODO: big or little endian? seems to be big
+            // TODO: big or little endian? seems to be big
-		case cap:
+        case cap:
-			buf[index] = 0;
+            buf[index] = 0;
-			break;
+            break;
-		case config:
+        case config:
-			if (index == 0) buf[0] = (mcp9808.config >> 8) & 0xff;
+            if (index == 0) buf[0] = (mcp9808.config >> 8) & 0xff;
-			else if (index == 1) buf[1] = (mcp9808.config >> 0) & 0xff;
+            else if (index == 1) buf[1] = (mcp9808.config >> 0) & 0xff;
-			else return index;
+            else return index;
-			break;
+            break;
-		case t_upper:
+        case t_upper:
-			if (index == 0) buf[0] = (mcp9808.t_upper >> 8) & 0xff;
+            if (index == 0) buf[0] = (mcp9808.t_upper >> 8) & 0xff;
-			else if (index == 1) buf[1] = (mcp9808.t_upper >> 0) & 0xff;
+            else if (index == 1) buf[1] = (mcp9808.t_upper >> 0) & 0xff;
-			else return index;
+            else return index;
-			break;
+            break;
-		case t_lower:
+        case t_lower:
-			if (index == 0) buf[0] = (mcp9808.t_lower >> 8) & 0xff;
+            if (index == 0) buf[0] = (mcp9808.t_lower >> 8) & 0xff;
-			else if (index == 1) buf[1] = (mcp9808.t_lower >> 0) & 0xff;
+            else if (index == 1) buf[1] = (mcp9808.t_lower >> 0) & 0xff;
-			else return index;
+            else return index;
-			break;
+            break;
-		case t_crit:
+        case t_crit:
-			if (index == 0) buf[0] = (mcp9808.t_crit >> 8) & 0xff;
+            if (index == 0) buf[0] = (mcp9808.t_crit >> 8) & 0xff;
-			else if (index == 1) buf[1] = (mcp9808.t_crit >> 0) & 0xff;
+            else if (index == 1) buf[1] = (mcp9808.t_crit >> 0) & 0xff;
-			else return index;
+            else return index;
-			break;
+            break;
-		case t_a: {
+        case t_a: {
-				static uint16_t temp;
+                static uint16_t temp;
-				if (index == 0) {
+                if (index == 0) {
-					int16_t res = tempsense_dev_get_temp();
+                    int16_t res = tempsense_dev_get_temp();
 
-					uint32_t tup = mcp9808.t_upper & 0x1ffc;
+                    uint32_t tup = mcp9808.t_upper & 0x1ffc;
-					if (tup & 0x1000) tup |= 0xffffe000; // make negative
+                    if (tup & 0x1000) tup |= 0xffffe000; // make negative
-					uint32_t tlo = mcp9808.t_lower & 0x1ffc;
+                    uint32_t tlo = mcp9808.t_lower & 0x1ffc;
-					if (tlo & 0x1000) tlo |= 0xffffe000; // make negative
+                    if (tlo & 0x1000) tlo |= 0xffffe000; // make negative
-					uint32_t tcr = mcp9808.t_crit  & 0x1ffc;
+                    uint32_t tcr = mcp9808.t_crit  & 0x1ffc;
-					if (tcr & 0x1000) tcr |= 0xffffe000; // make negative
+                    if (tcr & 0x1000) tcr |= 0xffffe000; // make negative
 
-					temp = res & 0x1fff; // data bits and sign bit
+                    temp = res & 0x1fff; // data bits and sign bit
 
-					if ((int32_t)tlo > res) temp |= 0x2000;
+                    if ((int32_t)tlo > res) temp |= 0x2000;
-					if ((int32_t)tup < res) temp |= 0x4000;
+                    if ((int32_t)tup < res) temp |= 0x4000;
-					if ((int32_t)tcr < res) temp |= 0x8000;
+                    if ((int32_t)tcr < res) temp |= 0x8000;
 
-					buf[0] = (temp >> 8) & 0xff;
+                    buf[0] = (temp >> 8) & 0xff;
-				} else if (index == 1) buf[1] = (temp>>0) & 0xff;
+                } else if (index == 1) buf[1] = (temp>>0) & 0xff;
-				else return index;
+                else return index;
-			}
+            }
-			break;
+            break;
-		case manuf_id:
+        case manuf_id:
-			if (index == 0) buf[0] = (MANUF_ID >> 8) & 0xff;
+            if (index == 0) buf[0] = (MANUF_ID >> 8) & 0xff;
-			else if (index == 1) buf[1] = (MANUF_ID>>0)&0xff;
+            else if (index == 1) buf[1] = (MANUF_ID>>0)&0xff;
-			else return index;
+            else return index;
-			break;
+            break;
-		case dev_idrev:
+        case dev_idrev:
-			if (index == 0) buf[0] = (DEV_IDREV >> 8) & 0xff;
+            if (index == 0) buf[0] = (DEV_IDREV >> 8) & 0xff;
-			else if (index == 1) buf[1] = (DEV_IDREV>>0)&0xff;
+            else if (index == 1) buf[1] = (DEV_IDREV>>0)&0xff;
-			else return index;
+            else return index;
-			break;
+            break;
-		case reso:
+        case reso:
-			if (index == 0) buf[0] = mcp9808.reso;
+            if (index == 0) buf[0] = mcp9808.reso;
-			else return index;
+            else return index;
-			break;
+            break;
-		default: return -1;
+        default: return -1;
-		}
+        }
-	}
+    }
 
-	return i;
+    return i;
 }
 int tempsense_do_write(int length, const uint8_t* buf) {
-	printf("write l=%d reg=%02x iss=%c ", length, reg, instartstop?'t':'f');
+    printf("write l=%d reg=%02x iss=%c ", length, reg, instartstop?'t':'f');
 
-	if (!instartstop || length < 0) return -1; // nak
+    if (!instartstop || length < 0) return -1; // nak
-	if (length == 0) return 0; // ack
+    if (length == 0) return 0; // ack
 
-	if (!hasreg) {
+    if (!hasreg) {
-		printf("get reg %02x ", reg);
+        printf("get reg %02x ", reg);
 
-		reg = *buf & 0xf;
+        reg = *buf & 0xf;
-		++buf;
+        ++buf;
-		--length;
+        --length;
-		hasreg = true;
+        hasreg = true;
-	}
+    }
 
-	if (length == 0) return 1; // ack, probably a read following
+    if (length == 0) return 1; // ack, probably a read following
 
-	int i;
+    int i;
-	for (i = 0; i < length; ++i, ++index) {
+    for (i = 0; i < length; ++i, ++index) {
-		switch (reg) {
+        switch (reg) {
-		case config:
+        case config:
-			if (index == 0) {
+            if (index == 0) {
-				mcp9808.config = (mcp9808.config & 0x00ff) | ((uint16_t)buf[0] << 8);
+                mcp9808.config = (mcp9808.config & 0x00ff) | ((uint16_t)buf[0] << 8);
-			}  else if (index == 1) {
+            }  else if (index == 1) {
-				mcp9808.config = (mcp9808.config & 0xff00) | ((uint16_t)buf[1] << 0);
+                mcp9808.config = (mcp9808.config & 0xff00) | ((uint16_t)buf[1] << 0);
-			} else return index;
+            } else return index;
-			break;
+            break;
-		case t_upper:
+        case t_upper:
-			if (index == 0) {
+            if (index == 0) {
-				mcp9808.t_upper = (mcp9808.t_upper & 0x00ff) | ((uint16_t)buf[0] << 8);
+                mcp9808.t_upper = (mcp9808.t_upper & 0x00ff) | ((uint16_t)buf[0] << 8);
-			} else if (index == 1) {
+            } else if (index == 1) {
-				mcp9808.t_upper = (mcp9808.t_upper & 0xff00) | ((uint16_t)buf[1] << 0);
+                mcp9808.t_upper = (mcp9808.t_upper & 0xff00) | ((uint16_t)buf[1] << 0);
-			} else return index;
+            } else return index;
-			break;
+            break;
-		case t_lower:
+        case t_lower:
-			if (index == 0) {
+            if (index == 0) {
-				mcp9808.t_lower = (mcp9808.t_lower & 0x00ff) | ((uint16_t)buf[0] << 8);
+                mcp9808.t_lower = (mcp9808.t_lower & 0x00ff) | ((uint16_t)buf[0] << 8);
-			} else if (index == 1) {
+            } else if (index == 1) {
-				mcp9808.t_lower = (mcp9808.t_lower & 0xff00) | ((uint16_t)buf[1] << 0);
+                mcp9808.t_lower = (mcp9808.t_lower & 0xff00) | ((uint16_t)buf[1] << 0);
-			} else return index;
+            } else return index;
-			break;
+            break;
-		case t_crit:
+        case t_crit:
-			if (index == 0) {
+            if (index == 0) {
-				mcp9808.t_crit = (mcp9808.t_crit & 0x00ff) | ((uint16_t)buf[0] << 8);
+                mcp9808.t_crit = (mcp9808.t_crit & 0x00ff) | ((uint16_t)buf[0] << 8);
-			} else if (index == 1) {
+            } else if (index == 1) {
-				mcp9808.t_crit = (mcp9808.t_crit & 0xff00) | ((uint16_t)buf[1] << 0);
+                mcp9808.t_crit = (mcp9808.t_crit & 0xff00) | ((uint16_t)buf[1] << 0);
-			} else return index;
+            } else return index;
-			break;
+            break;
-		case reso:
+        case reso:
-			mcp9808.reso = buf[index];
+            mcp9808.reso = buf[index];
-			break;
+            break;
-		default:
+        default:
-			printf("unk reg\n");
+            printf("unk reg\n");
-			return -1;
+            return -1;
-		}
+        }
-	}
+    }
 
-	return i;
+    return i;
 }
 
 #endif

src/usb_descriptors.c

@@ -45,47 +45,47 @@
 
 // String Descriptor Index
 enum {
-	STRID_LANGID = 0,
+    STRID_LANGID = 0,
-	STRID_MANUFACTURER,
+    STRID_MANUFACTURER,
-	STRID_PRODUCT,
+    STRID_PRODUCT,
-	STRID_SERIAL,
+    STRID_SERIAL,
 
-	STRID_CONFIG,
+    STRID_CONFIG,
 
-	STRID_IF_HID_CMSISDAP,
+    STRID_IF_HID_CMSISDAP,
-	STRID_IF_VND_I2CTINYUSB,
+    STRID_IF_VND_I2CTINYUSB,
-	STRID_IF_CDC_UART,
+    STRID_IF_CDC_UART,
-	STRID_IF_CDC_SERPROG,
+    STRID_IF_CDC_SERPROG,
-	STRID_IF_CDC_STDIO,
+    STRID_IF_CDC_STDIO,
 };
 
 //--------------------------------------------------------------------+
 // Device Descriptors
 //--------------------------------------------------------------------+
 tusb_desc_device_t const desc_device = {
-	.bLength            = sizeof(tusb_desc_device_t),
+    .bLength            = sizeof(tusb_desc_device_t),
-	.bDescriptorType    = TUSB_DESC_DEVICE,
+    .bDescriptorType    = TUSB_DESC_DEVICE,
-	.bcdUSB             = 0x0110, // TODO: 0x0200 ?
+    .bcdUSB             = 0x0110, // TODO: 0x0200 ?
-	.bDeviceClass       = 0x00,
+    .bDeviceClass       = 0x00,
-	.bDeviceSubClass    = 0x00,
+    .bDeviceSubClass    = 0x00,
-	.bDeviceProtocol    = 0x00,
+    .bDeviceProtocol    = 0x00,
-	.bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
+    .bMaxPacketSize0    = CFG_TUD_ENDPOINT0_SIZE,
 
-	.idVendor           = USB_VID,
+    .idVendor           = USB_VID,
-	.idProduct          = USB_PID,
+    .idProduct          = USB_PID,
-	.bcdDevice          = USB_BCD,
+    .bcdDevice          = USB_BCD,
 
-	.iManufacturer      = STRID_MANUFACTURER,
+    .iManufacturer      = STRID_MANUFACTURER,
-	.iProduct           = STRID_PRODUCT,
+    .iProduct           = STRID_PRODUCT,
-	.iSerialNumber      = STRID_SERIAL,
+    .iSerialNumber      = STRID_SERIAL,
 
-	.bNumConfigurations = 0x01
+    .bNumConfigurations = 0x01
 };
 
 // Invoked when received GET DEVICE DESCRIPTOR
 // Application return pointer to descriptor
 uint8_t const * tud_descriptor_device_cb(void) {
-	return (uint8_t const *) &desc_device;
+    return (uint8_t const *) &desc_device;
 }
 
 //--------------------------------------------------------------------+
@@ -93,16 +93,16 @@ uint8_t const * tud_descriptor_device_cb(void) {
 //--------------------------------------------------------------------+
 
 static uint8_t const desc_hid_report[] = {
-	TUD_HID_REPORT_DESC_GENERIC_INOUT(CFG_TUD_HID_EP_BUFSIZE)
+    TUD_HID_REPORT_DESC_GENERIC_INOUT(CFG_TUD_HID_EP_BUFSIZE)
 };
 
 // Invoked when received GET HID REPORT DESCRIPTOR
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
 uint8_t const * tud_hid_descriptor_report_cb(uint8_t instance) {
-	(void) instance;
+    (void) instance;
 
-	return desc_hid_report;
+    return desc_hid_report;
 }
 
 //--------------------------------------------------------------------+
@@ -111,48 +111,48 @@ uint8_t const * tud_hid_descriptor_report_cb(uint8_t instance) {
 
 enum {
 #ifdef DBOARD_HAS_I2C
-	ITF_NUM_VND_I2CTINYUSB,
+    ITF_NUM_VND_I2CTINYUSB,
 #endif
 #ifdef DBOARD_HAS_CMSISDAP
-	ITF_NUM_HID_CMSISDAP,
+    ITF_NUM_HID_CMSISDAP,
 #endif
 #ifdef DBOARD_HAS_UART
-	ITF_NUM_CDC_UART_COM,
+    ITF_NUM_CDC_UART_COM,
-	ITF_NUM_CDC_UART_DATA,
+    ITF_NUM_CDC_UART_DATA,
 #endif
 #ifdef DBOARD_HAS_SERPROG
-	ITF_NUM_CDC_SERPROG_COM,
+    ITF_NUM_CDC_SERPROG_COM,
-	ITF_NUM_CDC_SERPROG_DATA,
+    ITF_NUM_CDC_SERPROG_DATA,
 #endif
 #ifdef USE_USBCDC_FOR_STDIO
-	ITF_NUM_CDC_STDIO_COM,
+    ITF_NUM_CDC_STDIO_COM,
-	ITF_NUM_CDC_STDIO_DATA,
+    ITF_NUM_CDC_STDIO_DATA,
 #endif
 
-	ITF_NUM_TOTAL
+    ITF_NUM_TOTAL
 };
 
 #define TUD_I2CTINYUSB_LEN (9)
 #define TUD_I2CTINYUSB_DESCRIPTOR(_itfnum, _stridx) \
-	9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, 0, 0, 0, _stridx \
+    9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, 0, 0, 0, _stridx \
 
 
 enum {
-	CONFIG_TOTAL_LEN = TUD_CONFIG_DESC_LEN
+    CONFIG_TOTAL_LEN = TUD_CONFIG_DESC_LEN
 #ifdef DBOARD_HAS_I2C
-		+ TUD_I2CTINYUSB_LEN
+        + TUD_I2CTINYUSB_LEN
 #endif
 #ifdef DBOARD_HAS_UART
-		+ TUD_CDC_DESC_LEN
+        + TUD_CDC_DESC_LEN
 #endif
 #ifdef DBOARD_HAS_CMSISDAP
-		+ TUD_HID_INOUT_DESC_LEN
+        + TUD_HID_INOUT_DESC_LEN
 #endif
 #ifdef DBOARD_HAS_SERPROG
-		+ TUD_CDC_DESC_LEN
+        + TUD_CDC_DESC_LEN
 #endif
 #ifdef USE_USBCDC_FOR_STDIO
-		+ TUD_CDC_DESC_LEN
+        + TUD_CDC_DESC_LEN
 #endif
 };
 
@@ -170,26 +170,26 @@ enum {
 // NOTE: if you modify this table, don't forget to keep tusb_config.h up to date as well!
 // TODO: maybe add some strings to all these interfaces
 uint8_t const desc_configuration[] = {
-	TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, STRID_CONFIG, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
+    TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, STRID_CONFIG, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100),
 
 #ifdef DBOARD_HAS_CMSISDAP
-	TUD_HID_INOUT_DESCRIPTOR(ITF_NUM_HID_CMSISDAP, STRID_IF_HID_CMSISDAP, 0/*HID_PROTOCOL_NONE*/, sizeof(desc_hid_report), EPNUM_HID_CMSISDAP, 0x80 | (EPNUM_HID_CMSISDAP+0), CFG_TUD_HID_EP_BUFSIZE, 1),
+    TUD_HID_INOUT_DESCRIPTOR(ITF_NUM_HID_CMSISDAP, STRID_IF_HID_CMSISDAP, 0/*HID_PROTOCOL_NONE*/, sizeof(desc_hid_report), EPNUM_HID_CMSISDAP, 0x80 | (EPNUM_HID_CMSISDAP+0), CFG_TUD_HID_EP_BUFSIZE, 1),
 #endif
 
 #ifdef DBOARD_HAS_I2C
-	TUD_I2CTINYUSB_DESCRIPTOR(ITF_NUM_VND_I2CTINYUSB, STRID_IF_VND_I2CTINYUSB),
+    TUD_I2CTINYUSB_DESCRIPTOR(ITF_NUM_VND_I2CTINYUSB, STRID_IF_VND_I2CTINYUSB),
 #endif
 
 #ifdef DBOARD_HAS_UART
-	TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_UART_COM, STRID_IF_CDC_UART, EPNUM_CDC_UART_NOTIF, 64, EPNUM_CDC_UART_OUT, EPNUM_CDC_UART_IN, 64),
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_UART_COM, STRID_IF_CDC_UART, EPNUM_CDC_UART_NOTIF, 64, EPNUM_CDC_UART_OUT, EPNUM_CDC_UART_IN, 64),
 #endif
 
 #ifdef DBOARD_HAS_SERPROG
-	TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_SERPROG_COM, STRID_IF_CDC_SERPROG, EPNUM_CDC_SERPROG_NOTIF, 64, EPNUM_CDC_SERPROG_OUT, EPNUM_CDC_SERPROG_IN, 64),
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_SERPROG_COM, STRID_IF_CDC_SERPROG, EPNUM_CDC_SERPROG_NOTIF, 64, EPNUM_CDC_SERPROG_OUT, EPNUM_CDC_SERPROG_IN, 64),
 #endif
 
 #ifdef USE_USBCDC_FOR_STDIO
-	TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_STDIO_COM, STRID_IF_CDC_STDIO, EPNUM_CDC_STDIO_NOTIF, 64, EPNUM_CDC_STDIO_OUT, EPNUM_CDC_STDIO_IN, 64),
+    TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_STDIO_COM, STRID_IF_CDC_STDIO, EPNUM_CDC_STDIO_NOTIF, 64, EPNUM_CDC_STDIO_OUT, EPNUM_CDC_STDIO_IN, 64),
 #endif
 };
 
@@ -197,8 +197,8 @@ uint8_t const desc_configuration[] = {
 // Application return pointer to descriptor
 // Descriptor contents must exist long enough for transfer to complete
 uint8_t const * tud_descriptor_configuration_cb(uint8_t index) {
-	(void) index; // for multiple configurations
+    (void) index; // for multiple configurations
-	return desc_configuration;
+    return desc_configuration;
 }
 
 //--------------------------------------------------------------------+
@@ -207,54 +207,54 @@ uint8_t const * tud_descriptor_configuration_cb(uint8_t index) {
 
 // array of pointer to string descriptors
 char const* string_desc_arr [] = {
-	[STRID_LANGID]       = (const char[]) { 0x09, 0x04 }, // supported language is English (0x0409)
+    [STRID_LANGID]       = (const char[]) { 0x09, 0x04 }, // supported language is English (0x0409)
-	[STRID_MANUFACTURER] = INFO_MANUFACTURER,             // Manufacturer
+    [STRID_MANUFACTURER] = INFO_MANUFACTURER,             // Manufacturer
-	[STRID_PRODUCT]      = INFO_PRODUCT(INFO_BOARDNAME),  // Product
+    [STRID_PRODUCT]      = INFO_PRODUCT(INFO_BOARDNAME),  // Product
 
-	[STRID_CONFIG]            = "Configuration descriptor",
+    [STRID_CONFIG]            = "Configuration descriptor",
-	// max string length check:  |||||||||||||||||||||||||||||||
+    // max string length check:  |||||||||||||||||||||||||||||||
-	[STRID_IF_HID_CMSISDAP]   = "CMSIS-DAP HID interface",
+    [STRID_IF_HID_CMSISDAP]   = "CMSIS-DAP HID interface",
-	[STRID_IF_VND_I2CTINYUSB] = "I2C-Tiny-USB interface",
+    [STRID_IF_VND_I2CTINYUSB] = "I2C-Tiny-USB interface",
-	[STRID_IF_CDC_UART]       = "UART CDC interface",
+    [STRID_IF_CDC_UART]       = "UART CDC interface",
-	[STRID_IF_CDC_SERPROG]    = "Serprog CDC interface",
+    [STRID_IF_CDC_SERPROG]    = "Serprog CDC interface",
-	[STRID_IF_CDC_STDIO]      = "stdio CDC interface (debug)",
+    [STRID_IF_CDC_STDIO]      = "stdio CDC interface (debug)",
 };
 
 // Invoked when received GET STRING DESCRIPTOR request
 // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
 uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) {
-	static uint16_t _desc_str[32];
+    static uint16_t _desc_str[32];
 
-	(void) langid;
+    (void) langid;
 
-	uint8_t chr_count = 0;
+    uint8_t chr_count = 0;
 
-	if (STRID_LANGID == index) {
+    if (STRID_LANGID == index) {
-		memcpy(&_desc_str[1], string_desc_arr[STRID_LANGID], 2);
+        memcpy(&_desc_str[1], string_desc_arr[STRID_LANGID], 2);
-		chr_count = 1;
+        chr_count = 1;
-	} else if (STRID_SERIAL == index) {
+    } else if (STRID_SERIAL == index) {
-		chr_count = get_unique_id_u16(_desc_str + 1);
+        chr_count = get_unique_id_u16(_desc_str + 1);
-	} else {
+    } else {
-		// Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
+        // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors.
-		// https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
+        // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors
 
-		if (!(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])))
+        if (!(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])))
-			return NULL;
+            return NULL;
 
-		const char* str = string_desc_arr[index];
+        const char* str = string_desc_arr[index];
 
-		// Cap at max char
+        // Cap at max char
-		chr_count = TU_MIN(strlen(str), 31);
+        chr_count = TU_MIN(strlen(str), 31);
 
-		// Convert ASCII string into UTF-16
+        // Convert ASCII string into UTF-16
-		for (int i = 0; i < chr_count; i++) {
+        for (int i = 0; i < chr_count; i++) {
-			_desc_str[1+i] = str[i];
+            _desc_str[1+i] = str[i];
-		}
+        }
-	}
+    }
 
-	// first byte is length (including header), second byte is string type
+    // first byte is length (including header), second byte is string type
-	_desc_str[0] = (TUSB_DESC_STRING << 8) | (2*chr_count + 2);
+    _desc_str[0] = (TUSB_DESC_STRING << 8) | (2*chr_count + 2);
 
-	return _desc_str;
+    return _desc_str;
 }
 

src/util.h

@@ -3,8 +3,8 @@
 #define UTIL_H_
 
 static inline char nyb2hex(int x) {
-	if (x < 0xa) return '0'+(x-0);
+    if (x < 0xa) return '0'+(x-0);
-	else return 'A'+(x-0xa);
+    else return 'A'+(x-0xa);
 }
 
 void thread_yield(void);

src/vnd_i2ctinyusb.c

@@ -28,214 +28,214 @@ static uint8_t rxbuf[128];
 static uint8_t txbuf[128];
 
 static void iub_init(void) {
-	status = ITU_STATUS_IDLE;
+    status = ITU_STATUS_IDLE;
-	memset(&curcmd, 0, sizeof curcmd);
+    memset(&curcmd, 0, sizeof curcmd);
 
-	i2ctu_init();
+    i2ctu_init();
 #ifdef DBOARD_HAS_TEMPSENSOR
-	tempsense_init();
+    tempsense_init();
 #endif
 }
 
 static void iub_reset(uint8_t rhport) {
-	status = ITU_STATUS_IDLE;
+    status = ITU_STATUS_IDLE;
-	memset(&curcmd, 0, sizeof curcmd);
+    memset(&curcmd, 0, sizeof curcmd);
 
-	i2ctu_init();
+    i2ctu_init();
 #ifdef DBOARD_HAS_TEMPSENSOR
-	tempsense_init();
+    tempsense_init();
 #endif
 
-	itf_num = 0;
+    itf_num = 0;
 }
 
 static uint16_t iub_open(uint8_t rhport, tusb_desc_interface_t const* itf_desc,
-		uint16_t max_len) {
+        uint16_t max_len) {
-	TU_VERIFY(itf_desc->bInterfaceClass == 0
+    TU_VERIFY(itf_desc->bInterfaceClass == 0
-	       && itf_desc->bInterfaceSubClass == 0
+           && itf_desc->bInterfaceSubClass == 0
-	       && itf_desc->bInterfaceProtocol == 0, 0);
+           && itf_desc->bInterfaceProtocol == 0, 0);
 
-	const uint16_t drv_len = sizeof(tusb_desc_interface_t);
+    const uint16_t drv_len = sizeof(tusb_desc_interface_t);
-	TU_VERIFY(max_len >= drv_len, 0);
+    TU_VERIFY(max_len >= drv_len, 0);
 
-	itf_num = itf_desc->bInterfaceNumber;
+    itf_num = itf_desc->bInterfaceNumber;
 
-	return drv_len;
+    return drv_len;
 }
 
 static bool iub_ctl_req(uint8_t rhport, uint8_t stage, tusb_control_request_t const* req) {
-	/*static char* stages[]={"SETUP","DATA","ACK"};
+    /*static char* stages[]={"SETUP","DATA","ACK"};
-	static char* types[]={"STD","CLS","VND","INV"};
+    static char* types[]={"STD","CLS","VND","INV"};
 
-	printf("ctl req stage=%s rt=%s, wIndex=%04x, bReq=%02x, wValue=%04x wLength=%04x\n",
+    printf("ctl req stage=%s rt=%s, wIndex=%04x, bReq=%02x, wValue=%04x wLength=%04x\n",
-		stages[stage], types[req->bmRequestType_bit.type],
+        stages[stage], types[req->bmRequestType_bit.type],
-		req->wIndex, req->bRequest, req->wValue, req->wLength);*/
+        req->wIndex, req->bRequest, req->wValue, req->wLength);*/
 
-	if (req->bmRequestType_bit.type != TUSB_REQ_TYPE_VENDOR) return true;
+    if (req->bmRequestType_bit.type != TUSB_REQ_TYPE_VENDOR) return true;
 
-	if (stage == CONTROL_STAGE_DATA) {
+    if (stage == CONTROL_STAGE_DATA) {
-		struct itu_cmd cmd = curcmd;
+        struct itu_cmd cmd = curcmd;
 
-		if (req->bRequest >= ITU_CMD_I2C_IO && req->bRequest <= ITU_CMD_I2C_IO_BEGINEND
+        if (req->bRequest >= ITU_CMD_I2C_IO && req->bRequest <= ITU_CMD_I2C_IO_BEGINEND
-				&& cmd.cmd == req->bRequest && cmd.flags == req->wValue
+                && cmd.cmd == req->bRequest && cmd.flags == req->wValue
-				&& cmd.addr == req->wIndex && cmd.len == req->wLength) {
+                && cmd.addr == req->wIndex && cmd.len == req->wLength) {
-			//printf("WDATA a=%04hx l=%04hx ", cmd.addr, cmd.len);
+            //printf("WDATA a=%04hx l=%04hx ", cmd.addr, cmd.len);
 
-			//printf("data=%02x %02x...\n", rxbuf[0], rxbuf[1]);
+            //printf("data=%02x %02x...\n", rxbuf[0], rxbuf[1]);
 #ifdef DBOARD_HAS_TEMPSENSOR
-			if (tempsense_get_active() && tempsense_get_addr() == cmd.addr) {
+            if (tempsense_get_active() && tempsense_get_addr() == cmd.addr) {
-				if (cmd.cmd & ITU_CMD_I2C_IO_BEGIN_F) tempsense_do_start();
+                if (cmd.cmd & ITU_CMD_I2C_IO_BEGIN_F) tempsense_do_start();
-				// FIXME: fix status handling
+                // FIXME: fix status handling
-				int rv = tempsense_do_write(cmd.len > sizeof rxbuf ? sizeof rxbuf : cmd.len, rxbuf);
+                int rv = tempsense_do_write(cmd.len > sizeof rxbuf ? sizeof rxbuf : cmd.len, rxbuf);
-				if (rv < 0 || rv != cmd.len) status = ITU_STATUS_ADDR_NAK;
+                if (rv < 0 || rv != cmd.len) status = ITU_STATUS_ADDR_NAK;
-				else status = ITU_STATUS_ADDR_ACK;
+                else status = ITU_STATUS_ADDR_ACK;
-				if (cmd.cmd & ITU_CMD_I2C_IO_END_F  ) tempsense_do_stop ();
+                if (cmd.cmd & ITU_CMD_I2C_IO_END_F  ) tempsense_do_stop ();
-			} else
+            } else
 #endif
-			{
+            {
-				status = i2ctu_write(cmd.flags, cmd.cmd & ITU_CMD_I2C_IO_DIR_MASK,
+                status = i2ctu_write(cmd.flags, cmd.cmd & ITU_CMD_I2C_IO_DIR_MASK,
-					cmd.addr, rxbuf, cmd.len > sizeof rxbuf ? sizeof rxbuf : cmd.len);
+                    cmd.addr, rxbuf, cmd.len > sizeof rxbuf ? sizeof rxbuf : cmd.len);
-			}
+            }
 
-			// cancel curcmd
+            // cancel curcmd
-			curcmd.cmd = 0xff;
+            curcmd.cmd = 0xff;
-		}
+        }
-		return true;
+        return true;
-	} else if (stage == CONTROL_STAGE_SETUP) {
+    } else if (stage == CONTROL_STAGE_SETUP) {
-		switch (req->bRequest) {
+        switch (req->bRequest) {
-		case ITU_CMD_ECHO: { // flags to be echoed back, addr unused, len=2
+        case ITU_CMD_ECHO: { // flags to be echoed back, addr unused, len=2
-				if (req->wLength != 2) return false; // bad length -> let's stall
+                if (req->wLength != 2) return false; // bad length -> let's stall
 
-				uint8_t rv[2];
+                uint8_t rv[2];
-				rv[0] = req->wValue&0xff;
+                rv[0] = req->wValue&0xff;
-				rv[1] = (req->wValue>>8)&0xff;
+                rv[1] = (req->wValue>>8)&0xff;
-				return tud_control_xfer(rhport, req, rv, sizeof rv);
+                return tud_control_xfer(rhport, req, rv, sizeof rv);
-			}
+            }
-			break;
+            break;
-		case ITU_CMD_GET_FUNC: { // flags unused, addr unused, len=4
+        case ITU_CMD_GET_FUNC: { // flags unused, addr unused, len=4
-				if (req->wLength != 4) return false;
+                if (req->wLength != 4) return false;
 
-				const uint32_t func = i2ctu_get_func();
+                const uint32_t func = i2ctu_get_func();
-				txbuf[0]=func&0xff;
+                txbuf[0]=func&0xff;
-				txbuf[1]=(func>>8)&0xff;
+                txbuf[1]=(func>>8)&0xff;
-				txbuf[2]=(func>>16)&0xff;
+                txbuf[2]=(func>>16)&0xff;
-				txbuf[3]=(func>>24)&0xff;
+                txbuf[3]=(func>>24)&0xff;
-				return tud_control_xfer(rhport, req, txbuf, 4);
+                return tud_control_xfer(rhport, req, txbuf, 4);
-			}
+            }
-			break;
+            break;
-		case ITU_CMD_SET_DELAY: { // flags=delay, addr unused, len=0
+        case ITU_CMD_SET_DELAY: { // flags=delay, addr unused, len=0
-				if (req->wLength != 0) return false;
+                if (req->wLength != 0) return false;
 
-				uint32_t us = req->wValue ? req->wValue : 1;
+                uint32_t us = req->wValue ? req->wValue : 1;
-				uint32_t freq = 1000*1000 / us;
+                uint32_t freq = 1000*1000 / us;
 
-				//printf("set freq us=%u freq=%u\n", us, freq);
+                //printf("set freq us=%u freq=%u\n", us, freq);
-				if (i2ctu_set_freq(freq, us) != 0) // returned an ok frequency
+                if (i2ctu_set_freq(freq, us) != 0) // returned an ok frequency
-					return tud_control_status(rhport, req);
+                    return tud_control_status(rhport, req);
-				else return false;
+                else return false;
-			}
+            }
-			break;
+            break;
-		case ITU_CMD_GET_STATUS: { // flags unused, addr unused, len=1
+        case ITU_CMD_GET_STATUS: { // flags unused, addr unused, len=1
-				if (req->wLength != 1) return false;
+                if (req->wLength != 1) return false;
 
-				uint8_t rv = status;
+                uint8_t rv = status;
-				return tud_control_xfer(rhport, req, &rv, 1);
+                return tud_control_xfer(rhport, req, &rv, 1);
-			}
+            }
-			break;
+            break;
 
-		case ITU_CMD_I2C_IO:            // flags: ki2c_flags
+        case ITU_CMD_I2C_IO:            // flags: ki2c_flags
-		case ITU_CMD_I2C_IO_BEGIN:      // addr: I2C address
+        case ITU_CMD_I2C_IO_BEGIN:      // addr: I2C address
-		case ITU_CMD_I2C_IO_END:        // len: transfer size
+        case ITU_CMD_I2C_IO_END:        // len: transfer size
-		case ITU_CMD_I2C_IO_BEGINEND: { // (transfer dir is in flags)
+        case ITU_CMD_I2C_IO_BEGINEND: { // (transfer dir is in flags)
-				struct itu_cmd cmd;
+                struct itu_cmd cmd;
-				cmd.flags = req->wValue;
+                cmd.flags = req->wValue;
-				cmd.addr  = req->wIndex;
+                cmd.addr  = req->wIndex;
-				cmd.len   = req->wLength;
+                cmd.len   = req->wLength;
-				cmd.cmd   = req->bRequest;
+                cmd.cmd   = req->bRequest;
 
-				if (cmd.flags & I2C_M_RD) { // read from I2C device
+                if (cmd.flags & I2C_M_RD) { // read from I2C device
-					//printf("read addr=%04hx len=%04hx ", cmd.addr, cmd.len);
+                    //printf("read addr=%04hx len=%04hx ", cmd.addr, cmd.len);
 #ifdef DBOARD_HAS_TEMPSENSOR
-					if (tempsense_get_active() && tempsense_get_addr() == cmd.addr) {
+                    if (tempsense_get_active() && tempsense_get_addr() == cmd.addr) {
-						if (cmd.cmd & ITU_CMD_I2C_IO_BEGIN_F) tempsense_do_start();
+                        if (cmd.cmd & ITU_CMD_I2C_IO_BEGIN_F) tempsense_do_start();
-						int rv = tempsense_do_read(cmd.len > sizeof txbuf ? sizeof txbuf : cmd.len, txbuf);
+                        int rv = tempsense_do_read(cmd.len > sizeof txbuf ? sizeof txbuf : cmd.len, txbuf);
-						if (rv < 0 || rv != cmd.len) status = ITU_STATUS_ADDR_NAK;
+                        if (rv < 0 || rv != cmd.len) status = ITU_STATUS_ADDR_NAK;
-						else status = ITU_STATUS_ADDR_ACK;
+                        else status = ITU_STATUS_ADDR_ACK;
-						if (cmd.cmd & ITU_CMD_I2C_IO_END_F  ) tempsense_do_stop ();
+                        if (cmd.cmd & ITU_CMD_I2C_IO_END_F  ) tempsense_do_stop ();
-					} else
+                    } else
 #endif
-					{
+                    {
-						status = i2ctu_read(cmd.flags, cmd.cmd & ITU_CMD_I2C_IO_DIR_MASK,
+                        status = i2ctu_read(cmd.flags, cmd.cmd & ITU_CMD_I2C_IO_DIR_MASK,
-							cmd.addr, txbuf, cmd.len > sizeof txbuf ? sizeof txbuf : cmd.len);
+                            cmd.addr, txbuf, cmd.len > sizeof txbuf ? sizeof txbuf : cmd.len);
-					}
+                    }
-					//printf("data=%02x %02x...\n", txbuf[0], txbuf[1]);
+                    //printf("data=%02x %02x...\n", txbuf[0], txbuf[1]);
-					return tud_control_xfer(rhport, req, txbuf,
+                    return tud_control_xfer(rhport, req, txbuf,
-							cmd.len > sizeof txbuf ? sizeof txbuf : cmd.len);
+                            cmd.len > sizeof txbuf ? sizeof txbuf : cmd.len);
-				} else { // write
+                } else { // write
-					//printf("write addr=%04hx len=%04hx ", cmd.addr, cmd.len);
+                    //printf("write addr=%04hx len=%04hx ", cmd.addr, cmd.len);
-					if (cmd.len == 0) { // address probe -> do this here
+                    if (cmd.len == 0) { // address probe -> do this here
-						uint8_t bleh = 0;
+                        uint8_t bleh = 0;
 #ifdef DBOARD_HAS_TEMPSENSOR
-						if (tempsense_get_active() && tempsense_get_addr() == cmd.addr) {
+                        if (tempsense_get_active() && tempsense_get_addr() == cmd.addr) {
-							if (cmd.cmd & ITU_CMD_I2C_IO_BEGIN_F) tempsense_do_start();
+                            if (cmd.cmd & ITU_CMD_I2C_IO_BEGIN_F) tempsense_do_start();
-							int rv = tempsense_do_write(0, &bleh);
+                            int rv = tempsense_do_write(0, &bleh);
-							if (rv < 0 || rv != cmd.len) status = ITU_STATUS_ADDR_NAK;
+                            if (rv < 0 || rv != cmd.len) status = ITU_STATUS_ADDR_NAK;
-							else status = ITU_STATUS_ADDR_ACK;
+                            else status = ITU_STATUS_ADDR_ACK;
-							if (cmd.cmd & ITU_CMD_I2C_IO_END_F  ) tempsense_do_stop ();
+                            if (cmd.cmd & ITU_CMD_I2C_IO_END_F  ) tempsense_do_stop ();
-						} else
+                        } else
 #endif
-						{
+                        {
-							status = i2ctu_write(cmd.flags, cmd.cmd & ITU_CMD_I2C_IO_DIR_MASK,
+                            status = i2ctu_write(cmd.flags, cmd.cmd & ITU_CMD_I2C_IO_DIR_MASK,
-								cmd.addr, &bleh, 0);
+                                cmd.addr, &bleh, 0);
-						}
+                        }
-						//printf("probe -> %d\n", status);
+                        //printf("probe -> %d\n", status);
-						return tud_control_status(rhport, req);
+                        return tud_control_status(rhport, req);
-					} else {
+                    } else {
-						// handled in DATA stage!
+                        // handled in DATA stage!
-						curcmd = cmd;
+                        curcmd = cmd;
-						bool rv = tud_control_xfer(rhport, req, rxbuf,
+                        bool rv = tud_control_xfer(rhport, req, rxbuf,
-								cmd.len > sizeof rxbuf ? sizeof rxbuf : cmd.len);
+                                cmd.len > sizeof rxbuf ? sizeof rxbuf : cmd.len);
-						return rv;
+                        return rv;
-					}
+                    }
-				}
+                }
-			}
+            }
-			break;
+            break;
-		default:
+        default:
-			//printf("I2C-Tiny-USB: unknown command %02x\n", req->bRequest);
+            //printf("I2C-Tiny-USB: unknown command %02x\n", req->bRequest);
-			return false;
+            return false;
-		}
+        }
-	} else return true; // other stage...
+    } else return true; // other stage...
 }
 
 // never actually called fsr
 static bool iub_xfer(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
-	return true;
+    return true;
 }
 
 // interfacing stuff for TinyUSB API, actually defines the driver
 
 static usbd_class_driver_t const i2ctinyusb_driver = {
 #if CFG_TUSB_DEBUG >= 2
-	.name = "i2c-tiny-usb",
+    .name = "i2c-tiny-usb",
 #endif
 
-	.init            = iub_init,
+    .init            = iub_init,
-	.reset           = iub_reset,
+    .reset           = iub_reset,
-	.open            = iub_open,
+    .open            = iub_open,
-	.control_xfer_cb = iub_ctl_req,
+    .control_xfer_cb = iub_ctl_req,
-	.xfer_cb         = iub_xfer,
+    .xfer_cb         = iub_xfer,
-	.sof             = NULL
+    .sof             = NULL
 };
 
 usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) {
-	*driver_count = 1;
+    *driver_count = 1;
-	return &i2ctinyusb_driver;
+    return &i2ctinyusb_driver;
 }
 
 // we need to implement this one, because tinyusb uses hardcoded stuff for
 // endpoint 0, which is what the i2c-tiny-usb kernel module uses
 bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, tusb_control_request_t const* req) {
-	return iub_ctl_req(rhport, ep_addr, req);
+    return iub_ctl_req(rhport, ep_addr, req);
 }
 
 #endif /* DBOARD_HAS_I2C */