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Allow stub to return an error code.

This commit is contained in:
Gareth McMullin 2015-03-08 15:02:38 -07:00
parent 437aedda11
commit 8ddb186b35
5 changed files with 52 additions and 13 deletions
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9
flashstub/stm32f1.c
View File

@ -18,6 +18,9 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#include "libopencm3/stm32/flash.h" #include "libopencm3/stm32/flash.h"
#include "stub.h"
#define SR_ERROR_MASK 0x14
void __attribute__((naked)) void __attribute__((naked))
stm32f1_flash_write_stub(uint16_t *dest, uint16_t *src, uint32_t size) stm32f1_flash_write_stub(uint16_t *dest, uint16_t *src, uint32_t size)
@ -29,6 +32,10 @@ stm32f1_flash_write_stub(uint16_t *dest, uint16_t *src, uint32_t size)
while (FLASH_SR & FLASH_SR_BSY) while (FLASH_SR & FLASH_SR_BSY)
; ;
} }
asm("bkpt");
if (FLASH_SR & SR_ERROR_MASK)
stub_exit(1);
stub_exit(0);
} }

2
flashstub/stm32f1.stub
View File

@ -1 +1 @@
0x4613, 0xE010, 0x4A09, 0x2401, 0x6014, 0x4602, 0x1C90, 0x460C, 0x1CA1, 0x8824, 0x8014, 0x3B02, 0xBF00, 0x4A05, 0x6812, 0xF002, 0x0201, 0x2A00, 0xD1F9, 0x2B00, 0xD1EC, 0xBE00, 0x2010, 0x4002, 0x200C, 0x4002, 0x4613, 0xE010, 0x4A0D, 0x2401, 0x6014, 0x4602, 0x1C90, 0x460C, 0x1CA1, 0x8824, 0x8014, 0x3B02, 0xBF00, 0x4A09, 0x6812, 0xF002, 0x0201, 0x2A00, 0xD1F9, 0x2B00, 0xD1EC, 0x4B05, 0x681B, 0xF003, 0x0314, 0x2B00, 0xD000, 0xBE01, 0xBE00, 0xBF00, 0x2010, 0x4002, 0x200C, 0x4002,

30
flashstub/stub.h Normal file
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@ -0,0 +1,30 @@
/*
* This file is part of the Black Magic Debug project.
*
* Copyright (C) 2015 Black Sphere Technologies Ltd.
* Written by Gareth McMullin <gareth@blacksphere.co.nz>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __STUB_H
#define __STUB_H
static inline __attribute__((always_inline))
stub_exit(const int code)
{
asm("bkpt %0"::"i"(code));
}
#endif

9
src/cortexm.c
View File

@ -60,6 +60,7 @@ const struct command_s cortexm_cmd_list[] = {
static int cortexm_regs_read(struct target_s *target, void *data); static int cortexm_regs_read(struct target_s *target, void *data);
static int cortexm_regs_write(struct target_s *target, const void *data); static int cortexm_regs_write(struct target_s *target, const void *data);
static int cortexm_pc_write(struct target_s *target, const uint32_t val); static int cortexm_pc_write(struct target_s *target, const uint32_t val);
static uint32_t cortexm_pc_read(struct target_s *target);
static void cortexm_reset(struct target_s *target); static void cortexm_reset(struct target_s *target);
static int cortexm_halt_wait(struct target_s *target); static int cortexm_halt_wait(struct target_s *target);
@ -216,6 +217,7 @@ cortexm_probe(struct target_s *target)
target->regs_read = cortexm_regs_read; target->regs_read = cortexm_regs_read;
target->regs_write = cortexm_regs_write; target->regs_write = cortexm_regs_write;
target->pc_write = cortexm_pc_write; target->pc_write = cortexm_pc_write;
target->pc_read = cortexm_pc_read;
target->reset = cortexm_reset; target->reset = cortexm_reset;
target->halt_request = cortexm_halt_request; target->halt_request = cortexm_halt_request;
@ -629,7 +631,12 @@ int cortexm_run_stub(struct target_s *target, uint32_t loadaddr,
while (!cortexm_halt_wait(target)) while (!cortexm_halt_wait(target))
; ;
return 0; uint32_t pc = cortexm_pc_read(target);
uint16_t bkpt_instr = target_mem_read16(target, pc);
if (bkpt_instr >> 8 != 0xbe)
return -2;
return bkpt_instr & 0xff;
} }
/* The following routines implement hardware breakpoints. /* The following routines implement hardware breakpoints.

13
src/stm32f1.c
View File

@ -256,16 +256,11 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest,
memcpy((uint8_t *)data + offset, src, len); memcpy((uint8_t *)data + offset, src, len);
/* Write stub and data to target ram and set PC */ /* Write stub and data to target ram and set PC */
target_mem_write(target, STUB_BUFFER_BASE, data, sizeof(data)); target_mem_write(target, STUB_BUFFER_BASE, (void*)data, sizeof(data));
cortexm_run_stub(target, SRAM_BASE, stm32f1_flash_write_stub, return cortexm_run_stub(target, SRAM_BASE, stm32f1_flash_write_stub,
sizeof(stm32f1_flash_write_stub), sizeof(stm32f1_flash_write_stub),
dest - offset, STUB_BUFFER_BASE, sizeof(data), 0); dest - offset, STUB_BUFFER_BASE, sizeof(data),
0);
/* Check for error */
if (target_mem_read32(target, FLASH_SR) & SR_ERROR_MASK)
return -1;
return 0;
} }
static bool stm32f1_cmd_erase_mass(target *t) static bool stm32f1_cmd_erase_mass(target *t)