Avoid repetition of cortexm code in stmd20 driver.
This commit is contained in:
Gareth McMullin
parent
f1981925b3
commit
a3ab9b24d1
134
src/cortexm.c
134
src/cortexm.c
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@ -40,6 +40,7 @@
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#include "target.h"
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#include "command.h"
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#include "gdb_packet.h"
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#include "cortexm.h"
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static char cortexm_driver_str[] = "ARM Cortex-M";
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@ -54,142 +55,18 @@ const struct command_s cortexm_cmd_list[] = {
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#define TOPT_FLAVOUR_V6M (1<<0) /* if not set, target is assumed to be v7m */
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#define TOPT_FLAVOUR_V7MF (1<<1) /* if set, floating-point enabled. */
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/* Private peripheral bus base address */
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#define CORTEXM_PPB_BASE 0xE0000000
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#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000)
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#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C)
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#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28)
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#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C)
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#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30)
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#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88)
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#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0)
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#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4)
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#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8)
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#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC)
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#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000)
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/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */
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#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000)
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#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004)
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#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i)))
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#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000)
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#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000)
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#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i)))
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#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i)))
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#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i)))
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/* Application Interrupt and Reset Control Register (AIRCR) */
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#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16)
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/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */
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#define CORTEXM_AIRCR_ENDIANESS (1 << 15)
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/* Bits 15:11 - Unused, reserved */
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#define CORTEXM_AIRCR_PRIGROUP (7 << 8)
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/* Bits 7:3 - Unused, reserved */
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#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2)
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#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1)
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#define CORTEXM_AIRCR_VECTRESET (1 << 0)
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/* HardFault Status Register (HFSR) */
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#define CORTEXM_HFSR_DEBUGEVT (1 << 31)
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#define CORTEXM_HFSR_FORCED (1 << 30)
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/* Bits 29:2 - Not specified */
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#define CORTEXM_HFSR_VECTTBL (1 << 1)
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/* Bits 0 - Reserved */
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/* Debug Fault Status Register (DFSR) */
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/* Bits 31:5 - Reserved */
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#define CORTEXM_DFSR_RESETALL 0x1F
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#define CORTEXM_DFSR_EXTERNAL (1 << 4)
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#define CORTEXM_DFSR_VCATCH (1 << 3)
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#define CORTEXM_DFSR_DWTTRAP (1 << 2)
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#define CORTEXM_DFSR_BKPT (1 << 1)
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#define CORTEXM_DFSR_HALTED (1 << 0)
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/* Debug Halting Control and Status Register (DHCSR) */
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/* This key must be written to bits 31:16 for write to take effect */
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#define CORTEXM_DHCSR_DBGKEY 0xA05F0000
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/* Bits 31:26 - Reserved */
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#define CORTEXM_DHCSR_S_RESET_ST (1 << 25)
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#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DHCSR_S_LOCKUP (1 << 19)
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#define CORTEXM_DHCSR_S_SLEEP (1 << 18)
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#define CORTEXM_DHCSR_S_HALT (1 << 17)
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#define CORTEXM_DHCSR_S_REGRDY (1 << 16)
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/* Bits 15:6 - Reserved */
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#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */
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/* Bit 4 - Reserved */
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#define CORTEXM_DHCSR_C_MASKINTS (1 << 3)
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#define CORTEXM_DHCSR_C_STEP (1 << 2)
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#define CORTEXM_DHCSR_C_HALT (1 << 1)
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#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0)
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/* Debug Core Register Selector Register (DCRSR) */
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#define CORTEXM_DCRSR_REGWnR 0x00010000
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#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001F
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#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010
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#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011
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#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012
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/* Debug Exception and Monitor Control Register (DEMCR) */
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/* Bits 31:25 - Reserved */
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#define CORTEXM_DEMCR_TRCENA (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DEMCR_MON_REQ (1 << 19) /* v7m only */
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#define CORTEXM_DEMCR_MON_STEP (1 << 18) /* v7m only */
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#define CORTEXM_DEMCR_VC_MON_PEND (1 << 17) /* v7m only */
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#define CORTEXM_DEMCR_VC_MON_EN (1 << 16) /* v7m only */
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/* Bits 15:11 - Reserved */
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#define CORTEXM_DEMCR_VC_HARDERR (1 << 10)
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#define CORTEXM_DEMCR_VC_INTERR (1 << 9) /* v7m only */
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#define CORTEXM_DEMCR_VC_BUSERR (1 << 8) /* v7m only */
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#define CORTEXM_DEMCR_VC_STATERR (1 << 7) /* v7m only */
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#define CORTEXM_DEMCR_VC_CHKERR (1 << 6) /* v7m only */
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#define CORTEXM_DEMCR_VC_NOCPERR (1 << 5) /* v7m only */
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#define CORTEXM_DEMCR_VC_MMERR (1 << 4) /* v7m only */
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/* Bits 3:1 - Reserved */
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#define CORTEXM_DEMCR_VC_CORERESET (1 << 0)
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/* Flash Patch and Breakpoint Control Register (FP_CTRL) */
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/* Bits 32:15 - Reserved */
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/* Bits 14:12 - NUM_CODE2 */ /* v7m only */
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/* Bits 11:8 - NUM_LIT */ /* v7m only */
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/* Bits 7:4 - NUM_CODE1 */
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/* Bits 3:2 - Unspecified */
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#define CORTEXM_FPB_CTRL_KEY (1 << 1)
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#define CORTEXM_FPB_CTRL_ENABLE (1 << 0)
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/* Data Watchpoint and Trace Mask Register (DWT_MASKx) */
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#define CORTEXM_DWT_MASK_BYTE (0 << 0)
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#define CORTEXM_DWT_MASK_HALFWORD (1 << 0)
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#define CORTEXM_DWT_MASK_WORD (3 << 0)
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/* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */
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#define CORTEXM_DWT_FUNC_MATCHED (1 << 24)
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#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2 << 10) /* v7m only */
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#define CORTEXM_DWT_FUNC_FUNC_READ (5 << 0)
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#define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0)
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#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0)
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/* Signals returned by cortexm_halt_wait() */
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#define SIGINT 2
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#define SIGTRAP 5
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#define SIGSEGV 11
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static bool cortexm_attach(struct target_s *target);
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static void cortexm_detach(struct target_s *target);
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static int cortexm_regs_read(struct target_s *target, void *data);
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static int cortexm_regs_write(struct target_s *target, const void *data);
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static int cortexm_pc_write(struct target_s *target, const uint32_t val);
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static void cortexm_reset(struct target_s *target);
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static void cortexm_halt_resume(struct target_s *target, bool step);
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static int cortexm_halt_wait(struct target_s *target);
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static void cortexm_halt_request(struct target_s *target);
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static int cortexm_fault_unwind(struct target_s *target);
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@ -456,8 +333,7 @@ cortexm_attach(struct target_s *target)
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return true;
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}
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static void
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cortexm_detach(struct target_s *target)
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void cortexm_detach(struct target_s *target)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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struct cortexm_priv *priv = ap->priv;
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@ -646,14 +522,14 @@ cortexm_halt_wait(struct target_s *target)
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}
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static void
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cortexm_halt_resume(struct target_s *target, bool step)
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void cortexm_halt_resume(struct target_s *target, bool step)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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struct cortexm_priv *priv = ap->priv;
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uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN;
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if(step) dhcsr |= CORTEXM_DHCSR_C_STEP | CORTEXM_DHCSR_C_MASKINTS;
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if (step)
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dhcsr |= CORTEXM_DHCSR_C_STEP | CORTEXM_DHCSR_C_MASKINTS;
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/* Disable interrupts while single stepping... */
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if(step != priv->stepping) {
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@ -0,0 +1,130 @@
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#ifndef __CORTEXM_H
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#define __CORTEXM_H
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/* Private peripheral bus base address */
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#define CORTEXM_PPB_BASE 0xE0000000
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#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000)
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#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C)
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#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28)
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#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C)
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#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30)
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#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88)
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#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0)
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#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4)
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#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8)
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#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC)
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#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000)
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/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */
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#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000)
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#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004)
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#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i)))
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#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000)
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#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000)
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#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i)))
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#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i)))
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#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i)))
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/* Application Interrupt and Reset Control Register (AIRCR) */
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#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16)
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/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */
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#define CORTEXM_AIRCR_ENDIANESS (1 << 15)
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/* Bits 15:11 - Unused, reserved */
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#define CORTEXM_AIRCR_PRIGROUP (7 << 8)
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/* Bits 7:3 - Unused, reserved */
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#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2)
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#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1)
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#define CORTEXM_AIRCR_VECTRESET (1 << 0)
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/* HardFault Status Register (HFSR) */
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#define CORTEXM_HFSR_DEBUGEVT (1 << 31)
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#define CORTEXM_HFSR_FORCED (1 << 30)
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/* Bits 29:2 - Not specified */
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#define CORTEXM_HFSR_VECTTBL (1 << 1)
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/* Bits 0 - Reserved */
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/* Debug Fault Status Register (DFSR) */
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/* Bits 31:5 - Reserved */
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#define CORTEXM_DFSR_RESETALL 0x1F
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#define CORTEXM_DFSR_EXTERNAL (1 << 4)
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#define CORTEXM_DFSR_VCATCH (1 << 3)
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#define CORTEXM_DFSR_DWTTRAP (1 << 2)
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#define CORTEXM_DFSR_BKPT (1 << 1)
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#define CORTEXM_DFSR_HALTED (1 << 0)
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/* Debug Halting Control and Status Register (DHCSR) */
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/* This key must be written to bits 31:16 for write to take effect */
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#define CORTEXM_DHCSR_DBGKEY 0xA05F0000
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/* Bits 31:26 - Reserved */
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#define CORTEXM_DHCSR_S_RESET_ST (1 << 25)
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#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DHCSR_S_LOCKUP (1 << 19)
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#define CORTEXM_DHCSR_S_SLEEP (1 << 18)
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#define CORTEXM_DHCSR_S_HALT (1 << 17)
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#define CORTEXM_DHCSR_S_REGRDY (1 << 16)
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/* Bits 15:6 - Reserved */
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#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */
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/* Bit 4 - Reserved */
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#define CORTEXM_DHCSR_C_MASKINTS (1 << 3)
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#define CORTEXM_DHCSR_C_STEP (1 << 2)
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#define CORTEXM_DHCSR_C_HALT (1 << 1)
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#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0)
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/* Debug Core Register Selector Register (DCRSR) */
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#define CORTEXM_DCRSR_REGWnR 0x00010000
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#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001F
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#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010
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#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011
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#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012
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/* Debug Exception and Monitor Control Register (DEMCR) */
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/* Bits 31:25 - Reserved */
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#define CORTEXM_DEMCR_TRCENA (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DEMCR_MON_REQ (1 << 19) /* v7m only */
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#define CORTEXM_DEMCR_MON_STEP (1 << 18) /* v7m only */
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#define CORTEXM_DEMCR_VC_MON_PEND (1 << 17) /* v7m only */
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#define CORTEXM_DEMCR_VC_MON_EN (1 << 16) /* v7m only */
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/* Bits 15:11 - Reserved */
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#define CORTEXM_DEMCR_VC_HARDERR (1 << 10)
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#define CORTEXM_DEMCR_VC_INTERR (1 << 9) /* v7m only */
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#define CORTEXM_DEMCR_VC_BUSERR (1 << 8) /* v7m only */
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#define CORTEXM_DEMCR_VC_STATERR (1 << 7) /* v7m only */
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#define CORTEXM_DEMCR_VC_CHKERR (1 << 6) /* v7m only */
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#define CORTEXM_DEMCR_VC_NOCPERR (1 << 5) /* v7m only */
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#define CORTEXM_DEMCR_VC_MMERR (1 << 4) /* v7m only */
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/* Bits 3:1 - Reserved */
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#define CORTEXM_DEMCR_VC_CORERESET (1 << 0)
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/* Flash Patch and Breakpoint Control Register (FP_CTRL) */
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/* Bits 32:15 - Reserved */
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/* Bits 14:12 - NUM_CODE2 */ /* v7m only */
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/* Bits 11:8 - NUM_LIT */ /* v7m only */
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/* Bits 7:4 - NUM_CODE1 */
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/* Bits 3:2 - Unspecified */
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#define CORTEXM_FPB_CTRL_KEY (1 << 1)
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#define CORTEXM_FPB_CTRL_ENABLE (1 << 0)
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/* Data Watchpoint and Trace Mask Register (DWT_MASKx) */
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#define CORTEXM_DWT_MASK_BYTE (0 << 0)
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#define CORTEXM_DWT_MASK_HALFWORD (1 << 0)
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#define CORTEXM_DWT_MASK_WORD (3 << 0)
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/* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */
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#define CORTEXM_DWT_FUNC_MATCHED (1 << 24)
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#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2 << 10) /* v7m only */
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#define CORTEXM_DWT_FUNC_FUNC_READ (5 << 0)
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#define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0)
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#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0)
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void cortexm_detach(struct target_s *target);
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void cortexm_halt_resume(struct target_s *target, bool step);
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#endif
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133
src/samd20.c
133
src/samd20.c
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@ -39,6 +39,7 @@
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#include "target.h"
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#include "command.h"
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#include "gdb_packet.h"
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#include "cortexm.h"
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static int samd20_flash_erase(struct target_s *target, uint32_t addr, int len);
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static int samd20_flash_write(struct target_s *target, uint32_t dest,
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@ -145,104 +146,6 @@ static const char samd20_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* Component ID */
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#define SAMD20_CID_VALUE 0xB105100D
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#define CORTEXM_PPB_BASE 0xE0000000
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#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000)
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#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C)
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#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28)
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#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C)
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#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30)
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#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88)
|
||||
#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0)
|
||||
#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4)
|
||||
#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8)
|
||||
#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC)
|
||||
|
||||
/* Application Interrupt and Reset Control Register (AIRCR) */
|
||||
#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16)
|
||||
/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */
|
||||
#define CORTEXM_AIRCR_ENDIANESS (1 << 15)
|
||||
/* Bits 15:11 - Unused, reserved */
|
||||
#define CORTEXM_AIRCR_PRIGROUP (7 << 8)
|
||||
/* Bits 7:3 - Unused, reserved */
|
||||
#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2)
|
||||
#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1)
|
||||
#define CORTEXM_AIRCR_VECTRESET (1 << 0)
|
||||
|
||||
/* Debug Fault Status Register (DFSR) */
|
||||
/* Bits 31:5 - Reserved */
|
||||
#define CORTEXM_DFSR_RESETALL 0x1F
|
||||
#define CORTEXM_DFSR_EXTERNAL (1 << 4)
|
||||
#define CORTEXM_DFSR_VCATCH (1 << 3)
|
||||
#define CORTEXM_DFSR_DWTTRAP (1 << 2)
|
||||
#define CORTEXM_DFSR_BKPT (1 << 1)
|
||||
#define CORTEXM_DFSR_HALTED (1 << 0)
|
||||
|
||||
/* Debug Halting Control and Status Register (DHCSR) */
|
||||
/* This key must be written to bits 31:16 for write to take effect */
|
||||
#define CORTEXM_DHCSR_DBGKEY 0xA05F0000
|
||||
/* Bits 31:26 - Reserved */
|
||||
#define CORTEXM_DHCSR_S_RESET_ST (1 << 25)
|
||||
#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24)
|
||||
/* Bits 23:20 - Reserved */
|
||||
#define CORTEXM_DHCSR_S_LOCKUP (1 << 19)
|
||||
#define CORTEXM_DHCSR_S_SLEEP (1 << 18)
|
||||
#define CORTEXM_DHCSR_S_HALT (1 << 17)
|
||||
#define CORTEXM_DHCSR_S_REGRDY (1 << 16)
|
||||
/* Bits 15:6 - Reserved */
|
||||
#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */
|
||||
/* Bit 4 - Reserved */
|
||||
#define CORTEXM_DHCSR_C_MASKINTS (1 << 3)
|
||||
#define CORTEXM_DHCSR_C_STEP (1 << 2)
|
||||
#define CORTEXM_DHCSR_C_HALT (1 << 1)
|
||||
#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0)
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------------- */
|
||||
/* Cortex-M definitions for SAM D20 revision B fix */
|
||||
/* -------------------------------------------------------------------------- */
|
||||
|
||||
#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000)
|
||||
|
||||
/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */
|
||||
#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000)
|
||||
#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004)
|
||||
#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i)))
|
||||
|
||||
#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000)
|
||||
|
||||
#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000)
|
||||
#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i)))
|
||||
#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i)))
|
||||
#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i)))
|
||||
|
||||
#define CORTEXM_MAX_WATCHPOINTS 4 /* architecture says up to 15, no implementation has > 4 */
|
||||
#define CORTEXM_MAX_BREAKPOINTS 6 /* architecture says up to 127, no implementation has > 6 */
|
||||
|
||||
struct cortexm_priv {
|
||||
bool stepping;
|
||||
bool on_bkpt;
|
||||
/* Watchpoint unit status */
|
||||
struct wp_unit_s {
|
||||
uint32_t addr;
|
||||
uint8_t type;
|
||||
uint8_t size;
|
||||
} hw_watchpoint[CORTEXM_MAX_WATCHPOINTS];
|
||||
unsigned hw_watchpoint_max;
|
||||
/* Breakpoint unit status */
|
||||
uint32_t hw_breakpoint[CORTEXM_MAX_BREAKPOINTS];
|
||||
unsigned hw_breakpoint_max;
|
||||
/* Copy of DEMCR for vector-catch */
|
||||
uint32_t demcr;
|
||||
/* Semihosting state */
|
||||
uint32_t syscall;
|
||||
uint32_t errno;
|
||||
uint32_t byte_count;
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* Utility */
|
||||
#define MINIMUM(a,b) ((a < b) ? a : b)
|
||||
|
||||
|
|
@ -340,19 +243,7 @@ static void
|
|||
samd20_revB_detach(struct target_s *target)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(target);
|
||||
struct cortexm_priv *priv = ap->priv;
|
||||
unsigned i;
|
||||
|
||||
/* Clear any stale breakpoints */
|
||||
for(i = 0; i < priv->hw_breakpoint_max; i++)
|
||||
adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0);
|
||||
|
||||
/* Clear any stale watchpoints */
|
||||
for(i = 0; i < priv->hw_watchpoint_max; i++)
|
||||
adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0);
|
||||
|
||||
/* Disable debug */
|
||||
adiv5_ap_mem_write(ap, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
|
||||
cortexm_detach(target);
|
||||
|
||||
/* ---- Additional ---- */
|
||||
/* Exit extended reset */
|
||||
|
|
@ -374,25 +265,7 @@ static void
|
|||
samd20_revB_halt_resume(struct target_s *target, bool step)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(target);
|
||||
struct cortexm_priv *priv = ap->priv;
|
||||
uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN;
|
||||
|
||||
if(step) dhcsr |= CORTEXM_DHCSR_C_STEP | CORTEXM_DHCSR_C_MASKINTS;
|
||||
|
||||
/* Disable interrupts while single stepping... */
|
||||
if(step != priv->stepping) {
|
||||
adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT);
|
||||
priv->stepping = step;
|
||||
}
|
||||
|
||||
if (priv->on_bkpt) {
|
||||
uint32_t pc = target->pc_read(target);
|
||||
if ((adiv5_ap_mem_read_halfword(ap, pc) & 0xFF00) == 0xBE00)
|
||||
target->pc_write(target, pc + 2);
|
||||
}
|
||||
|
||||
adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr);
|
||||
ap->dp->allow_timeout = true;
|
||||
cortexm_halt_resume(target, step);
|
||||
|
||||
/* ---- Additional ---- */
|
||||
/* Exit extended reset */
|
||||
|
|
|
|||
Loading…
Reference in New Issue