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adiv5: Activate DP reset sequence, guarded with timeouts. 

While not working on most STM32, it succeeds on STM32G474.
Thanks to Dave Marples <dave@marples.net>
This commit is contained in:
Uwe Bonnes 2019-10-20 15:55:21 +02:00 committed by UweBonnes
parent c6f43cf23f
commit b9249fe104
1 changed files with 25 additions and 22 deletions
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25
src/target/adiv5.c
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@ -30,10 +30,6 @@
#include "cortexm.h" #include "cortexm.h"
#include "exception.h" #include "exception.h"
#ifndef DO_RESET_SEQ
#define DO_RESET_SEQ 0
#endif
/* All this should probably be defined in a dedicated ADIV5 header, so that they /* All this should probably be defined in a dedicated ADIV5 header, so that they
* are consistently named and accessible when needed in the codebase. * are consistently named and accessible when needed in the codebase.
*/ */
@ -455,26 +451,33 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
(ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK)) != (ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK)) !=
(ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK)); (ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK));
if(DO_RESET_SEQ) {
/* This AP reset logic is described in ADIv5, but fails to work /* This AP reset logic is described in ADIv5, but fails to work
* correctly on STM32. CDBGRSTACK is never asserted, and we * correctly on STM32. CDBGRSTACK is never asserted, and we
* just wait forever. * just wait forever. This scenario is described in B2.4.1
* so we have a timeout mechanism in addition to the sensing one.
*/ */
/* Write request for debug reset */ /* Write request for debug reset */
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT,
ctrlstat |= ADIV5_DP_CTRLSTAT_CDBGRSTREQ); ctrlstat |= ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
platform_timeout timeout;
platform_timeout_set(&timeout,200);
/* Wait for acknowledge */ /* Wait for acknowledge */
while(!((ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT)) & while ((!platform_timeout_is_expired(&timeout)) &&
ADIV5_DP_CTRLSTAT_CDBGRSTACK)); (!((ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT)) & ADIV5_DP_CTRLSTAT_CDBGRSTACK))
);
/* Write request for debug reset release */ /* Write request for debug reset release */
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT,
ctrlstat &= ~ADIV5_DP_CTRLSTAT_CDBGRSTREQ); ctrlstat &= ~ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
platform_timeout_set(&timeout,200);
/* Wait for acknowledge */ /* Wait for acknowledge */
while(adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) & while ((!platform_timeout_is_expired(&timeout)) &&
ADIV5_DP_CTRLSTAT_CDBGRSTACK); (adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) & ADIV5_DP_CTRLSTAT_CDBGRSTACK)
} );
DEBUG("RESET_SEQ %s\n", (platform_timeout_is_expired(&timeout)) ? "failed": "succeeded");
dp->dp_idcode = adiv5_dp_read(dp, ADIV5_DP_IDCODE); dp->dp_idcode = adiv5_dp_read(dp, ADIV5_DP_IDCODE);
if ((dp->dp_idcode & ADIV5_DP_VERSION_MASK) == ADIV5_DPv2) { if ((dp->dp_idcode & ADIV5_DP_VERSION_MASK) == ADIV5_DPv2) {