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cortexa: Disable AHB memory access to avoid issues with L2 cache.

This commit is contained in:
Gareth McMullin 2016-10-26 18:27:35 -07:00
parent 3b7edc325d
commit bcf3caf20e
1 changed files with 5 additions and 1 deletions
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6
src/target/cortexa.c
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@ -359,7 +359,11 @@ bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base)
* device specific. */ * device specific. */
priv->ahb = adiv5_new_ap(apb->dp, 0); priv->ahb = adiv5_new_ap(apb->dp, 0);
adiv5_ap_ref(priv->ahb); adiv5_ap_ref(priv->ahb);
if ((priv->ahb->idr & 0xfffe00f) == 0x4770001) { if (false) {
/* FIXME: This used to be if ((priv->ahb->idr & 0xfffe00f) == 0x4770001)
* Accessing memory directly through the AHB is much faster, but can
* result in data inconsistencies if the L2 cache is enabled.
*/
/* This is an AHB */ /* This is an AHB */
t->mem_read = cortexa_mem_read; t->mem_read = cortexa_mem_read;
t->mem_write = cortexa_mem_write; t->mem_write = cortexa_mem_write;