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Export function to read out PIDR and use for samd and samx5x.

This commit is contained in:
Uwe Bonnes 2020-03-08 13:08:54 +01:00 committed by UweBonnes
parent a0e42e229b
commit c4d7232223
4 changed files with 32 additions and 79 deletions
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40
src/target/adiv5.c
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@ -210,6 +210,7 @@ static const struct {
{0xc09, aa_cortexa, cidc_dc, PIDR_PN_BIT_STRINGS("Cortex-A9 Debug", "(Debug Unit)")},
{0xc0f, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 Debug", "(Debug Unit)")}, /* support? */
{0xc14, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-R4 Debug", "(Debug Unit)")}, /* support? */
{0xcd0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Atmel DSU", "(Device Service Unit)")},
{0xd21, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M33", "()")}, /* support? */
{0xfff, aa_end, cidc_unknown, PIDR_PN_BIT_STRINGS("end", "end")}
};
@ -252,12 +253,29 @@ static uint32_t adiv5_mem_read32(ADIv5_AP_t *ap, uint32_t addr)
return ret;
}
static uint32_t adiv5_ap_read_id(ADIv5_AP_t *ap, uint32_t addr)
{
uint32_t res = 0;
for (int i = 0; i < 4; i++) {
uint32_t x = adiv5_mem_read32(ap, addr + 4 * i);
res |= (x & 0xff) << (i * 8);
}
return res;
}
uint64_t adiv5_ap_read_pidr(ADIv5_AP_t *ap, uint32_t addr)
{
uint64_t pidr = adiv5_ap_read_id(ap, addr + PIDR4_OFFSET);
pidr = pidr << 32 | adiv5_ap_read_id(ap, addr + PIDR0_OFFSET);
return pidr;
}
static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion, int num_entry)
{
(void) num_entry;
addr &= ~3;
uint64_t pidr = 0;
uint32_t cidr = 0;
uint64_t pidr = adiv5_ap_read_pidr(ap, addr);
uint32_t cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET);
bool res = false;
#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
char indent[recursion + 1];
@ -266,22 +284,6 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
indent[recursion] = 0;
#endif
/* Assemble logical Product ID register value. */
for (int i = 0; i < 4; i++) {
uint32_t x = adiv5_mem_read32(ap, addr + PIDR0_OFFSET + 4*i);
pidr |= (x & 0xff) << (i * 8);
}
{
uint32_t x = adiv5_mem_read32(ap, addr + PIDR4_OFFSET);
pidr |= (uint64_t)x << 32;
}
/* Assemble logical Component ID register value. */
for (int i = 0; i < 4; i++) {
uint32_t x = adiv5_mem_read32(ap, addr + CIDR0_OFFSET + 4*i);
cidr |= ((uint64_t)(x & 0xff)) << (i * 8);
}
if (adiv5_dp_error(ap->dp)) {
DEBUG("%sFault reading ID registers\n", indent);
return false;
@ -376,7 +378,7 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
cortexm_probe(ap, false);
break;
case aa_cortexa:
DEBUG("%s-> cortexa_probe\n", indent + 1);
DEBUG("\n -> cortexa_probe\n");
cortexa_probe(ap, addr);
break;
default:

2
src/target/adiv5.h
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@ -198,5 +198,5 @@ void adiv5_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len);
void adiv5_mem_write(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len);
void adiv5_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src,
size_t len, enum align align);
uint64_t adiv5_ap_read_pidr(ADIv5_AP_t *ap, uint32_t addr);
#endif

40
src/target/samd.c
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@ -113,10 +113,8 @@ const struct command_s samd_cmd_list[] = {
#define SAMD_DSU_ADDRESS (SAMD_DSU_EXT_ACCESS + 0x4)
#define SAMD_DSU_LENGTH (SAMD_DSU_EXT_ACCESS + 0x8)
#define SAMD_DSU_DID (SAMD_DSU_EXT_ACCESS + 0x018)
#define SAMD_DSU_PID(n) (SAMD_DSU + 0x1FE0 + \
(0x4 * (n % 4)) - (0x10 * (n / 4)))
#define SAMD_DSU_CID(n) (SAMD_DSU + 0x1FF0 + \
(0x4 * (n % 4)))
#define SAMD_DSU_PID (SAMD_DSU + 0x1000)
#define SAMD_DSU_CID (SAMD_DSU + 0x1010)
/* Control and Status Register (CTRLSTAT) */
#define SAMD_CTRL_CHIP_ERASE (1 << 4)
@ -221,35 +219,6 @@ static const struct samd_part samd_l22_parts[] = {
{0xFF, 0, 0, 0}
};
/**
* Reads the SAM D20 Peripheral ID
*/
uint64_t samd_read_pid(target *t)
{
uint64_t pid = 0;
uint8_t i, j;
/* Five PID registers to read LSB first */
for (i = 0, j = 0; i < 5; i++, j += 8)
pid |= (target_mem_read32(t, SAMD_DSU_PID(i)) & 0xFF) << j;
return pid;
}
/**
* Reads the SAM D20 Component ID
*/
uint32_t samd_read_cid(target *t)
{
uint64_t cid = 0;
uint8_t i, j;
/* Four CID registers to read LSB first */
for (i = 0, j = 0; i < 4; i++, j += 8)
cid |= (target_mem_read32(t, SAMD_DSU_CID(i)) & 0xFF) << j;
return cid;
}
/**
* Overloads the default cortexm reset function with a version that
* removes the target from extended reset where required.
@ -474,8 +443,9 @@ static void samd_add_flash(target *t, uint32_t addr, size_t length)
char variant_string[60];
bool samd_probe(target *t)
{
uint32_t cid = samd_read_cid(t);
uint32_t pid = samd_read_pid(t);
ADIv5_AP_t *ap = cortexm_ap(t);
uint32_t cid = adiv5_ap_read_pidr(ap, SAMD_DSU_CID);
uint32_t pid = adiv5_ap_read_pidr(ap, SAMD_DSU_PID);
/* Check the ARM Coresight Component and Perhiperal IDs */
if ((cid != SAMD_CID_VALUE) ||

29
src/target/samx5x.c
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@ -169,11 +169,8 @@ const struct command_s samx5x_protected_cmd_list[] = {
#define SAMX5X_DSU_LENGTH (SAMX5X_DSU_EXT_ACCESS + 0x08)
#define SAMX5X_DSU_DATA (SAMX5X_DSU_EXT_ACCESS + 0x0C)
#define SAMX5X_DSU_DID (SAMX5X_DSU_EXT_ACCESS + 0x18)
#define SAMX5X_DSU_PID(n) (SAMX5X_DSU + 0x1FE0 + \
(0x4 * (n % 4)) - \
(0x10 * (n / 4)))
#define SAMX5X_DSU_CID(n) (SAMX5X_DSU + 0x1FF0 + \
(0x4 * (n % 4)))
#define SAMX5X_DSU_PID (SAMX5X_DSU + 0x1000)
#define SAMX5X_DSU_CID (SAMX5X_DSU + 0x1010)
/* Control and Status Register (CTRLSTAT) */
#define SAMX5X_CTRL_CHIP_ERASE (1 << 4)
@ -219,23 +216,6 @@ const struct command_s samx5x_protected_cmd_list[] = {
/* Component ID */
#define SAMX5X_CID_VALUE 0xB105100D
/**
* Reads the SAM D5x/E5x Peripheral ID
*
* (Reuses the SAM D1x/2x implementation as it is identical)
*/
extern uint64_t samd_read_pid(target *t);
#define samx5x_read_pid samd_read_pid
/**
* Reads the SAM D5x/E5x Component ID
*
* (Reuses the SAM D1x/2x implementation as it is identical)
*/
extern uint32_t samd_read_cid(target *t);
#define samx5x_read_cid samd_read_cid
/**
* Overloads the default cortexm reset function with a version that
* removes the target from extended reset where required.
@ -367,8 +347,9 @@ static void samx5x_add_flash(target *t, uint32_t addr, size_t length,
char variant_string[60];
bool samx5x_probe(target *t)
{
uint32_t cid = samx5x_read_cid(t);
uint32_t pid = samx5x_read_pid(t);
ADIv5_AP_t *ap = cortexm_ap(t);
uint32_t cid = adiv5_ap_read_pidr(ap, SAMX5X_DSU_CID);
uint32_t pid = adiv5_ap_read_pidr(ap, SAMX5X_DSU_PID);
/* Check the ARM Coresight Component and Perhiperal IDs */
if ((cid != SAMX5X_CID_VALUE) ||