swlink: Enable UART2 for SWO.
Stlink on STM8S-Disco needs additional wiring for SWO.
This commit is contained in:
Uwe Bonnes
Gareth McMullin
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UsingSWO
27
UsingSWO
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@ -25,13 +25,13 @@ the it is a pretty long run before it becomes a problem).
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Note that the baudrate equation means there are only certain speeds
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available. The highest half dozen are;
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1 4.50 Mbps
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2 2.25 Mbps
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3 1.50 Mbps
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4 1.125 Mbps
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5 0.900 Mbps
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6 0.750 Mbps
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SWO uses USART1(stlink) USART2(swlink)
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1 4.50 Mbps 2.25 Mbps
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2 2.25 Mbps 1.125 Mbps
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3 1.50 Mbps 0.75 Mbps
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4 1.125 Mbps 0.5635 Mbps
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5 0.900 Mbps 0.45 Mbps
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6 0.750 Mbps 0.375 Mbps
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...the USART will cope with some timing slip, but it's advisible to stay as
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close to these values as you can. As the speed comes down the spread between
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@ -50,13 +50,14 @@ An example for a STM32F103 for the UART (NRZ) data format that we use;
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AFIO->MAPR |= (2 << 24); // Disable JTAG to release TRACESWO
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DBGMCU->CR |= DBGMCU_CR_TRACE_IOEN; // Enable IO trace pins
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*((volatile unsigned *)(0xE0040010)) = 31; // Output bits at 72000000/(31+1)=2.25MHz.
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*((volatile unsigned *)(0xE00400F0)) = 2; // Use Async mode (1 for RZ/Manchester)
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*((volatile unsigned *)(0xE0040304)) = 0; // Disable formatter
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TPI->ACPR = 31; // Output bits at 72000000/(31+1)=2.25MHz.
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TPI->SPPR = 2; // Use Async mode (1 for RZ/Manchester)
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TPI-FFCR = 0; // Disable formatter
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/* Configure instrumentation trace macroblock */
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ITM->LAR = 0xC5ACCE55;
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ITM->TCR = 0x00010005;
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ITM->TCR = 1 << ITM_TCR_TraceBusID_Pos | ITM_TCR_SYNCENA_Msk |
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ITM_TCR_ITMENA_Msk;
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ITM->TER = 0xFFFFFFFF; // Enable all stimulus ports
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Code for the STM32L476 might look like:
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@ -234,7 +235,7 @@ can pick this up. Success has been had with CP2102 dongles at up to 921600
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baud.
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To use this mode just connect SWO to the RX pin of your dongle, and start
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swolisten with parmeters representing the speed and port. An example;
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swolisten with parameters representing the speed and port. An example;
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>./swolisten -p /dev/cu.SLAB_USBtoUART -v -b swo/ -s 921600
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@ -251,4 +252,4 @@ Further information
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SWO is a wide field. Read e.g. the blogs around SWD on
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http://shadetail.com/blog/swo-starting-the-steroids/
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An open source program suite for SWO under active development is
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https://github.com/mubes/orbuculum
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https://github.com/mubes/orbuculum
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@ -26,6 +26,7 @@ SRC += cdcacm.c \
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serialno.c \
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timing.c \
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timing_stm32.c \
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traceswoasync.c \
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platform_common.c \
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all: blackmagic.bin blackmagic_dfu.bin blackmagic_dfu.hex dfu_upgrade.bin dfu_upgrade.hex
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@ -0,0 +1,72 @@
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# Blackmagic for STM8S Discovery and STM32F103 Minimum System Development Board
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## External connections:
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| Function | PIN | STM8S-DISCO | BLUEPILL |
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| ----------- | ----- | ----------- | ----------- |
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| JTMS/SWDIO | PA13 | CN5/5 | P2/2 |
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| JTCK/SWCLK | PA14 | CN5/4 | P2/3 |
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| JTDI | PA15 | CN5/6 | P4/11 (38) |
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| JTDO | PB3 | CN5/3 | P4/10 (39) |
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| SRST | PB4 | CN5/8 | P4/9 (40) |
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| UART1_TX | PB6 | CN7/4 | P4/7 (42) |
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| UART1_RX | PB7 | CN7/2 | P4/6 (43) |
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| SWO/RX2 | PA3 | NA(*1) | P3/7 (13) |
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*1: Wire JTDO/PB3 (U2/39) to USART2_RX/PA3 (U2/13) to expose SWO for Stlink
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on STM8S-Disco on CN5/3
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### Force Bootloader Entry:
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STM8S Discovery: Jumper CN7/4 to CN7/3 to read PB6 low.
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Bluepill: Jumper Boot1 to '1' to read PB2 high.
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### References:
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[STM8S UM0817 User manual
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](https://www.st.com/resource/en/user_manual/cd00250600.pdf)
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[Blue Pill Schematics 1
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](https://jeelabs.org/img/2016/STM32F103C8T6-DEV-BOARD-SCH.pdf) :
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Use first number!
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[Blue Pill Schematics 2
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](https://wiki.stm32duino.com/images/a/ae/Bluepillpinout.gif) :
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Use second number!
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Distinguish boards by checking the SWIM_IN connection PB9/PB10 seen on
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STM8S Discovery.
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## STM8S Discovery
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The board is a ST-Link V1 Board, but with access to JTAG pins accessible
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on CN5. This allows easy reprogramming and reuse of the JTAG header.
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Programmatical it seems indistinguishable from a e.g. STM32VL
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Discovery. So here a variant that uses CN5 for JTAG/SWD and CN7 for
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UART.
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Force Bootloader entry is done with shorting CN7 Pin3/4 so PB6 read low while
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pulled up momentary by PB6. As PB6 is USBUART TX, this pin is idle
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high. Setting the jumper while BMP is running means shorting the GPIO with
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output high to ground. Do not do that for extended periods. Un- and repower
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soon after setting the jump. Best is to short only when unplugged.
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Reuse SWIM Pins for Uart (USART1)
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RX: CN7 Pin2 ->SWIM_IN (PB7)/USART1_RX / SWIM_IN(PB9)
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TX: CN7 Pin4 -> SWIM_RST_IN(PB6)/USART1_TX
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## STM32F103 Minimum System Development Board (aka Blue Pill)
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This board has the SWD pins of the onboard F103 accessible on one side.
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Reuse these pins. There are also jumpers for BOOT0 and BOOT1(PB2). Reuse
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Boot1 as "Force Bootloader entry" jumpered high when booting. Boot1
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has 100 k Ohm between MCU and header pin and can not be used as output.
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All other port pins are have header access with headers not yet soldered.
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This platform can be used for any STM32F103x[8|B] board when JTAG/SWD are
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accessible, with the LED depending on actual board layout routed to some
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wrong pin and force boot not working.
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## Other STM32F103x[8|B] boards
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If the needed JTAG connections are accessible, you can use this swlink variant.
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Depending on board layout, LED and force bootloader entry may be routed to
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wrong pins.
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@ -1,49 +0,0 @@
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Blackmagic for STM8S Discovery and STM32F103 Minimum System Development Board
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=============================================================================
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* External connections:
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Function PIN STM8S-DISCO BLUPILL
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JTMS/SWDIO PA13 CN5/5 P2/2
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TTCK/SWCLK PA14 CN5/4 P2/3
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JTDI PA15 CN5/6 P4/11 (38)
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JTDO PB3 CN5/3 P4/10 (39)
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SRST PB4 CN5/8 P4/9 (40)
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UART1_TX PB6 CN7/4 P4/7 (42)
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UART1_RX PB7 CN7/2 P4/6 (43)
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References:
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https://www.st.com/resource/en/user_manual/cd00250600.pdf
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Blue Pill:
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https://jeelabs.org/img/2016/STM32F103C8T6-DEV-BOARD-SCH.pdf (first number)
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https://wiki.stm32duino.com/images/a/ae/Bluepillpinout.gif (second number)
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* STM8S Discovery
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The board is a ST-Link V1 Board, but with access to JTAG pins accessible
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on CN5. This allows easy reprogramming and reuse of the JTAG header.
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Programmatical it seems indistinguishable from a e.g. STM32VL
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Discovery. So here a variant that uses CN5 for JTAG/SWD and CN7 for
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UART.
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Force Bootloader entry is done with shorting CN7 Pin3/4 so PB6 read low while
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pulled up momentary by PB6.
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Reuse SWIM Pins for Uart (USART1)
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RX: CN7 Pin2 ->SWIM_IN (PB7)/USART1_RX / SWIM_IN(PB9)
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TX: CN7 Pin4 -> SWIM_RST_IN(PB6)/USART1_TX
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* STM32F103 Minimum System Development Board (aka Blue Pill)
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This board has the SWD pins of the onboard F103 accessible on one side.
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Reuse these pins. There are also jumpers for BOOT0 and BOOT1(PB2). Reuse
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Boot1 as "Force Bootloader entry" jumpered high when connecting to USB. Boot1
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has 100 k Ohm between MCU and header pin and can not be used as SRST.
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All other port pins are have header access with headers not yet soldered.
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JTAG TDO: PB3
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JTAG TDI: PA15
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SWD SWO: PA10 (use Uart pin as on normal STLINK)
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Distinguish boards by checking the SWIM_IN connection PB9/PB10
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@ -62,6 +62,9 @@
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#define LED_PORT_UART GPIOC
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#define LED_UART GPIO14
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#define PLATFORM_HAS_TRACESWO 1
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#define NUM_TRACE_PACKETS (128) /* This is an 8K buffer */
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# define SWD_CR GPIO_CRH(SWDIO_PORT)
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# define SWD_CR_MULT (1 << ((13 - 8) << 2))
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@ -97,7 +100,7 @@
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#define IRQ_PRI_USBUSART (1 << 4)
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#define IRQ_PRI_USBUSART_TIM (3 << 4)
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#define IRQ_PRI_USB_VBUS (14 << 4)
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#define IRQ_PRI_TRACE (0 << 4)
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#define IRQ_PRI_SWO_DMA (0 << 4)
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#define USBUSART USART1
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#define USBUSART_CR1 USART1_CR1
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@ -126,6 +129,21 @@ int usbuart_debug_write(const char *buf, size_t len);
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# define DEBUG(...)
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#endif
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/* On F103, only USART1 is on AHB2 and can reach 4.5 MBaud at 72 MHz.
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* USART1 is already used. sp maximum speed is 2.25 MBaud. */
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#define SWO_UART USART2
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#define SWO_UART_DR USART2_DR
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#define SWO_UART_CLK RCC_USART2
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#define SWO_UART_PORT GPIOA
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#define SWO_UART_RX_PIN GPIO3
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/* This DMA channel is set by the USART in use */
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#define SWO_DMA_BUS DMA1
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#define SWO_DMA_CLK RCC_DMA1
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#define SWO_DMA_CHAN DMA_CHANNEL6
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#define SWO_DMA_IRQ NVIC_DMA1_CHANNEL6_IRQ
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#define SWO_DMA_ISR(x) dma1_channel6_isr(x)
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#define LED_PORT GPIOC
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#define LED_IDLE_RUN GPIO15
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#define SET_RUN_STATE(state)
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