Remove unfinished ARM7TDMI driver.
This commit is contained in:
Gareth McMullin
parent
64c79e1d03
commit
d9af3cca6c
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@ -20,7 +20,6 @@ SRC = \
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adiv5.c \
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adiv5_jtagdp.c \
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adiv5_swdp.c \
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arm7tdmi.c \
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command.c \
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cortexm.c \
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crc32.c \
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291
src/arm7tdmi.c
291
src/arm7tdmi.c
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@ -1,291 +0,0 @@
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/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2011 Black Sphere Technologies Ltd.
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* Written by Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements the ARM7TDMI target support using the JTAG
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* interface as described in ARM7TDMI Technical Reference Manual,
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* ARM Document DDI 0210C
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*/
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#include "general.h"
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#include "target.h"
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#include "jtag_scan.h"
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#include "jtagtap.h"
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/* TODO:
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* Skeleton target.
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* EmbeddedICE registers, halt/resume target.
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* Check target mode on halt, switch to ARM if needed.
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* Read registers on halt, restore on resume. Give GDB cached copy.
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* System speed access, read/write memory.
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* Misaligned/byte memory access.
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* Breakpoint support.
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* Watchpoint support.
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* Funnies: abort on breakpointed instruction, etc.
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* Flash programming for STR73x and LPC2xxx.
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*/
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static const char arm7_driver_str[] = "ARM7TDMI";
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/* ARM7 JTAG IR values */
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#define ARM7_IR_EXTEST 0x0
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#define ARM7_IR_SCAN_N 0x2
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#define ARM7_IR_SAMPLE_PRELOAD 0x3
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#define ARM7_IR_RESTART 0x4
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#define ARM7_IR_CLAMP 0x5
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#define ARM7_IR_HIGHZ 0x7
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#define ARM7_IR_CLAMPZ 0x9
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#define ARM7_IR_INTEST 0xC
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#define ARM7_IR_IDCODE 0xE
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#define ARM7_IR_BYPASS 0xF
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/* ARM7 SCAN_N scan chain values */
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#define ARM7_SCANN_BOUNDARY 0
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#define ARM7_SCANN_DBUS 1
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#define ARM7_SCANN_EICE 2
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/* EmbeddedICE-RT Register addresses */
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#define ARM7_EICE_DEBUG_CTRL 0x00
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#define ARM7_EICE_DEBUG_STAT 0x01
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#define ARM7_EICE_ABORT_STAT 0x02
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#define ARM7_EICE_COMMS_CTRL 0x04
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#define ARM7_EICE_COMMS_DATA 0x05
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#define ARM7_EICE_WATCH_ADDR(x) (0x08 + (8 * (x))
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#define ARM7_EICE_WATCH_ADDR_MASK(x) (0x09 + (8 * (x))
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#define ARM7_EICE_WATCH_DATA(x) (0x0A + (8 * (x))
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#define ARM7_EICE_WATCH_DATA_MASK(x) (0x0B + (8 * (x))
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#define ARM7_EICE_WATCH_CTRL(x) (0x0C + (8 * (x))
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#define ARM7_EICE_WATCH_CTRL_MASK(x) (0x0D + (8 * (x))
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/* Read/write bit in EmbeddedICE-RT scan chain */
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#define ARM7_EICE_READ (0uLL << 37)
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#define ARM7_EICE_WRITE (1uLL << 37)
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/* Debug Control Register bits */
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#define ARM7_EICE_DEBUG_CTRL_EICE_DISABLE (1 << 5)
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#define ARM7_EICE_DEBUG_CTRL_MONITOR (1 << 4)
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/* Bit 3 - Reserved */
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#define ARM7_EICE_DEBUG_CTRL_INTDIS (1 << 2)
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#define ARM7_EICE_DEBUG_CTRL_DBGRQ (1 << 1)
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#define ARM7_EICE_DEBUG_CTRL_DBGACK (1 << 0)
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/* Debug Status Register bits */
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#define ARM7_EICE_DEBUG_STAT_TBIT (1 << 4)
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#define ARM7_EICE_DEBUG_STAT_NMREQ (1 << 3)
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#define ARM7_EICE_DEBUG_STAT_INTDIS (1 << 2)
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#define ARM7_EICE_DEBUG_STAT_DBGRQ (1 << 1)
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#define ARM7_EICE_DEBUG_STAT_DBGACK (1 << 0)
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#define ARM7_OP_NOP 0xE1A00000
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struct target_arm7_s {
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target t;
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jtag_dev_t *jtag;
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uint32_t reg_cache[16];
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};
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/* FIXME: Remove: */
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static void do_nothing(void)
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{
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}
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static bool arm7_attach(struct target_s *target);
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static int arm7_regs_read(struct target_s *target, void *data);
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static int arm7_regs_write(struct target_s *target, const void *data);
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static void arm7_halt_request(struct target_s *target);
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static int arm7_halt_wait(struct target_s *target);
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static void arm7_halt_resume(struct target_s *target, bool step);
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void arm7tdmi_jtag_handler(jtag_dev_t *dev)
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{
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struct target_arm7_s *tj = (void*)target_new(sizeof(*tj));
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target *t = (target *)tj;
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t->driver = arm7_driver_str;
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tj->jtag = dev;
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/* Setup mandatory virtual methods */
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t->attach = arm7_attach;
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t->detach = (void *)do_nothing;
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t->check_error = (void *)do_nothing;
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t->mem_read = (void *)do_nothing;
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t->mem_write = (void *)do_nothing;
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t->regs_size = 16 * sizeof(uint32_t);
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t->regs_read = (void *)arm7_regs_read;
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t->regs_write = (void *)arm7_regs_write;
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t->pc_write = (void *)do_nothing;
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t->reset = (void *)do_nothing;
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t->halt_request = arm7_halt_request;
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t->halt_wait = arm7_halt_wait;
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t->halt_resume = arm7_halt_resume;
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/* TODO: Breakpoint and watchpoint functions. */
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/* TODO: Fault unwinder. */
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/* TODO: Memory map / Flash programming. */
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}
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static void arm7_select_scanchain(struct target_arm7_s *target, uint8_t chain)
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{
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jtag_dev_write_ir(target->jtag, ARM7_IR_SCAN_N);
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jtag_dev_shift_dr(target->jtag, NULL, &chain, 4);
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jtag_dev_write_ir(target->jtag, ARM7_IR_INTEST);
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}
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static void arm7_eice_write(struct target_arm7_s *target,
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uint8_t addr, uint32_t value)
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{
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uint64_t val = ((uint64_t)addr << 32) | value | ARM7_EICE_WRITE;
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arm7_select_scanchain(target, ARM7_SCANN_EICE);
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jtag_dev_shift_dr(target->jtag, NULL, (uint8_t *)&val, 38);
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DEBUG("eice_write(%d, 0x%08X)\n", addr, value);
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}
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static uint32_t arm7_eice_read(struct target_arm7_s *target, uint8_t addr)
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{
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uint64_t val = ((uint64_t)addr << 32) | ARM7_EICE_READ;
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arm7_select_scanchain(target, ARM7_SCANN_EICE);
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jtag_dev_shift_dr(target->jtag, NULL, (uint8_t *)&val, 38);
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jtag_dev_shift_dr(target->jtag, (uint8_t *)&val, (uint8_t *)&val, 38);
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DEBUG("eice_read(%d, 0x%08X)\n", addr, (uint32_t)val);
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return (uint32_t)val;
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}
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/* Execute a single instruction at debug speed.
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* Performs datalen data bus accesses after the op to capture data.
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*/
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static void arm7_op_debug(struct target_arm7_s *t, uint32_t op, uint32_t *data,
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int datalen)
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{
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uint64_t tmp;
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/* FIXME: This routine is broken.
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* This process isn't very well documented. Maybe NOPs need to
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* be shifted into pipeline before data is read out.
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*/
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DEBUG("op_debug(0x%08X)\n", op);
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arm7_select_scanchain(t, ARM7_SCANN_DBUS);
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tmp = op;
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jtag_dev_shift_dr(t->jtag, NULL, (const uint8_t*)&tmp, 33);
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while(datalen--) {
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tmp = *data;
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jtag_dev_shift_dr(t->jtag, (uint8_t*)&tmp, (uint8_t*)&tmp, 33);
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*data = (uint32_t)tmp;
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DEBUG("\t0x%08X\n", *data);
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data++;
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}
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}
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/* Execute a single instruction at system speed. */
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static void arm7_op_system(struct target_arm7_s *t, uint32_t op)
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{
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uint64_t tmp;
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arm7_select_scanchain(t, ARM7_SCANN_DBUS);
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tmp = op | (1uLL << 32);
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jtag_dev_shift_dr(t->jtag, NULL, (const uint8_t*)&tmp, 33);
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}
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static void arm7_halt_request(struct target_s *target)
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{
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struct target_arm7_s *t = (struct target_arm7_s *)target;
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arm7_eice_write(t, ARM7_EICE_DEBUG_CTRL, ARM7_EICE_DEBUG_CTRL_DBGRQ);
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}
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static int arm7_halt_wait(struct target_s *target)
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{
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struct target_arm7_s *t = (struct target_arm7_s *)target;
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int stat = arm7_eice_read(t, ARM7_EICE_DEBUG_STAT);
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if(!(stat & ARM7_EICE_DEBUG_STAT_DBGACK))
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return 0;
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/* We are halted, so switch to ARM mode if needed. */
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if(stat & ARM7_EICE_DEBUG_STAT_TBIT) {
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/* This sequence switches to ARM mode:
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* 6000 STR R0, [R0] ; Save R0 before use
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* 4678 MOV R0, PC ; Copy PC into R0
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* 6000 STR R0, [R0] ; Now save the PC in R0
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* 4778 BX PC ; Jump into ARM state
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* 46c0 MOV R8, R8 ; NOP
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* 46c0 MOV R8, R8 ; NOP
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*/
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/* FIXME: Switch to ARM mode. */
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}
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/* Fetch core register values */
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/* E880FFFF STM R0, {R0-R15} */
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arm7_op_debug(t, 0xE880FFFF, t->reg_cache, 16);
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return 1;
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}
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static void arm7_halt_resume(struct target_s *target, bool step)
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{
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struct target_arm7_s *t = (struct target_arm7_s *)target;
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if(step) {
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/* FIXME: Set breakpoint on any instruction to single step. */
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}
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/* Restore core registers. */
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/* E890FFFF LDM R0, {R0-R15} */
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arm7_op_debug(t, 0xE890FFFF, t->reg_cache, 16);
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/* Release DBGRQ */
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arm7_eice_write(t, ARM7_EICE_DEBUG_CTRL, 0);
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/* This sequence restores PC if no other instructions issued in
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* debug mode...
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* 0 E1A00000; MOV R0, R0
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* 1 E1A00000; MOV R0, R0
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* 0 EAFFFFFA; B -6
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* FIXME: Add adjustment for other opcodes.
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*/
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arm7_op_debug(t, ARM7_OP_NOP, NULL, 0);
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arm7_op_system(t, ARM7_OP_NOP);
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arm7_op_debug(t, 0xEAFFFFF8, NULL, 0);
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jtag_dev_write_ir(t->jtag, ARM7_IR_RESTART);
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}
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static bool arm7_attach(struct target_s *target)
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{
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int tries = 0;
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target_halt_request(target);
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while(!target_halt_wait(target) && --tries)
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platform_delay(2);
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if(!tries)
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return false;
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return true;
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}
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static int arm7_regs_read(struct target_s *target, void *data)
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{
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struct target_arm7_s *t = (struct target_arm7_s *)target;
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memcpy(data, t->reg_cache, target->regs_size);
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return 0;
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}
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static int arm7_regs_write(struct target_s *target, const void *data)
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{
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struct target_arm7_s *t = (struct target_arm7_s *)target;
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memcpy(t->reg_cache, data, target->regs_size);
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return 0;
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}
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@ -43,9 +43,6 @@ static struct jtag_dev_descr_s {
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{.idcode = 0x0BA00477, .idmask = 0x0FFF0FFF,
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.descr = "ARM Limited: ADIv5 JTAG-DP port.",
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.handler = adiv5_jtag_dp_handler},
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{.idcode = 0x3F0F0F0F, .idmask = 0xFFFFFFFF,
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.descr = "ST Microelectronics: STR730",
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.handler = arm7tdmi_jtag_handler},
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{.idcode = 0x06410041, .idmask = 0x0FFFFFFF,
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.descr = "ST Microelectronics: STM32, Medium density."},
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{.idcode = 0x06412041, .idmask = 0x0FFFFFFF,
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