Added support for STM32L1.
This commit is contained in:
Vegard Storheil Eriksen
parent
dddb51ca1c
commit
faa43fdc92
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@ -29,6 +29,7 @@ SRC = gdb_if.c \
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lmi.c \
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arm7tdmi.c \
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stm32f4.c \
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stm32l1.c \
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crc32.c \
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sam3x.c \
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target.c \
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@ -361,6 +361,7 @@ cortexm_probe(struct target_s *target)
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PROBE(stm32f1_probe);
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PROBE(stm32f4_probe);
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PROBE(stm32l1_probe);
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PROBE(lpc11xx_probe);
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PROBE(sam3x_probe);
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/* Try LMI last, as it doesn't fail. */
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@ -197,6 +197,7 @@ void target_add_commands(target *t, const struct command_s *cmds, const char *na
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int cortexm_probe(struct target_s *target);
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int stm32f1_probe(struct target_s *target);
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int stm32f4_probe(struct target_s *target);
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int stm32l1_probe(struct target_s *target);
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int lmi_probe(struct target_s *target);
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int lpc11xx_probe(struct target_s *target);
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int sam3x_probe(struct target_s *target);
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@ -0,0 +1,229 @@
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/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2012 Vegard Storheil Eriksen <zyp@jvnv.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements STM32L1 target specific functions for detecting
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* the device, providing the XML memory map and Flash memory programming.
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*
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* Refereces:
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* ST doc - RM0038
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* Reference manual - STM32L151xx, STM32L152xx and STM32L162xx
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* advanced ARM-based 32-bit MCUs
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* ST doc - PM0062
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* Programming manual - STM32L151xx, STM32L152xx and STM32L162xx
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* Flash and EEPROM programming
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*/
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#include <stdlib.h>
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#include <string.h>
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#include "general.h"
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#include "adiv5.h"
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#include "target.h"
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#include "command.h"
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#include "gdb_packet.h"
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static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, int len);
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static int stm32l1_flash_write(struct target_s *target, uint32_t dest,
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const uint8_t *src, int len);
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static const char stm32l1_driver_str[] = "STM32L1xx";
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static const char stm32l1_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* "<!DOCTYPE memory-map "
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" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
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"<memory-map>"
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" <memory type=\"flash\" start=\"0x8000000\" length=\"0x80000\">"
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" <property name=\"blocksize\">0x100</property>"
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" </memory>"
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x5000\"/>"
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"</memory-map>";
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/* Flash Controller Register Map */
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#define FLASH_BASE 0x40023C00
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#define FLASH_ACR (FLASH_BASE+0x00)
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#define FLASH_PECR (FLASH_BASE+0x04)
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#define FLASH_PDKEYR (FLASH_BASE+0x08)
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#define FLASH_PEKEYR (FLASH_BASE+0x0C)
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#define FLASH_PRGKEYR (FLASH_BASE+0x10)
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#define FLASH_OPTKEYR (FLASH_BASE+0x14)
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#define FLASH_SR (FLASH_BASE+0x18)
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#define FLASH_OBR (FLASH_BASE+0x1C)
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#define FLASH_WRPR1 (FLASH_BASE+0x20)
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#define FLASH_WRPR2 (FLASH_BASE+0x80)
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#define FLASH_WRPR3 (FLASH_BASE+0x84)
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#define FLASH_PECR_FPRG (1 << 10)
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#define FLASH_PECR_ERASE (1 << 9)
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#define FLASH_PECR_PROG (1 << 3)
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#define FLASH_SR_BSY (1 << 0)
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#define FLASH_SR_EOP (1 << 1)
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#define FLASH_SR_ERROR_MASK (0x1f << 8)
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#define PEKEY1 0x89ABCDEF
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#define PEKEY2 0x02030405
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#define PRGKEY1 0x8C9DAEBF
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#define PRGKEY2 0x13141516
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#define DBGMCU_IDCODE 0xE0042000
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int stm32l1_probe(struct target_s *target)
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{
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uint32_t idcode;
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idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE);
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switch(idcode & 0xFFF) {
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case 0x416: /* Medium density */
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case 0x436: /* High density */
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target->driver = stm32l1_driver_str;
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target->xml_mem_map = stm32l1_xml_memory_map;
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target->flash_erase = stm32l1_flash_erase;
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target->flash_write = stm32l1_flash_write;
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return 0;
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}
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return -1;
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}
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static void stm32l1_flash_unlock(ADIv5_AP_t *ap)
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{
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adiv5_ap_mem_write(ap, FLASH_PEKEYR, PEKEY1);
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adiv5_ap_mem_write(ap, FLASH_PEKEYR, PEKEY2);
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adiv5_ap_mem_write(ap, FLASH_PRGKEYR, PRGKEY1);
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adiv5_ap_mem_write(ap, FLASH_PRGKEYR, PRGKEY2);
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}
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static int stm32l1_flash_erase(struct target_s *target, uint32_t addr, int len)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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uint16_t sr;
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addr &= ~255;
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len &= ~255;
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stm32l1_flash_unlock(ap);
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/* Flash page erase instruction */
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adiv5_ap_mem_write(ap, FLASH_PECR, FLASH_PECR_ERASE | FLASH_PECR_PROG);
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/* Read FLASH_SR to poll for BSY bit */
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while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(target))
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return -1;
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while(len) {
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/* Write first word of page to 0 */
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adiv5_ap_mem_write(ap, addr, 0);
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len -= 256;
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addr += 256;
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}
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/* Disable programming mode */
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adiv5_ap_mem_write(ap, FLASH_PECR, 0);
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/* Check for error */
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sr = adiv5_ap_mem_read(ap, FLASH_SR);
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if ((sr & FLASH_SR_ERROR_MASK) || !(sr & FLASH_SR_EOP))
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return -1;
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return 0;
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}
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static int stm32l1_flash_write(struct target_s *target, uint32_t dest,
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const uint8_t *src, int len)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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uint16_t sr;
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/* Handle non word-aligned start */
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if(dest & 3) {
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uint32_t data = 0;
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uint32_t wlen = 4 - (dest & 3);
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if(wlen > len)
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wlen = len;
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memcpy((uint8_t *)&data + (dest & 3), src, wlen);
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adiv5_ap_mem_write(ap, dest & ~3, data);
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src += wlen;
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dest += wlen;
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len -= wlen;
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}
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/* Handle non half-page-aligned start */
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if(dest & 127 && len >= 4) {
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uint32_t xlen = 128 - (dest & 127);
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if(xlen > len)
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xlen = len & ~3;
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target_mem_write_words(target, dest, (uint32_t*)src, xlen);
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src += xlen;
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dest += xlen;
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len -= xlen;
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}
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/* Write half-pages */
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if(len > 128) {
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/* Enable half page mode */
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adiv5_ap_mem_write(ap, FLASH_PECR, FLASH_PECR_FPRG | FLASH_PECR_PROG);
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/* Read FLASH_SR to poll for BSY bit */
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while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(target))
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return -1;
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target_mem_write_words(target, dest, (uint32_t*)src, len & ~127);
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src += len & ~127;
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dest += len & ~127;
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len -= len & ~127;
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/* Disable half page mode */
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adiv5_ap_mem_write(ap, FLASH_PECR, 0);
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/* Read FLASH_SR to poll for BSY bit */
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while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(target))
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return -1;
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}
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/* Handle non-full page at the end */
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if(len >= 4) {
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target_mem_write_words(target, dest, (uint32_t*)src, len & ~3);
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src += len & ~3;
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dest += len & ~3;
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len -= len & ~3;
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}
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/* Handle non-full word at the end */
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if(len) {
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uint32_t data = 0;
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memcpy((uint8_t *)&data, src, len);
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adiv5_ap_mem_write(ap, dest, data);
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}
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/* Check for error */
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sr = adiv5_ap_mem_read(ap, FLASH_SR);
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if ((sr & FLASH_SR_ERROR_MASK) || !(sr & FLASH_SR_EOP))
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return -1;
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return 0;
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}
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