Add support for Atmel SAM3N devices.
This commit is contained in:
Gareth McMullin
parent
cdaed128c1
commit
feaf626673
124
src/sam3x.c
124
src/sam3x.c
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@ -38,8 +38,6 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest,
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static bool sam3x_cmd_gpnvm_get(target *t);
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static bool sam3x_cmd_gpnvm_set(target *t, int argc, char *argv[]);
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static const char sam3x_driver_str[] = "Atmel SAM3X";
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const struct command_s sam3x_cmd_list[] = {
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{"gpnvm_get", (cmd_handler)sam3x_cmd_gpnvm_get, "Get GPVNM value"},
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{"gpnvm_set", (cmd_handler)sam3x_cmd_gpnvm_set, "Set GPVNM bit"},
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@ -58,13 +56,25 @@ static const char sam3x_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x200000\"/>"
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"</memory-map>";
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static const char sam3n_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* "<!DOCTYPE memory-map "
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" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
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"<memory-map>"
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" <memory type=\"flash\" start=\"0x400000\" length=\"0x400000\">"
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" <property name=\"blocksize\">0x100</property>"
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" </memory>"
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" <memory type=\"rom\" start=\"0x800000\" length=\"0x400000\"/>"
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x200000\"/>"
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"</memory-map>";
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/* Enhanced Embedded Flash Controller (EEFC) Register Map */
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#define EEFC_BASE(x) (0x400E0A00+((x)*0x400))
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#define EEFC_FMR(x) (EEFC_BASE(x)+0x00)
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#define EEFC_FCR(x) (EEFC_BASE(x)+0x04)
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#define EEFC_FSR(x) (EEFC_BASE(x)+0x08)
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#define EEFC_FRR(x) (EEFC_BASE(x)+0x0C)
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#define SAM3N_EEFC_BASE 0x400E0A00
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#define SAM3X_EEFC_BASE(x) (0x400E0A00+((x)*0x400))
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#define EEFC_FMR(base) ((base)+0x00)
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#define EEFC_FCR(base) ((base)+0x04)
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#define EEFC_FSR(base) ((base)+0x08)
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#define EEFC_FRR(base) ((base)+0x0C)
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#define EEFC_FCR_FKEY (0x5A << 24)
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#define EEFC_FCR_FCMD_GETD 0x00
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@ -87,7 +97,8 @@ static const char sam3x_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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#define EEFC_FSR_FLOCKE (1 << 2)
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#define EEFC_FSR_ERROR (EEFC_FSR_FCMDE | EEFC_FSR_FLOCKE)
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#define CHIPID_CIDR 0x400E0940
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#define SAM3X_CHIPID_CIDR 0x400E0940
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#define SAM3N_CHIPID_CIDR 0x400E0740
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#define CHIPID_CIDR_VERSION_MASK (0x1F << 0)
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#define CHIPID_CIDR_EPROC_CM3 (0x03 << 5)
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@ -102,6 +113,9 @@ static const char sam3x_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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#define CHIPID_CIDR_ARCH_SAM3XxC (0x84 << 20)
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#define CHIPID_CIDR_ARCH_SAM3XxE (0x85 << 20)
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#define CHIPID_CIDR_ARCH_SAM3XxG (0x86 << 20)
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#define CHIPID_CIDR_ARCH_SAM3NxA (0x93 << 20)
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#define CHIPID_CIDR_ARCH_SAM3NxB (0x94 << 20)
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#define CHIPID_CIDR_ARCH_SAM3NxC (0x95 << 20)
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#define CHIPID_CIDR_NVPTYP_MASK (0x07 << 28)
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#define CHIPID_CIDR_NVPTYP_FLASH (0x02 << 28)
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#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x03 << 28)
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@ -113,70 +127,92 @@ bool sam3x_probe(struct target_s *target)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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target->idcode = adiv5_ap_mem_read(ap, CHIPID_CIDR);
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target->idcode = adiv5_ap_mem_read(ap, SAM3X_CHIPID_CIDR);
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/* FIXME: Check for all variants with similar flash interface */
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switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
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case CHIPID_CIDR_ARCH_SAM3XxC | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3XxE | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3XxG | CHIPID_CIDR_EPROC_CM3:
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target->driver = sam3x_driver_str;
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target->driver = "Atmel SAM3X";
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target->xml_mem_map = sam3x_xml_memory_map;
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target->flash_erase = sam3x_flash_erase;
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target->flash_write = sam3x_flash_write;
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target_add_commands(target, sam3x_cmd_list, sam3x_driver_str);
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target_add_commands(target, sam3x_cmd_list, "SAM3X");
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return true;
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}
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target->idcode = adiv5_ap_mem_read(ap, SAM3N_CHIPID_CIDR);
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switch (target->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
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case CHIPID_CIDR_ARCH_SAM3NxA | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3NxB | CHIPID_CIDR_EPROC_CM3:
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case CHIPID_CIDR_ARCH_SAM3NxC | CHIPID_CIDR_EPROC_CM3:
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target->driver = "Atmel SAM3N";
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target->xml_mem_map = sam3n_xml_memory_map;
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target->flash_erase = sam3x_flash_erase;
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target->flash_write = sam3x_flash_write;
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target_add_commands(target, sam3x_cmd_list, "SAM3N");
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return true;
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}
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return false;
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}
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static int
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sam3x_flash_cmd(struct target_s *target, int bank, uint8_t cmd, uint16_t arg)
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sam3x_flash_cmd(struct target_s *target, uint32_t base, uint8_t cmd, uint16_t arg)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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adiv5_ap_mem_write(ap, EEFC_FCR(bank),
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DEBUG("%s: base = 0x%08x cmd = 0x%02X, arg = 0x%06X\n",
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__func__, base, cmd, arg);
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adiv5_ap_mem_write(ap, EEFC_FCR(base),
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EEFC_FCR_FKEY | cmd | ((uint32_t)arg << 8));
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while(!(adiv5_ap_mem_read(ap, EEFC_FSR(bank)) & EEFC_FSR_FRDY))
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while(!(adiv5_ap_mem_read(ap, EEFC_FSR(base)) & EEFC_FSR_FRDY))
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if(target_check_error(target))
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return -1;
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uint32_t sr = adiv5_ap_mem_read(ap, EEFC_FSR(bank));
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uint32_t sr = adiv5_ap_mem_read(ap, EEFC_FSR(base));
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return sr & EEFC_FSR_ERROR;
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}
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static int
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sam3x_flash_bank(struct target_s *target, uint32_t addr, uint32_t *offset)
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static uint32_t
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sam3x_flash_base(struct target_s *target, uint32_t addr, uint32_t *offset)
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{
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uint32_t half = -1;
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switch (target->idcode & CHIPID_CIDR_NVPSIZ_MASK) {
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case CHIPID_CIDR_NVPSIZ_128K:
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half = 0x00090000;
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break;
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case CHIPID_CIDR_NVPSIZ_256K:
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half = 0x000A0000;
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break;
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case CHIPID_CIDR_NVPSIZ_512K:
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half = 0x000C0000;
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break;
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}
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if (addr > half) {
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if (offset)
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*offset = addr - half;
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return 1;
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if (strcmp(target->driver, "Atmel SAM3X") == 0) {
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uint32_t half = -1;
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switch (target->idcode & CHIPID_CIDR_NVPSIZ_MASK) {
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case CHIPID_CIDR_NVPSIZ_128K:
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half = 0x00090000;
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break;
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case CHIPID_CIDR_NVPSIZ_256K:
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half = 0x000A0000;
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break;
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case CHIPID_CIDR_NVPSIZ_512K:
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half = 0x000C0000;
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break;
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}
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if (addr > half) {
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if (offset)
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*offset = addr - half;
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return SAM3X_EEFC_BASE(1);
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} else {
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if (offset)
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*offset = addr - 0x80000;
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return SAM3X_EEFC_BASE(0);
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}
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}
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/* SAM3N device */
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if (offset)
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*offset = addr - 0x80000;
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return 0;
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*offset = addr - 0x400000;
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return SAM3N_EEFC_BASE;
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}
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static int sam3x_flash_erase(struct target_s *target, uint32_t addr, int len)
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{
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uint32_t offset;
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uint8_t bank = sam3x_flash_bank(target, addr, &offset);
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uint32_t base = sam3x_flash_base(target, addr, &offset);
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unsigned chunk = offset / PAGE_SIZE;
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uint8_t buf[PAGE_SIZE];
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@ -190,7 +226,7 @@ static int sam3x_flash_erase(struct target_s *target, uint32_t addr, int len)
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target_mem_write_words(target, addr, (void*)buf, PAGE_SIZE);
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while (len) {
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if(sam3x_flash_cmd(target, bank, EEFC_FCR_FCMD_EWP, chunk))
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if(sam3x_flash_cmd(target, base, EEFC_FCR_FCMD_EWP, chunk))
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return -1;
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len -= PAGE_SIZE;
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@ -205,7 +241,7 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest,
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const uint8_t *src, int len)
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{
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uint32_t offset;
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uint8_t bank = sam3x_flash_bank(target, dest, &offset);
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uint32_t base = sam3x_flash_base(target, dest, &offset);
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uint8_t buf[PAGE_SIZE];
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unsigned first_chunk = offset / PAGE_SIZE;
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unsigned last_chunk = (offset + len - 1) / PAGE_SIZE;
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@ -240,7 +276,7 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest,
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}
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target_mem_write_words(target, dest, (void*)buf, PAGE_SIZE);
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if(sam3x_flash_cmd(target, bank, EEFC_FCR_FCMD_WP, chunk))
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if(sam3x_flash_cmd(target, base, EEFC_FCR_FCMD_WP, chunk))
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return -1;
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}
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@ -250,9 +286,10 @@ static int sam3x_flash_write(struct target_s *target, uint32_t dest,
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static bool sam3x_cmd_gpnvm_get(target *t)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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uint32_t base = sam3x_flash_base(t, 0, NULL);
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sam3x_flash_cmd(t, 0, EEFC_FCR_FCMD_GGPB, 0);
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gdb_outf("GPNVM: 0x%08X\n", adiv5_ap_mem_read(ap, EEFC_FRR(0)));
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sam3x_flash_cmd(t, base, EEFC_FCR_FCMD_GGPB, 0);
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gdb_outf("GPNVM: 0x%08X\n", adiv5_ap_mem_read(ap, EEFC_FRR(base)));
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return true;
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}
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@ -260,6 +297,7 @@ static bool sam3x_cmd_gpnvm_get(target *t)
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static bool sam3x_cmd_gpnvm_set(target *t, int argc, char *argv[])
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{
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uint32_t bit, cmd;
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uint32_t base = sam3x_flash_base(t, 0, NULL);
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if (argc != 3) {
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gdb_out("usage: monitor gpnvm_set <bit> <val>\n");
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@ -268,7 +306,7 @@ static bool sam3x_cmd_gpnvm_set(target *t, int argc, char *argv[])
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bit = atol(argv[1]);
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cmd = atol(argv[2]) ? EEFC_FCR_FCMD_SGPB : EEFC_FCR_FCMD_CGPB;
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sam3x_flash_cmd(t, 0, cmd, bit);
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sam3x_flash_cmd(t, base, cmd, bit);
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sam3x_cmd_gpnvm_get(t);
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return true;
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