The CH32F1 routine now reads the IDCode into a local.
If the part number matches and appears to be the chip (based on Flash locking), it only then writes the IDCode into `t->idcode`, which is at the point we can only `return true` from the probe routine anyway.
cortexm_initial_halt() repeats the DHCSR write with high values for TRNCNT in
CSW. This is needed to catch a STM32F7 mostly in WFI. While the repeated write
is running, STLINKV3 on a Nucleo-WL55 (V3J7M2B0S0) answers first with
STLINK_SWD_AP_WAIT and on more read if write command is still running with
STLINK_SWD_AP_FAULT. At some point when the last command is finished, normal
STLINK_ERROR_OK indicates finally successful read. Treat STLINK_SWD_AP_FAULT
after STLINK_ERROR_WAIT as STLINK_ERROR_WAIT in that case. STLINK_SWD_AP_FAULT
may still be issued on other invalid accesses and should still be treated as
error in the other possible cases. Fixes#1071.
Rather than casting here, use PRIu32 - as in "%" PRIu32 ".%" PRIu32 - it's undefined behaviour and quite illegal to do the cast as, depending on platform, you'll end up with only some of the bytes in units and tenths written and which ones and what that means will depend on endianess.
"Single" core STM32WLE still sees AP1 but on first scan aborts gracefully
after some errors and on later runs sees AP1 as unusable. Fixes#832.
Decode the Cross trigger interface found on CPU2 on STM32WBxx.
E.g on STM32WXXX AP1 with C2BOOT not set, the AP base registers have valid
values but reading them fails and turns the AP unusable. BMDA reading CIDR
with multiple calls will will loop and finally hang up BMD. Other target
devices may show similar behaviour.
Reading CIDR with a single call allows recovery from in that case and
additional spares target transactions.
Try to look for repeating sectors before reverting to reading the
JEDEC ID of the flash chip. This way we don't interrupt the flash
execution if a valid program is running, but can detect the flash
size if the flash memory has been erased.