f1752c7a1a
stm32f4: Allow DWORD parallelism.
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Needs external VPP!
2018-06-16 13:30:53 +02:00
15312eb86c
stm32f4: Honor parallelism also for erase.
2018-06-16 13:30:53 +02:00
bfeb6f0db9
stm32f4: Use buffered direct flash write with choosen size.
2018-06-16 13:30:53 +02:00
54f73858f9
Provide a target function to write with given size.
2018-06-16 13:30:08 +02:00
ae6f0eadc9
Support for MSP432 TI MCUs ( #353 )
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Introduces flashing and debugging support for Texas Instruments MSP432
series of MCUs
2018-06-07 08:34:21 +12:00
077e455a94
Setting the driver string on scan.
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This way swdp_scan and jtag_scan commands will show the chip that was
detected instead of the generic STM32F4 string. The generic name is
most confusing when attaching to an STM32F7 target.
2018-06-01 12:46:14 -07:00
df05d7ce7b
libftdi: Allow device specific port/pin to read SWD bitbanged.
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Gracefully abort swd scan if devices can not do SWD.
Best effort to indicated SWD capability on existing cables and
add descriptions for the cables.
2018-05-30 19:21:03 +02:00
f3cacba219
libftdi: Flush buffer with detach.
2018-05-30 19:21:03 +02:00
48d232807e
Merge pull request #337 from adamgreig/stm32f4-ram-size
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Update maximum RAM sizes for F4 and F7 devices
2018-04-26 13:38:11 +12:00
e1cefb2031
Update maximum RAM sizes for F4 and F7 devices
2018-04-24 11:06:07 +01:00
93f3b14b68
stm32f1(f0): Do not read normal device registers during probe.
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Device may not be halted and memory map setup may fail.
2018-04-23 11:06:08 +12:00
a0596a0dcc
stm32l4: Build Memory Map during attach.
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Reading target registers while target not halted may fail and result in
invalid memory map.
2018-04-23 11:06:08 +12:00
5f404cdbc0
Construct memory map on the stack
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The memory map uses 1k of SRAM and is only needed during attach. Release
after use lowers pressure on SRAM.
2018-04-23 10:51:04 +12:00
63967346cd
stm32f4: Don't duplicate resources on reattach.
2018-04-23 10:48:05 +12:00
00decb3718
target: Separate function to free memory map.
2018-04-23 10:48:05 +12:00
1fd2a24c2d
stm32f4: Only construct memory map at attach.
2018-04-23 10:48:05 +12:00
9d7925792f
Merge branch 'master' into always_buffer_flash
2018-04-23 10:40:20 +12:00
fa62403ee3
nrf51: Add nRF51802 device id. ( #331 )
2018-04-03 10:45:56 +12:00
cfaa5ea963
Merge branch 'korken89-master'
2018-03-27 13:01:06 +13:00
76bfb4929d
Use lowercase register names.
2018-03-27 13:00:39 +13:00
a3f855ce5c
Merge branch 'master' of https://github.com/konsgn/blackmagic into konsgn-master
2018-03-27 08:03:03 +13:00
31965a5bbc
Added support for k64 ( #301 )
2018-03-25 14:43:33 -07:00
471ce2547c
Added LPC17xx support ( #317 )
2018-03-25 12:53:30 -07:00
a41d8cb97a
Another nRF52 device id. ( #315 )
2018-03-25 12:37:51 -07:00
1ee6d4503e
Update to split 'special' into its sane parts (update from @mubes)
2018-03-24 16:44:59 +01:00
04fbabb299
mkl27 support
2018-01-21 23:43:01 -05:00
1fe870b8df
added MKL27<128kB support
2018-01-16 13:23:36 -05:00
922f857de7
stm32f1.c: Add missing fall through statement needed by GCC7.
2017-12-18 13:56:59 +01:00
1f3c235205
src/target/stm32f1.c: Add CCM Ram of STM32F303 devices.
2017-12-08 13:39:24 +01:00
048e8447a5
target: Only support buffered flash writes
2017-10-13 08:58:37 +13:00
c53a12bfd1
cortexm: Better cache support for Cortex-M7
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- On probe, read CTR for cache presence and minimum line length
- Make D-Cache clean a function
- Clean before memory reads
- Clean and invalidate before memory writes
- Flush all I-Cache before resume
2017-10-12 09:26:01 +13:00
0e5b3ab00e
Make Cortex M driver write DCCIMVAC (Data cache clean and invalidate by address to the PoC=Point of Coherency) prior to reading or writing each 32 bytes of RAM
2017-10-12 08:41:58 +13:00
120a2d9378
target: Fix calculation of erase size.
2017-10-05 22:11:01 +02:00
a7815fff3d
target.c: No need to split write while still in same flash block.
2017-10-04 21:52:29 +02:00
25610e5ec5
target: Fix unconsistant use of tmplen.
2017-10-04 21:52:29 +02:00
0aa47113f3
stm32f4: Fix F4 dual bank OPTCR1 to option byte mapping.
2017-10-02 16:22:14 +02:00
c4d3712b39
stm32f4.c: Rework flash structure recognition.
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Dual bank devices do not have sectors (8)12..15 !
Dual banks devices need to MER1 set for mass erase.
F72x has different FLASHSIZE_BASE
2017-10-02 16:22:14 +02:00
259f1b90df
cortexa: Check for fault on set/clear soft breakpoint.
2017-09-20 11:16:36 +12:00
1cb4271749
cortexa: Remove problematic code for AHB access.
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The old code for 'fast' memory accesses using the AHB directly
has problems with data consitency. Until this can be resolved, I'm
removing the affected code.
2017-09-19 09:13:22 +12:00
2df0c7d6a7
Merge pull request #261 from cpavlina/tm4c
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lm3s/tm4c: add TM4C1230C3PM
2017-09-06 15:34:42 +12:00
46e363393f
Add nRF52840 support (PCA10056, nrf52840 PDK)
2017-09-03 23:05:29 +00:00
37f9623de2
Added NRF51_FICR_CONFIGID for nRF51822 QFAA H2
2017-08-30 17:14:52 +02:00
37bb86267a
STM32F0: Several STM32F0[3|7]0 have same ID as other STM32F0X0.
2017-08-28 22:58:59 +02:00
a0b0b8a716
lm3s/tm4c: add TM4C1230C3PM
2017-07-21 13:29:41 -06:00
7663794fdf
Merge pull request #247 from schodet/stm32f4-x8-x32
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Allow programming STM32F4 when using a low voltage
2017-07-09 14:33:06 -07:00
3846ea4708
stm32f4: allow selection of flash programming parallelism
2017-07-09 23:26:49 +02:00
09f49b469d
Merge pull request #256 from nar0909/patch-1
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New Device Id update - QFAA G1
2017-07-09 13:45:52 -07:00
43ac4a04f7
New Device Id update - QFAA G1
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New device Id - for NRF51822 QFAA G1 1529AM.
2017-07-04 12:32:39 +10:00
f036be8cb2
Identify and support LPC1112/102 MCU as well
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Signed-off-by: Daniel Egger <daniel@eggers-club.de>
2017-06-23 21:52:13 +02:00
984f8b3d94
Merge pull request #248 from schodet/typo
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stm32f4: fix typo in target name
2017-06-22 18:35:29 -07:00
Uwe Bonnes
newbrain
Piotr Esden-Tempski
Gareth McMullin
Adam Greig
Mike Walters
Christopher Woodall
Akila Ravihansa Perera
Mark Rages
Emil Fresk
Konsgn
Nick Downing
David R. Piegdon
Carl Sandström
Chris Pavlina
Nicolas Schodet
nar0909
Daniel Egger