341 lines
13 KiB
C
341 lines
13 KiB
C
/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2011 Black Sphere Technologies Ltd.
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* Written by Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ADIV5_H
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#define __ADIV5_H
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#include "jtag_scan.h"
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#define ADIV5_APnDP 0x100U
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#define ADIV5_DP_REG(x) (x)
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#define ADIV5_AP_REG(x) (ADIV5_APnDP | (x))
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#define ADIV5_DP_BANK0 0x00U
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#define ADIV5_DP_BANK1 0x10U
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#define ADIV5_DP_BANK2 0x20U
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#define ADIV5_DP_BANK3 0x30U
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#define ADIV5_DP_BANK4 0x40U
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/* ADIv5 DP Register addresses */
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#define ADIV5_DP_IDCODE ADIV5_DP_REG(0x0U)
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#define ADIV5_DP_ABORT ADIV5_DP_REG(0x0U)
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#define ADIV5_DP_CTRLSTAT ADIV5_DP_REG(0x4U)
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#define ADIV5_DP_TARGETID (ADIV5_DP_BANK2 | ADIV5_DP_REG(0x4U))
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#define ADIV5_DP_SELECT ADIV5_DP_REG(0x8U)
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#define ADIV5_DP_RDBUFF ADIV5_DP_REG(0xCU)
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#define ADIV5_DP_TARGETSEL ADIV5_DP_REG(0xCU)
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/* AP DPIDR */
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#define ADIV5_DP_DPIDR_REVISION_OFFSET 28U
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#define ADIV5_DP_DPIDR_REVISION_MASK (0xfU << ADIV5_DP_DPIDR_VERSION_OFFSET)
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#define ADIV5_DP_DPIDR_PARTNO_OFFSET 20U
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#define ADIV5_DP_DPIDR_PARTNO_MASK (0xffU << ADIV5_DP_DPIDR_PARTNO_OFFSET)
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#define ADIV5_DP_DPIDR_MINDP_OFFSET 16U
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#define ADIV5_DP_DPIDR_MINDP (1U << ADIV5_DP_DPIDR_MINDP_OFFSET)
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#define ADIV5_DP_DPIDR_VERSION_OFFSET 12U
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#define ADIV5_DP_DPIDR_VERSION_MASK (0xfU << ADIV5_DP_DPIDR_VERSION_OFFSET)
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#define ADIV5_DP_DPIDR_VERSION_DPv1 (1U << ADIV5_DP_DPIDR_VERSION_OFFSET)
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#define ADIV5_DP_DPIDR_VERSION_DPv2 (2U << ADIV5_DP_DPIDR_VERSION_OFFSET)
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#define ADIV5_DP_DPIDR_DESIGNER_OFFSET 1U
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#define ADIV5_DP_DPIDR_DESIGNER_MASK (0x7ffU << ADIV5_DP_DPIDR_DESIGNER_OFFSET)
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/* AP Abort Register (ABORT) */
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/* Bits 31:5 - Reserved */
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#define ADIV5_DP_ABORT_ORUNERRCLR (1U << 4U)
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#define ADIV5_DP_ABORT_WDERRCLR (1U << 3U)
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#define ADIV5_DP_ABORT_STKERRCLR (1U << 2U)
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#define ADIV5_DP_ABORT_STKCMPCLR (1U << 1U)
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/* Bits 5:1 - SW-DP only, reserved in JTAG-DP */
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#define ADIV5_DP_ABORT_DAPABORT (1U << 0U)
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/* Control/Status Register (CTRLSTAT) */
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#define ADIV5_DP_CTRLSTAT_CSYSPWRUPACK (1U << 31U)
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#define ADIV5_DP_CTRLSTAT_CSYSPWRUPREQ (1U << 30U)
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#define ADIV5_DP_CTRLSTAT_CDBGPWRUPACK (1U << 29U)
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#define ADIV5_DP_CTRLSTAT_CDBGPWRUPREQ (1U << 28U)
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#define ADIV5_DP_CTRLSTAT_CDBGRSTACK (1U << 27U)
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#define ADIV5_DP_CTRLSTAT_CDBGRSTREQ (1U << 26U)
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/* Bits 25:24 - Reserved */
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/* Bits 23:12 - TRNCNT */
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#define ADIV5_DP_CTRLSTAT_TRNCNT (1U << 12U)
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/* Bits 11:8 - MASKLANE */
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#define ADIV5_DP_CTRLSTAT_MASKLANE
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/* Bits 7:6 - Reserved in JTAG-DP */
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#define ADIV5_DP_CTRLSTAT_WDATAERR (1U << 7U)
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#define ADIV5_DP_CTRLSTAT_READOK (1U << 6U)
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#define ADIV5_DP_CTRLSTAT_STICKYERR (1U << 5U)
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#define ADIV5_DP_CTRLSTAT_STICKYCMP (1U << 4U)
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#define ADIV5_DP_CTRLSTAT_TRNMODE_MASK (3U << 2U)
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#define ADIV5_DP_CTRLSTAT_STICKYORUN (1U << 1U)
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#define ADIV5_DP_CTRLSTAT_ORUNDETECT (1U << 0U)
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/* ADIv5 MEM-AP Registers */
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#define ADIV5_AP_CSW ADIV5_AP_REG(0x00U)
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#define ADIV5_AP_TAR ADIV5_AP_REG(0x04U)
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/* 0x08 - Reserved */
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#define ADIV5_AP_DRW ADIV5_AP_REG(0x0CU)
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#define ADIV5_AP_DB(x) ADIV5_AP_REG(0x10U + (4U * (x)))
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/* 0x20:0xF0 - Reserved */
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#define ADIV5_AP_CFG ADIV5_AP_REG(0xF4U)
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#define ADIV5_AP_BASE ADIV5_AP_REG(0xF8U)
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#define ADIV5_AP_IDR ADIV5_AP_REG(0xFCU)
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/* AP Control and Status Word (CSW) */
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#define ADIV5_AP_CSW_DBGSWENABLE (1U << 31U)
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/* Bits 30:24 - Prot, Implementation defined, for Cortex-M3: */
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#define ADIV5_AP_CSW_MASTERTYPE_DEBUG (1U << 29U)
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#define ADIV5_AP_CSW_HPROT1 (1U << 25U)
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#define ADIV5_AP_CSW_SPIDEN (1U << 23U)
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/* Bits 22:12 - Reserved */
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/* Bits 11:8 - Mode, must be zero */
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#define ADIV5_AP_CSW_TRINPROG (1U << 7U)
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#define ADIV5_AP_CSW_DEVICEEN (1U << 6U)
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#define ADIV5_AP_CSW_ADDRINC_NONE (0U << 4U)
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#define ADIV5_AP_CSW_ADDRINC_SINGLE (1U << 4U)
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#define ADIV5_AP_CSW_ADDRINC_PACKED (2U << 4U)
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#define ADIV5_AP_CSW_ADDRINC_MASK (3U << 4U)
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/* Bit 3 - Reserved */
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#define ADIV5_AP_CSW_SIZE_BYTE (0U << 0U)
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#define ADIV5_AP_CSW_SIZE_HALFWORD (1U << 0U)
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#define ADIV5_AP_CSW_SIZE_WORD (2U << 0U)
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#define ADIV5_AP_CSW_SIZE_MASK (7U << 0U)
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/* AP Debug Base Address Register (BASE) */
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#define ADIV5_AP_BASE_BASEADDR (0xFFFFF000U)
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#define ADIV5_AP_BASE_PRESENT (1U << 0)
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/* ADIv5 Class 0x1 ROM Table Registers */
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#define ADIV5_ROM_MEMTYPE 0xFCCU
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#define ADIV5_ROM_MEMTYPE_SYSMEM (1U << 0U)
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#define ADIV5_ROM_ROMENTRY_PRESENT (1U << 0U)
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#define ADIV5_ROM_ROMENTRY_OFFSET (0xFFFFF000U)
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/* Constants to make RnW parameters more clear in code */
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#define ADIV5_LOW_WRITE 0
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#define ADIV5_LOW_READ 1
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#define SWDP_ACK_OK 0x01U
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#define SWDP_ACK_WAIT 0x02U
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#define SWDP_ACK_FAULT 0x04U
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/* JEP-106 code list
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* JEP-106 is a JEDEC standard assigning IDs to different manufacturers
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* the codes in this list are encoded as 16 bit values,
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* with the first bit marking a legacy code (ASCII, not JEP106), the following 3 bits being NULL/unused
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* the following 4 bits the number of continuation codes (see JEP106 continuation scheme),
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* and the last 8 bits being the code itself (without parity, bit 7 is always 0).
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*
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* |15 |11 |7|6 0|
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* | | | | | | | | |0| | | | | | | |
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* |\____/ \______/|\_____________/
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* | V V | V
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* | Unused Cont | code
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* | Code |
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* \_ Legacy flag \_ Parity bit (always 0)
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*/
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#define ASCII_CODE_FLAG (1U << 15U) /* flag the code as legacy ASCII */
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#define JEP106_MANUFACTURER_ARM 0x43BU /* ARM Ltd. */
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#define JEP106_MANUFACTURER_FREESCALE 0x00eU /* Freescale */
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#define JEP106_MANUFACTURER_TEXAS 0x017U /* Texas Instruments */
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#define JEP106_MANUFACTURER_ATMEL 0x01fU /* Atmel */
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#define JEP106_MANUFACTURER_STM 0x020U /* STMicroelectronics */
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#define JEP106_MANUFACTURER_CYPRESS 0x034U /* Cypress Semiconductor */
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#define JEP106_MANUFACTURER_INFINEON 0x041U /* Infineon Technologies */
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#define JEP106_MANUFACTURER_NORDIC 0x244U /* Nordic Semiconductor */
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#define JEP106_MANUFACTURER_SPECULAR 0x501U /* LPC845 with code 501. Strange!? Specular Networks */
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#define JEP106_MANUFACTURER_ENERGY_MICRO 0x673U /* Energy Micro */
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#define JEP106_MANUFACTURER_GIGADEVICE 0x751U /* GigaDevice */
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#define JEP106_MANUFACTURER_RASPBERRY 0x927U /* Raspberry Pi */
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/*
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* This code is not listed in the JEP106 standard, but is used by some stm32f1 clones
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* since we're not using this code elsewhere let's switch to the stm code.
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*/
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#define JEP106_MANUFACTURER_ERRATA_CS 0x555U
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/* CPU2 for STM32W(L|B) uses ARM's JEP-106 continuation code (4) instead of
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* STM's JEP-106 continuation code (0) like expected, CPU1 behaves as expected.
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*
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* See RM0453
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* https://www.st.com/resource/en/reference_manual/rm0453-stm32wl5x-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf :
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* 38.8.2 CPU1 ROM CoreSight peripheral identity register 4 (ROM_PIDR4)
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* vs
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* 38.13.2 CPU2 ROM1 CoreSight peripheral identity register 4 (C2ROM1_PIDR4)
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*
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* let's call this an errata and switch to the "correct" continuation scheme.
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*
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* note: the JEP code 0x420 would belong to "Legend Silicon Corp." so in
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* the unlikely event we need to support chips by them, here be dragons.
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*/
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#define JEP106_MANUFACTURER_ERRATA_STM32WX 0x420U
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enum align {
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ALIGN_BYTE = 0,
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ALIGN_HALFWORD = 1,
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ALIGN_WORD = 2,
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ALIGN_DWORD = 3
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};
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typedef struct ADIv5_AP_s ADIv5_AP_t;
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/* Try to keep this somewhat absract for later adding SW-DP */
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typedef struct ADIv5_DP_s {
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int refcnt;
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uint32_t idcode;
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uint32_t targetid; /* Contains IDCODE for DPv2 devices.*/
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void (*seq_out)(uint32_t tms_states, size_t clock_cycles);
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void (*seq_out_parity)(uint32_t tms_states, size_t clock_cycles);
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uint32_t (*seq_in)(size_t clock_cycles);
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bool (*seq_in_parity)(uint32_t *ret, size_t clock_cycles);
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/* dp_low_write returns true if no OK resonse, but ignores errors */
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bool (*dp_low_write)(struct ADIv5_DP_s *dp, uint16_t addr, const uint32_t data);
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uint32_t (*dp_read)(struct ADIv5_DP_s *dp, uint16_t addr);
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uint32_t (*error)(struct ADIv5_DP_s *dp);
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uint32_t (*low_access)(struct ADIv5_DP_s *dp, uint8_t RnW, uint16_t addr, uint32_t value);
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void (*abort)(struct ADIv5_DP_s *dp, uint32_t abort);
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#if PC_HOSTED == 1
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bmp_type_t dp_bmp_type;
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bool (*ap_setup)(int i);
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void (*ap_cleanup)(int i);
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void (*ap_regs_read)(ADIv5_AP_t *ap, void *data);
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uint32_t (*ap_reg_read)(ADIv5_AP_t *ap, int num);
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void (*ap_reg_write)(ADIv5_AP_t *ap, int num, uint32_t value);
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void (*read_block)(uint32_t addr, uint8_t *data, int size);
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void (*dap_write_block_sized)(uint32_t addr, uint8_t *data, int size, enum align align);
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#endif
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uint32_t (*ap_read)(ADIv5_AP_t *ap, uint16_t addr);
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void (*ap_write)(ADIv5_AP_t *ap, uint16_t addr, uint32_t value);
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void (*mem_read)(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len);
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void (*mem_write_sized)(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len, enum align align);
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uint8_t dp_jd_index;
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uint8_t fault;
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} ADIv5_DP_t;
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struct ADIv5_AP_s {
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int refcnt;
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ADIv5_DP_t *dp;
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uint8_t apsel;
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uint32_t idr;
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uint32_t base;
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uint32_t csw;
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uint32_t ap_cortexm_demcr; /* Copy of demcr when starting */
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uint32_t ap_storage; /* E.g to hold STM32F7 initial DBGMCU_CR value.*/
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uint16_t designer_code;
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uint16_t ap_partno;
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};
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unsigned int make_packet_request(uint8_t RnW, uint16_t addr);
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#if PC_HOSTED == 0
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static inline uint32_t adiv5_dp_read(ADIv5_DP_t *dp, uint16_t addr)
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{
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return dp->dp_read(dp, addr);
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}
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static inline uint32_t adiv5_dp_error(ADIv5_DP_t *dp)
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{
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return dp->error(dp);
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}
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static inline uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t RnW, uint16_t addr, uint32_t value)
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{
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return dp->low_access(dp, RnW, addr, value);
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}
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static inline void adiv5_dp_abort(struct ADIv5_DP_s *dp, uint32_t abort)
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{
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return dp->abort(dp, abort);
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}
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static inline uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr)
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{
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return ap->dp->ap_read(ap, addr);
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}
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static inline void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value)
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{
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return ap->dp->ap_write(ap, addr, value);
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}
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static inline void adiv5_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len)
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{
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return ap->dp->mem_read(ap, dest, src, len);
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}
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static inline void adiv5_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len, enum align align)
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{
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return ap->dp->mem_write_sized(ap, dest, src, len, align);
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}
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static inline void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value)
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{
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dp->low_access(dp, ADIV5_LOW_WRITE, addr, value);
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}
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#else
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uint32_t adiv5_dp_read(ADIv5_DP_t *dp, uint16_t addr);
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uint32_t adiv5_dp_error(ADIv5_DP_t *dp);
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uint32_t adiv5_dp_low_access(struct ADIv5_DP_s *dp, uint8_t RnW, uint16_t addr, uint32_t value);
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void adiv5_dp_abort(struct ADIv5_DP_s *dp, uint32_t abort);
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uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr);
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void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value);
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void adiv5_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len);
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void adiv5_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len, enum align align);
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void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value);
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#endif
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void adiv5_dp_init(ADIv5_DP_t *dp);
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void platform_adiv5_dp_defaults(ADIv5_DP_t *dp);
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ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel);
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void remote_jtag_dev(const jtag_dev_t *jtag_dev);
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void adiv5_ap_ref(ADIv5_AP_t *ap);
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void adiv5_ap_unref(ADIv5_AP_t *ap);
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void platform_add_jtag_dev(const int dev_index, const jtag_dev_t *jtag_dev);
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void adiv5_jtag_dp_handler(uint8_t jd_index);
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int platform_jtag_dp_init(ADIv5_DP_t *dp);
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int swdptap_init(ADIv5_DP_t *dp);
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void adiv5_mem_write(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len);
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uint64_t adiv5_ap_read_pidr(ADIv5_AP_t *ap, uint32_t addr);
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void *extract(void *dest, uint32_t src, uint32_t val, enum align align);
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void firmware_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len, enum align align);
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void firmware_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len);
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void firmware_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value);
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uint32_t firmware_ap_read(ADIv5_AP_t *ap, uint16_t addr);
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uint32_t firmware_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, uint16_t addr, uint32_t value);
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uint32_t fw_adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, uint16_t addr, uint32_t value);
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uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr);
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uint32_t fw_adiv5_jtagdp_read(ADIv5_DP_t *dp, uint16_t addr);
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uint32_t firmware_swdp_error(ADIv5_DP_t *dp);
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void firmware_swdp_abort(ADIv5_DP_t *dp, uint32_t abort);
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void adiv5_jtagdp_abort(ADIv5_DP_t *dp, uint32_t abort);
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#endif
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