147 lines
3.1 KiB
Plaintext
147 lines
3.1 KiB
Plaintext
EESchema Schematic File Version 4
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EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 6 6
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Comp
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L 4xxx:4053 U500
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U 1 1 6270B9B6
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P 6250 3950
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F 0 "U500" H 6250 5031 50 0000 C CNN
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F 1 "MAX4619" H 6250 4940 50 0000 C CNN
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F 2 "Package_SO:SO-16_3.9x9.9mm_P1.27mm" H 6250 3950 50 0001 C CNN
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F 3 "http://www.intersil.com/content/dam/Intersil/documents/cd40/cd4051bms-52bms-53bms.pdf" H 6250 3950 50 0001 C CNN
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1 6250 3950
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1 0 0 -1
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$EndComp
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Wire Wire Line
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6250 4900 6250 4850
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Wire Wire Line
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6250 4900 6300 4900
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Wire Wire Line
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6350 4900 6350 4850
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Wire Wire Line
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6300 4900 6300 5000
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Connection ~ 6300 4900
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Wire Wire Line
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6300 4900 6350 4900
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$Comp
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L power:GND #PWR0149
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U 1 1 6270C54F
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P 6300 5000
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F 0 "#PWR0149" H 6300 4750 50 0001 C CNN
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F 1 "GND" H 6305 4827 50 0000 C CNN
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F 2 "" H 6300 5000 50 0001 C CNN
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F 3 "" H 6300 5000 50 0001 C CNN
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1 6300 5000
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1 0 0 -1
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$EndComp
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Text GLabel 5650 4350 0 50 Input ~ 0
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MAX_SW_A
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Text GLabel 5650 4450 0 50 Input ~ 0
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MAX_SW_B
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Wire Wire Line
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5750 4350 5650 4350
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Wire Wire Line
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5650 4450 5750 4450
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Text GLabel 4450 4250 0 50 Input ~ 0
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MAX_EN
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Text GLabel 5650 4550 0 50 Input ~ 0
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GLITCH_SIG
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Wire Wire Line
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5650 4550 5750 4550
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Text GLabel 6850 3950 2 50 Input ~ 0
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GLITCH_OUT
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Text GLabel 5650 3750 0 50 Input ~ 0
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Vdclo
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$Comp
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L power:GND #PWR0150
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U 1 1 6271CC5F
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P 5350 3650
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F 0 "#PWR0150" H 5350 3400 50 0001 C CNN
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F 1 "GND" V 5355 3522 50 0000 R CNN
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F 2 "" H 5350 3650 50 0001 C CNN
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F 3 "" H 5350 3650 50 0001 C CNN
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1 5350 3650
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0 1 1 0
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$EndComp
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Wire Wire Line
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5750 3650 5350 3650
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Wire Wire Line
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5650 3750 5750 3750
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Wire Wire Line
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6250 3050 6500 3050
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$Comp
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L power:+3V3 #PWR0152
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U 1 1 6271E09E
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P 6500 3050
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F 0 "#PWR0152" H 6500 2900 50 0001 C CNN
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F 1 "+3V3" H 6515 3223 50 0000 C CNN
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F 2 "" H 6500 3050 50 0001 C CNN
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F 3 "" H 6500 3050 50 0001 C CNN
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1 6500 3050
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0 1 1 0
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$EndComp
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Wire Wire Line
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4900 3100 4900 3950
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Wire Wire Line
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4900 3950 5750 3950
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Wire Wire Line
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6750 3650 7100 3650
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Wire Wire Line
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7100 3650 7100 2300
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Wire Wire Line
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7100 2300 4800 2300
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Wire Wire Line
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4800 2300 4800 4050
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Wire Wire Line
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4800 4050 5750 4050
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Wire Wire Line
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6850 3950 6750 3950
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Text Label 5200 3950 0 50 ~ 0
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Vglitch_hi
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Text Label 5200 4050 0 50 ~ 0
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Vglitch_lo
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Text Notes 6500 2950 0 50 ~ 0
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TODO: use\nVBUS here\ninstead?
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$Comp
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L Device:R R500
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U 1 1 62925A32
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P 4700 4250
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F 0 "R500" V 4493 4250 50 0000 C CNN
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F 1 "4.7k" V 4584 4250 50 0000 C CNN
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F 2 "Resistor_SMD:R_0603_1608Metric_Pad0.98x0.95mm_HandSolder" V 4630 4250 50 0001 C CNN
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F 3 "~" H 4700 4250 50 0001 C CNN
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1 4700 4250
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0 1 1 0
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$EndComp
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Wire Wire Line
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4550 4250 4450 4250
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Wire Wire Line
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4850 4250 5000 4250
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Text GLabel 5000 4400 3 50 Input ~ 0
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EMERG_SHDN
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Wire Wire Line
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5000 4400 5000 4250
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Connection ~ 5000 4250
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Wire Wire Line
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5000 4250 5750 4250
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NoConn ~ 6750 3350
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NoConn ~ 5750 3350
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Wire Wire Line
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4900 3100 5050 3100
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Text GLabel 5050 3100 2 50 Input ~ 0
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Vdcflt
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NoConn ~ 5750 3450
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$EndSCHEMATC
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