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fix jtag_read_reg and jtag_write_reg functions according to the documentation: SLAU320 MSP430 Programming via JTAG User's Guide 

tclk set and clr was in wrong order
This commit is contained in:
iddq 2020-06-01 06:56:52 +02:00
parent 493f38bb85
commit 0c5f33ec42
1 changed files with 15 additions and 17 deletions
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30
drivers/jtaglib.c
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@ -30,6 +30,8 @@
* jtag_write_reg corrected * jtag_write_reg corrected
* 2015-02-21 jtag_set_breakpoint added Peter Bägel (DF5EQ) * 2015-02-21 jtag_set_breakpoint added Peter Bägel (DF5EQ)
* jtag_cpu_state added * jtag_cpu_state added
* 2020-06-01 jtag_read_reg corrected Gabor Mayer (HG5OAP)
* jtag_write_reg corrected
*/ */
#include <stdlib.h> #include <stdlib.h>
@ -953,23 +955,23 @@ address_t jtag_read_reg(struct jtdev *p, int reg)
{ {
unsigned int value; unsigned int value;
/* Set CPU into instruction fetch mode */
jtag_set_instruction_fetch(p);
/* CPU controls RW & BYTE */ /* CPU controls RW & BYTE */
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
jtag_dr_shift_16(p, 0x3401); jtag_dr_shift_16(p, 0x3401);
/* Set CPU into instruction fetch mode */
jtag_set_instruction_fetch(p);
jtag_ir_shift(p, IR_DATA_16BIT); jtag_ir_shift(p, IR_DATA_16BIT);
/* "jmp $-4" instruction */ /* "jmp $-4" instruction */
/* PC - 4 -> PC */ /* PC - 4 -> PC */
/* needs 2 clock cycles */ /* needs 2 clock cycles */
jtag_dr_shift_16(p, 0x3ffd); jtag_dr_shift_16(p, 0x3ffd);
jtag_tclk_set(p);
jtag_tclk_clr(p); jtag_tclk_clr(p);
jtag_tclk_set(p); jtag_tclk_set(p);
jtag_tclk_clr(p); jtag_tclk_clr(p);
jtag_tclk_set(p);
/* "mov Rn,&0x01fe" instruction /* "mov Rn,&0x01fe" instruction
* Rn -> &0x01fe * Rn -> &0x01fe
@ -979,15 +981,15 @@ address_t jtag_read_reg(struct jtdev *p, int reg)
* the registers value is placed on the databus * the registers value is placed on the databus
*/ */
jtag_dr_shift_16(p, 0x4082 | (((unsigned int)reg << 8) & 0x0f00) ); jtag_dr_shift_16(p, 0x4082 | (((unsigned int)reg << 8) & 0x0f00) );
jtag_tclk_set(p);
jtag_tclk_clr(p); jtag_tclk_clr(p);
jtag_tclk_set(p);
jtag_dr_shift_16(p, 0x01fe); jtag_dr_shift_16(p, 0x01fe);
jtag_tclk_set(p);
jtag_tclk_clr(p); jtag_tclk_clr(p);
jtag_tclk_set(p); jtag_tclk_set(p);
jtag_tclk_clr(p); jtag_tclk_clr(p);
jtag_tclk_set(p); jtag_tclk_set(p);
jtag_tclk_clr(p); jtag_tclk_clr(p);
jtag_tclk_set(p);
/* Read databus which contains the registers value */ /* Read databus which contains the registers value */
jtag_ir_shift(p, IR_DATA_CAPTURE); jtag_ir_shift(p, IR_DATA_CAPTURE);
@ -997,8 +999,6 @@ address_t jtag_read_reg(struct jtdev *p, int reg)
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
jtag_dr_shift_16(p, 0x2401); jtag_dr_shift_16(p, 0x2401);
jtag_tclk_set(p);
/* Return value read from register */ /* Return value read from register */
return value; return value;
} }
@ -1006,23 +1006,23 @@ address_t jtag_read_reg(struct jtdev *p, int reg)
/* Writes a value into a register of the target CPU */ /* Writes a value into a register of the target CPU */
void jtag_write_reg(struct jtdev *p, int reg, address_t value) void jtag_write_reg(struct jtdev *p, int reg, address_t value)
{ {
/* Set CPU into instruction fetch mode */
jtag_set_instruction_fetch(p);
/* CPU controls RW & BYTE */ /* CPU controls RW & BYTE */
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
jtag_dr_shift_16(p, 0x3401); jtag_dr_shift_16(p, 0x3401);
/* Set CPU into instruction fetch mode */
jtag_set_instruction_fetch(p);
jtag_ir_shift(p, IR_DATA_16BIT); jtag_ir_shift(p, IR_DATA_16BIT);
/* "jmp $-4" instruction */ /* "jmp $-4" instruction */
/* PC - 4 -> PC */ /* PC - 4 -> PC */
/* needs 4 clock cycles */ /* needs 4 clock cycles */
jtag_dr_shift_16(p, 0x3ffd); jtag_dr_shift_16(p, 0x3ffd);
jtag_tclk_set(p);
jtag_tclk_clr(p); jtag_tclk_clr(p);
jtag_tclk_set(p); jtag_tclk_set(p);
jtag_tclk_clr(p); jtag_tclk_clr(p);
jtag_tclk_set(p);
/* "mov #value,Rn" instruction /* "mov #value,Rn" instruction
* value -> Rn * value -> Rn
@ -1030,17 +1030,15 @@ void jtag_write_reg(struct jtdev *p, int reg, address_t value)
* needs 2 clock cycles * needs 2 clock cycles
*/ */
jtag_dr_shift_16(p, 0x4030 | (reg & 0x000f) ); jtag_dr_shift_16(p, 0x4030 | (reg & 0x000f) );
jtag_tclk_set(p);
jtag_tclk_clr(p); jtag_tclk_clr(p);
jtag_tclk_set(p);
jtag_dr_shift_16(p, value); jtag_dr_shift_16(p, value);
jtag_tclk_set(p);
jtag_tclk_clr(p); jtag_tclk_clr(p);
jtag_tclk_set(p);
/* JTAG controls RW & BYTE */ /* JTAG controls RW & BYTE */
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT); jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
jtag_dr_shift_16(p, 0x2401); jtag_dr_shift_16(p, 0x2401);
jtag_tclk_set(p);
} }
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/