Merge pull request #56 from tgtakaoka/update-chipinfo-slac460y

Update chipinfo.db with slac460y

chipinfo.db

@@ -1,6 +1,6 @@
 /* MSP430 chip database
  *
- * THIS FILE WAS GENERATED FROM MSP430.DLL v3.12.0.604
+ * THIS FILE WAS GENERATED FROM MSP430.DLL v3.13.0.601
  *
  * Copyright (C) 2011 - 2018 Texas Instruments Incorporated - http://www.ti.com/
  *
@@ -34,10 +34,10 @@
  */
 
 #define CI_DLL430_VERSION_MAJOR 3
-#define CI_DLL430_VERSION_MINOR 12
+#define CI_DLL430_VERSION_MINOR 13
 #define CI_DLL430_VERSION_PATCH 0
-#define CI_DLL430_VERSION_BUILD 604
+#define CI_DLL430_VERSION_BUILD 601
-#define CI_DLL430_VERSION_STRING "3.12.0.604"
+#define CI_DLL430_VERSION_STRING "3.13.0.601"
 
 static const struct chipinfo_funclet erase_xv2_fr41xx = {
 	.code_size	= 42,
@@ -89769,6 +89769,446 @@ const struct chipinfo chipinfo_db[] = {	{
 		},
 	},
 
+	{
+		.name		= "MSP430FR2355",
+		.bits		= 20,
+		.psa		= CHIPINFO_PSA_REGULAR,
+		.clock_control	= 0x02,
+		.mclk_control	= 0x000000fc,
+		.clock_map	= {
+			{"ADC", 0xd8},
+			{"PORT", 0x50},
+			{"Comparator E0", 0xa9},
+			{"Comparator E1", 0xaa},
+			{"eUSCIA0", 0x2c},
+			{"eUSCIA1", 0x2d},
+			{"eUSCIB0", 0x30},
+			{"eUSCIB1", 0x31},
+			{"RTC", 0x8a},
+			{"Timer0_B3", 0x97},
+			{"Timer1_B3", 0x98},
+			{"Timer2_B3", 0x99},
+			{"Timer3_B7", 0x9d},
+			{"Watchdog Timer", 0x0a},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+		},
+		.id		= {
+			.ver_id		= 0x830c,
+			.ver_sub_id	= 0x0000,
+			.revision	= 0x00,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.id_mask		= {
+			.ver_id		= 0xffff,
+			.ver_sub_id	= 0xffff,
+			.revision	= 0xff,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.eem		= { /* no info */ },
+		.voltage	= {
+			.vcc_min	= 1800,
+			.vcc_max	= 3600,
+			.vcc_flash_min	= 1800,
+			.vcc_secure_min	= 2500,
+			.vpp_secure_min	= 6000,
+			.vpp_secure_max	= 7000,
+			.has_test_vpp	= 1,
+		},
+		.v3_functions	= {
+			[0x09]	= 0x39,
+			[0x12]	= 0x3a,
+			[0x13]	= 0x3b,
+			[0x14]	= 0x3c,
+			[0x15]	= 0x3d,
+			[0x16]	= 0x3d,
+			[0x17]	= 0x3e,
+			[0x18]	= 0x3f,
+			[0x19]	= 0x3f,
+			[0x1a]	= 0x40,
+			[0x1c]	= 0x41,
+			[0x1d]	= 0x42,
+			[0x1e]	= 0x43,
+			[0x1f]	= 0x44,
+			[0x20]	= 0x45,
+			[0x26]	= 0x37,
+			[0x4a]	= 0x4b,
+			[0x4e]	= 0x3f,
+		},
+		.v3_erase	= &erase_xv2_fr41xx,
+		.v3_write	= &write_xv2_fram,
+		.clock_sys	= CHIPINFO_CLOCK_SYS_MOD_OSC,
+		.features	= 0
+			| CHIPINFO_FEATURE_LCFE
+			| CHIPINFO_FEATURE_QUICK_MEM_READ
+			| CHIPINFO_FEATURE_FRAM,
+		.power		= {
+			.reg_mask		= 0x10018,
+			.enable_lpm5		= 0x00018,
+			.disable_lpm5		= 0x00018,
+			.reg_mask_3v		= 0x04020,
+			.enable_lpm5_3v		= 0x04020,
+			.disable_lpm5_3v	= 0x04020,
+		},
+		.memory		= {
+			{
+				.name		= "Bsl2",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 1024,
+				.offset		= 0xffc00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Lib",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 20480,
+				.offset		= 0xfac00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Main",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 32768,
+				.offset		= 0x08000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Ram",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 4096,
+				.offset		= 0x02000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "BootCode",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 1536,
+				.offset		= 0x01a00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Info",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 512,
+				.offset		= 0x01800,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Bsl",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x01000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Peripheral16bit2",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 4064,
+				.offset		= 0x00020,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "TinyRam",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 26,
+				.offset		= 0x00006,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Peripheral16bit",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 6,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{0}
+		},
+	},
+
+	{
+		.name		= "MSP430FR2353",
+		.bits		= 20,
+		.psa		= CHIPINFO_PSA_REGULAR,
+		.clock_control	= 0x02,
+		.mclk_control	= 0x000000fc,
+		.clock_map	= {
+			{"ADC", 0xd8},
+			{"PORT", 0x50},
+			{"Comparator E0", 0xa9},
+			{"Comparator E1", 0xaa},
+			{"eUSCIA0", 0x2c},
+			{"eUSCIA1", 0x2d},
+			{"eUSCIB0", 0x30},
+			{"eUSCIB1", 0x31},
+			{"RTC", 0x8a},
+			{"Timer0_B3", 0x97},
+			{"Timer1_B3", 0x98},
+			{"Timer2_B3", 0x99},
+			{"Timer3_B7", 0x9d},
+			{"Watchdog Timer", 0x0a},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+		},
+		.id		= {
+			.ver_id		= 0x830d,
+			.ver_sub_id	= 0x0000,
+			.revision	= 0x00,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.id_mask		= {
+			.ver_id		= 0xffff,
+			.ver_sub_id	= 0xffff,
+			.revision	= 0xff,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.eem		= { /* no info */ },
+		.voltage	= {
+			.vcc_min	= 1800,
+			.vcc_max	= 3600,
+			.vcc_flash_min	= 1800,
+			.vcc_secure_min	= 2500,
+			.vpp_secure_min	= 6000,
+			.vpp_secure_max	= 7000,
+			.has_test_vpp	= 1,
+		},
+		.v3_functions	= {
+			[0x09]	= 0x39,
+			[0x12]	= 0x3a,
+			[0x13]	= 0x3b,
+			[0x14]	= 0x3c,
+			[0x15]	= 0x3d,
+			[0x16]	= 0x3d,
+			[0x17]	= 0x3e,
+			[0x18]	= 0x3f,
+			[0x19]	= 0x3f,
+			[0x1a]	= 0x40,
+			[0x1c]	= 0x41,
+			[0x1d]	= 0x42,
+			[0x1e]	= 0x43,
+			[0x1f]	= 0x44,
+			[0x20]	= 0x45,
+			[0x26]	= 0x37,
+			[0x4a]	= 0x4b,
+			[0x4e]	= 0x3f,
+		},
+		.v3_erase	= &erase_xv2_fr41xx,
+		.v3_write	= &write_xv2_fram,
+		.clock_sys	= CHIPINFO_CLOCK_SYS_MOD_OSC,
+		.features	= 0
+			| CHIPINFO_FEATURE_LCFE
+			| CHIPINFO_FEATURE_QUICK_MEM_READ
+			| CHIPINFO_FEATURE_FRAM,
+		.power		= {
+			.reg_mask		= 0x10018,
+			.enable_lpm5		= 0x00018,
+			.disable_lpm5		= 0x00018,
+			.reg_mask_3v		= 0x04020,
+			.enable_lpm5_3v		= 0x04020,
+			.disable_lpm5_3v	= 0x04020,
+		},
+		.memory		= {
+			{
+				.name		= "Bsl2",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 1024,
+				.offset		= 0xffc00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Lib",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 20480,
+				.offset		= 0xfac00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Main",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 16384,
+				.offset		= 0x0c000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Ram",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x02000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "BootCode",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 1536,
+				.offset		= 0x01a00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Info",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 512,
+				.offset		= 0x01800,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Bsl",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x01000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Peripheral16bit2",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 4064,
+				.offset		= 0x00020,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "TinyRam",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 26,
+				.offset		= 0x00006,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Peripheral16bit",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 6,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{0}
+		},
+	},
+
 	{
 		.name		= "MSP430FR50431",
 		.bits		= 20,
@@ -91776,6 +92216,446 @@ const struct chipinfo chipinfo_db[] = {	{
 		},
 	},
 
+	{
+		.name		= "MSP430FR2153",
+		.bits		= 20,
+		.psa		= CHIPINFO_PSA_REGULAR,
+		.clock_control	= 0x02,
+		.mclk_control	= 0x000000fc,
+		.clock_map	= {
+			{"ADC", 0xd8},
+			{"PORT", 0x50},
+			{"Comparator E0", 0xa9},
+			{"Comparator E1", 0xaa},
+			{"eUSCIA0", 0x2c},
+			{"eUSCIA1", 0x2d},
+			{"eUSCIB0", 0x30},
+			{"eUSCIB1", 0x31},
+			{"RTC", 0x8a},
+			{"Timer0_B3", 0x97},
+			{"Timer1_B3", 0x98},
+			{"Timer2_B3", 0x99},
+			{"Timer3_B7", 0x9d},
+			{"Watchdog Timer", 0x0a},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+		},
+		.id		= {
+			.ver_id		= 0x831d,
+			.ver_sub_id	= 0x0000,
+			.revision	= 0x00,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.id_mask		= {
+			.ver_id		= 0xffff,
+			.ver_sub_id	= 0xffff,
+			.revision	= 0xff,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.eem		= { /* no info */ },
+		.voltage	= {
+			.vcc_min	= 1800,
+			.vcc_max	= 3600,
+			.vcc_flash_min	= 1800,
+			.vcc_secure_min	= 2500,
+			.vpp_secure_min	= 6000,
+			.vpp_secure_max	= 7000,
+			.has_test_vpp	= 1,
+		},
+		.v3_functions	= {
+			[0x09]	= 0x39,
+			[0x12]	= 0x3a,
+			[0x13]	= 0x3b,
+			[0x14]	= 0x3c,
+			[0x15]	= 0x3d,
+			[0x16]	= 0x3d,
+			[0x17]	= 0x3e,
+			[0x18]	= 0x3f,
+			[0x19]	= 0x3f,
+			[0x1a]	= 0x40,
+			[0x1c]	= 0x41,
+			[0x1d]	= 0x42,
+			[0x1e]	= 0x43,
+			[0x1f]	= 0x44,
+			[0x20]	= 0x45,
+			[0x26]	= 0x37,
+			[0x4a]	= 0x4b,
+			[0x4e]	= 0x3f,
+		},
+		.v3_erase	= &erase_xv2_fr41xx,
+		.v3_write	= &write_xv2_fram,
+		.clock_sys	= CHIPINFO_CLOCK_SYS_MOD_OSC,
+		.features	= 0
+			| CHIPINFO_FEATURE_LCFE
+			| CHIPINFO_FEATURE_QUICK_MEM_READ
+			| CHIPINFO_FEATURE_FRAM,
+		.power		= {
+			.reg_mask		= 0x10018,
+			.enable_lpm5		= 0x00018,
+			.disable_lpm5		= 0x00018,
+			.reg_mask_3v		= 0x04020,
+			.enable_lpm5_3v		= 0x04020,
+			.disable_lpm5_3v	= 0x04020,
+		},
+		.memory		= {
+			{
+				.name		= "Bsl2",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 1024,
+				.offset		= 0xffc00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Lib",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 20480,
+				.offset		= 0xfac00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Main",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 16384,
+				.offset		= 0x0c000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Ram",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x02000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "BootCode",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 1536,
+				.offset		= 0x01a00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Info",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 512,
+				.offset		= 0x01800,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Bsl",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x01000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Peripheral16bit2",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 4064,
+				.offset		= 0x00020,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "TinyRam",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 26,
+				.offset		= 0x00006,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Peripheral16bit",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 6,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{0}
+		},
+	},
+
+	{
+		.name		= "MSP430FR2155",
+		.bits		= 20,
+		.psa		= CHIPINFO_PSA_REGULAR,
+		.clock_control	= 0x02,
+		.mclk_control	= 0x000000fc,
+		.clock_map	= {
+			{"ADC", 0xd8},
+			{"PORT", 0x50},
+			{"Comparator E0", 0xa9},
+			{"Comparator E1", 0xaa},
+			{"eUSCIA0", 0x2c},
+			{"eUSCIA1", 0x2d},
+			{"eUSCIB0", 0x30},
+			{"eUSCIB1", 0x31},
+			{"RTC", 0x8a},
+			{"Timer0_B3", 0x97},
+			{"Timer1_B3", 0x98},
+			{"Timer2_B3", 0x99},
+			{"Timer3_B7", 0x9d},
+			{"Watchdog Timer", 0x0a},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+			{0},
+		},
+		.id		= {
+			.ver_id		= 0x831e,
+			.ver_sub_id	= 0x0000,
+			.revision	= 0x00,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.id_mask		= {
+			.ver_id		= 0xffff,
+			.ver_sub_id	= 0xffff,
+			.revision	= 0xff,
+			.fab		= 0x00,
+			.self		= 0x0000,
+			.config		= 0x00,
+			.fuses		= 0x00,
+			.activation_key	= 0x00000000,
+		},
+		.eem		= { /* no info */ },
+		.voltage	= {
+			.vcc_min	= 1800,
+			.vcc_max	= 3600,
+			.vcc_flash_min	= 1800,
+			.vcc_secure_min	= 2500,
+			.vpp_secure_min	= 6000,
+			.vpp_secure_max	= 7000,
+			.has_test_vpp	= 1,
+		},
+		.v3_functions	= {
+			[0x09]	= 0x39,
+			[0x12]	= 0x3a,
+			[0x13]	= 0x3b,
+			[0x14]	= 0x3c,
+			[0x15]	= 0x3d,
+			[0x16]	= 0x3d,
+			[0x17]	= 0x3e,
+			[0x18]	= 0x3f,
+			[0x19]	= 0x3f,
+			[0x1a]	= 0x40,
+			[0x1c]	= 0x41,
+			[0x1d]	= 0x42,
+			[0x1e]	= 0x43,
+			[0x1f]	= 0x44,
+			[0x20]	= 0x45,
+			[0x26]	= 0x37,
+			[0x4a]	= 0x4b,
+			[0x4e]	= 0x3f,
+		},
+		.v3_erase	= &erase_xv2_fr41xx,
+		.v3_write	= &write_xv2_fram,
+		.clock_sys	= CHIPINFO_CLOCK_SYS_MOD_OSC,
+		.features	= 0
+			| CHIPINFO_FEATURE_LCFE
+			| CHIPINFO_FEATURE_QUICK_MEM_READ
+			| CHIPINFO_FEATURE_FRAM,
+		.power		= {
+			.reg_mask		= 0x10018,
+			.enable_lpm5		= 0x00018,
+			.disable_lpm5		= 0x00018,
+			.reg_mask_3v		= 0x04020,
+			.enable_lpm5_3v		= 0x04020,
+			.disable_lpm5_3v	= 0x04020,
+		},
+		.memory		= {
+			{
+				.name		= "Bsl2",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 1024,
+				.offset		= 0xffc00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Lib",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 20480,
+				.offset		= 0xfac00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Main",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 32768,
+				.offset		= 0x08000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Ram",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 4096,
+				.offset		= 0x02000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "BootCode",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 1536,
+				.offset		= 0x01a00,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Info",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 512,
+				.offset		= 0x01800,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Bsl",
+				.type		= CHIPINFO_MEMTYPE_ROM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 2048,
+				.offset		= 0x01000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Peripheral16bit2",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 4064,
+				.offset		= 0x00020,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "TinyRam",
+				.type		= CHIPINFO_MEMTYPE_RAM,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 26,
+				.offset		= 0x00006,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{
+				.name		= "Peripheral16bit",
+				.type		= CHIPINFO_MEMTYPE_REGISTER,
+				.bits		= 16,
+				.mapped		= 1,
+				.size		= 6,
+				.offset		= 0x00000,
+				.seg_size	= 1,
+				.bank_size	= 0 /* no info */,
+				.banks		= 1,
+			},
+			{0}
+		},
+	},
+
 	{
 		.name		= "MSP430FR2100",
 		.bits		= 20,