Merge pull request #90 from Mauroq/master
Support files for FR5994 (Launchpad) and FR5964
This commit is contained in:
Daniel Beer
GitHub
commit
b506542094
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@ -315,6 +315,17 @@ const struct device_table sdeviceID[] =
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{{0x41, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5229, "MSP430F5213"}, // MSP430F5529
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{{0x40, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5229, "MSP430F5212"}, // MSP430F5529
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{{0x29, 0x55, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430G2955, "MSP430G2955"},
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{{0x03, 0x82, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430F5255, "MSP430F5255"}, // MSP430F5255
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{{0x5F, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5947, "MSP430FR5947"}, // MSP430FR5947
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{{0x60, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5948, "MSP430FR5948"}, // MSP430FR5948
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{{0x61, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5949, "MSP430FR5949"}, // MSP430FR5949
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{{0x63, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5957, "MSP430FR5957"}, // MSP430FR5957
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{{0x64, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5958, "MSP430FR5958"}, // MSP430FR5958
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{{0x65, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5959, "MSP430FR5959"}, // MSP430FR5959
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{{0x67, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5967, "MSP430FR5967"}, // MSP430FR5967
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{{0x68, 0x81, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5968, "MSP430FR5968"}, // MSP430FR5968
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{{0xA1, 0x82, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5994, "MSP430FR5994"}, // MSP430FR5994
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{{0xA4, 0x82, -1 , -1 , -1 , -1 , -1 , -1 , -1 }, DT_MSP430FR5964, "MSP430FR5964"}, // MSP430FR5964
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// end of device table default return value
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{{ 0 , -1 , -1 , -1 , -1 , -1 , -1 , -1 , -1 }, -1, NULL}
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};
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@ -310,6 +310,17 @@ typedef enum {
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DT_MSP430F5213,
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DT_MSP430F5212,
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DT_MSP430G2955,
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DT_MSP430F5255,
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DT_MSP430FR5947,
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DT_MSP430FR5948,
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DT_MSP430FR5949,
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DT_MSP430FR5957,
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DT_MSP430FR5958,
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DT_MSP430FR5959,
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DT_MSP430FR5967,
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DT_MSP430FR5968,
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DT_MSP430FR5994,
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DT_MSP430FR5964
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} devicetype_t;
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/* Mapping between device types and identification bytes. */
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258
drivers/fet_db.c
258
drivers/fet_db.c
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@ -38263,6 +38263,264 @@ static const struct fet_db_record fet_db[] = {{ .name= "Prototype_MSP430F
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#endif
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},
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{ .name= "MSP430FR5994" /* database IDX F2*/
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, .msg28_data= { 0xA1, 0x82 /* ID (off: 0)*/
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, 0xFF /* REV (off: 2)*/
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, 0xFF /* FAB (off: 3)*/
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, 0x00, 0x00, 0x00, 0x00
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, 0xFF /* SELF0 (off: 8)*/
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, 0xFF /* SELF1 (off: 9)*/
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, 0x00, 0x00, 0x00
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, 0xFF /* CONF (off: 13)*/
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, 0x00, 0x00
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, 0xFF /* FUSES (off: 16)*/
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, 0xFF } /* F PATT (off: 17)*/
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, .msg29_params={ 0x00, 0x209, 0xEA /*, 0x4A */ }
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, .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x04, 0x00 /* off: 0 ROM */
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, 0x00, 0x18, 0xFF, 0x19, 0x00, 0x00 /* off: 6 INFO */
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, 0x00, 0x1C, 0xFF, 0x2B /* off: 12 RAM */
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, 0x00, 0x2C, 0xFF, 0x3B /* off: 16 RAM2 (placed LEA ram here)*/
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, 0x03, 0x00 /* off: 20 Breakpoints */
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, 0x05, 0x00 /* off: 22 Emulation */
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, 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/
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, 0x0F, 0x04 /* off: 26 Id devices */
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, 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */
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, 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */
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, 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */
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, 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */
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, 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */
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, 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */
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, 0x01, 0x00 /* off: 42 Has test Vpp*/
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, 0x03, 0x00 /* off: 44 3-> Default clock control */
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0xFF, 0x00 /* SET */
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, 0xFF, 0x00 /* SET */
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, 0xFF, 0x00 /* SET */}
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, .msg2b_len= 0x4A
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, .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */
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, 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */
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, 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */
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, ETWPID_WDT_A , ETWPID_TMR3_A2
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, ETWPID_TMR1_A2, ETWPID_TA3_1
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, ETWPID_TA3_0 , ETWPID_TMR0_B7
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, ETWPID_USCIA1 , ETWPID_USCIA0
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, ETWPID_USCIB0 , ETWPID_EMPTY
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, ETWPID_RTC , ETWPID_ADC12_A
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, ETWPID_COMP_B , ETWPID_AES128
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, ETWPID_EMPTY , ETWPID_EMPTY
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, 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x00, 0x00
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00 }
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#ifdef MSP430_STORED_INFO
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, .endian = 0xAA55 /* The value 0xaa55. */
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, .id = 0x209 /* Identification number.*/
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, .string = "MSP430FR5994"
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, .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/
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, .coreIpId = 0x0000 /* The CoreIP ID.*/
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, .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/
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, .mainStart = 0x4000, .mainEnd = 0x43FFF /* MAIN Memory range */
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, .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */
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, .ramStart = 0x1C00, .ramEnd = 0x2BFF /* RAM Memory range.*/
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, .ram2Start = 0x2C00, .ram2End = 0x3BFF /* RAM Memory range.*//* LEA? */
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, .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/
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, .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/
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, .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/
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, .hasFramMemory = 1 /* FRAM Memory type */
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, .hasTestVpp = 1 /* Device has TEST/VPP.*/
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, .nBreakpoints = 3 /* Number of breakpoints.*/
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, .nRegTrigger = 1 /* Number of CPU Register Trigger.*/
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, .nCombinations = 4 /* Number of EEM Trigger Combinations.*/
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, .nBreakOps = 1 /* Breakpoint Modes*/
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, .nBreakRdWr = 1
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, .nBreakRdDma = 1
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, .TrigerMask = 1 /* Trigger Mask for Breakpoint */
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, .nRegTriggerMod= 1 /* Register Trigger modes*/
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, .nStateStorage = 0 /* MSP430 has Stage Storage*/
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, .nCycleCount = 1 /* Number of cycle counters of MSP430*/
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, .nCycleCountOps= 1 /* Cycle couter modes*/
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, .nSequencer = 0 /* Msp430 has Sequencer*/
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, .clockControl = 2 /* Clock control level.*/
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, .emulation = 0x0005 /* Emulation level.*/
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, .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/
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, .eemVersion = 0x2800 /* The EEM Version Number.*/
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#endif
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},
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{ .name= "MSP430FR5964" /* database IDX F2*/
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, .msg28_data= { 0xA4, 0x82 /* ID (off: 0)*/
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, 0xFF /* REV (off: 2)*/
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, 0xFF /* FAB (off: 3)*/
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, 0x00, 0x00, 0x00, 0x00
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, 0xFF /* SELF0 (off: 8)*/
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, 0xFF /* SELF1 (off: 9)*/
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, 0x00, 0x00, 0x00
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, 0xFF /* CONF (off: 13)*/
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, 0x00, 0x00
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, 0xFF /* FUSES (off: 16)*/
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, 0xFF } /* F PATT (off: 17)*/
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, .msg29_params={ 0x00, 0x20A, 0xEA /*, 0x4A */ }
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, .msg29_data={ 0x00, 0x40, 0xFF, 0x3F, 0x04, 0x00 /* off: 0 ROM */
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, 0x00, 0x18, 0xFF, 0x19, 0x00, 0x00 /* off: 6 INFO */
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, 0x00, 0x1C, 0xFF, 0x3B /* off: 12 RAM */
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, 0x00, 0x00, 0x03, 0x00 /* off: 16 RAM2 */
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, 0x03, 0x00 /* off: 20 Breakpoints */
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, 0x05, 0x00 /* off: 22 Emulation */
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, 0x02, 0x00 /* off: 24 GCC (0200 -> extended )*/
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, 0x0F, 0x04 /* off: 26 Id devices */
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, 0x00, 0x00, 0x00, 0x00 /* off: 28 LCD MEM */
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, 0x08, 0x07 /* off: 32 Vcc 0 : 1800 */
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, 0x10, 0x0E /* off: 34 Vcc 1 : 3600 */
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, 0xC4, 0x09 /* off: 36 Vcc 2 : 2500 */
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, 0x70, 0x17 /* off: 38 Vcc 3 : 6000 */
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, 0x58, 0x1B /* off: 40 Vcc 4 : 7000 */
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, 0x01, 0x00 /* off: 42 Has test Vpp*/
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, 0x03, 0x00 /* off: 44 3-> Default clock control */
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0xFF, 0x00 /* SET */
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, 0xFF, 0x00 /* SET */
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, 0xFF, 0x00 /* SET */}
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, .msg2b_len= 0x4A
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, .msg2b_data= { 0x00, 0x10, 0xFF, 0x17, 0x00 /* off: 0 info org, len, banks */
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, 0x00, 0x01, 0x00, 0x04, 0x00 /* off: 5 ram org, len, banks */
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, 0x00, 0x00 /* off: 10 BYTE FLAGS ?? */
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, ETWPID_WDT_A , ETWPID_TMR3_A2
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, ETWPID_TMR1_A2, ETWPID_TA3_1
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, ETWPID_TA3_0 , ETWPID_TMR0_B7
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, ETWPID_USCIA1 , ETWPID_USCIA0
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, ETWPID_USCIB0 , ETWPID_EMPTY
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, ETWPID_RTC , ETWPID_ADC12_A
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, ETWPID_COMP_B , ETWPID_AES128
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, ETWPID_EMPTY , ETWPID_EMPTY
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, 0x01, 0x00, 0x01, 0x01 /* off: 28 BYTE FLAGS ?? */
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x00, 0x00
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, 0x01, 0x00 /* SET */
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, 0x01, 0x00 /* SET */
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00
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, 0x00, 0x00 }
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#ifdef MSP430_STORED_INFO
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, .endian = 0xAA55 /* The value 0xaa55. */
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, .id = 0x20A /* Identification number.*/
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, .string = "MSP430FR5964"
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, .cpuArch = 0x0000 /* The MSP430 architecture (non-X, X or Xv2).*/
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, .coreIpId = 0x0000 /* The CoreIP ID.*/
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, .deviceIdPtr= 0x24263F /* The Device-ID Pointer.*/
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, .mainStart = 0x4000, .mainEnd = 0x43FFF /* MAIN Memory range */
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, .infoStart = 0x1800, .infoEnd = 0x19FF /* INFO Memory range */
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, .ramStart = 0x1C00, .ramEnd = 0x3BFF /* RAM Memory range.*/
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, .ram2Start = 0x0000, .ram2End = 0x0000 /* RAM Memory range.*/
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, .lcdStart = 0x0000, .lcdEnd = 0x0000 /* LCD Memory range.*/
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, .bslStart = 0x1000, .bslEnd = 0x17FF /* BSL Memory range.*/
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, .vccMinOp = 0x0708, .vccMaxOp= 0x0E10 /* Vcc range during operation [mVolts].*/
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, .hasFramMemory = 1 /* FRAM Memory type */
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, .hasTestVpp = 1 /* Device has TEST/VPP.*/
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, .nBreakpoints = 3 /* Number of breakpoints.*/
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, .nRegTrigger = 1 /* Number of CPU Register Trigger.*/
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, .nCombinations = 4 /* Number of EEM Trigger Combinations.*/
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, .nBreakOps = 1 /* Breakpoint Modes*/
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, .nBreakRdWr = 1
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, .nBreakRdDma = 1
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, .TrigerMask = 1 /* Trigger Mask for Breakpoint */
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, .nRegTriggerMod= 1 /* Register Trigger modes*/
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, .nStateStorage = 0 /* MSP430 has Stage Storage*/
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, .nCycleCount = 1 /* Number of cycle counters of MSP430*/
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, .nCycleCountOps= 1 /* Cycle couter modes*/
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, .nSequencer = 0 /* Msp430 has Sequencer*/
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, .clockControl = 2 /* Clock control level.*/
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, .emulation = 0x0005 /* Emulation level.*/
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, .jtagId = 0x0000 /* The JTAG ID - value returned on an instruction shift.*/
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, .eemVersion = 0x2800 /* The EEM Version Number.*/
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#endif
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},
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};
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