sys64738
/
mspdebug
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

v3hil now working properly with firmware versions 2.3.0.6, 3.8.0.2 and 3.12.0.0 of eZ-FET on EXP430FR5994

This commit is contained in:
Triss 2022-05-15 04:37:15 +02:00
parent fc79881203
commit b8ed9d7194
5 changed files with 164 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitignore vendored
View File

@ -4,3 +4,5 @@ mspdebug
mspdebug.exe mspdebug.exe
inst/ inst/
config.mk config.mk
*.pcapng
*.pcapng.gz

14
chipinfo.db
View File

@ -85042,20 +85042,10 @@ const struct chipinfo chipinfo_db[] = { {
{0}, {0},
{0}, {0},
}, },
/*.id = {
.ver_id = 0x82a1,
.ver_sub_id = 0x0000,
.revision = 0x10,
.fab = 0x00,
.self = 0x0000,
.config = 0x00,
.fuses = 0x00,
.activation_key = 0x00000000,
},*/
.id = { .id = {
.ver_id = 0x82a1, .ver_id = 0x82a1,
.ver_sub_id = 0x0000, .ver_sub_id = 0x0000,
.revision = 0x21, .revision = /*0x10*/0x21,
.fab = 0x00, .fab = 0x00,
.self = 0x0000, .self = 0x0000,
.config = 0x00, .config = 0x00,
@ -85094,7 +85084,7 @@ const struct chipinfo chipinfo_db[] = { {
[0x18] = 0x3f, [0x18] = 0x3f,
[0x19] = 0x3f, [0x19] = 0x3f,
[0x1a] = 0x40, [0x1a] = 0x40,
[0x1c] = 0x50, [0x1c] = /*0x50*/0x41,
[0x1d] = 0x42, [0x1d] = 0x42,
[0x1e] = 0x43, [0x1e] = 0x43,
[0x1f] = 0x44, [0x1f] = 0x44,

13
drivers/hal_proto.h
View File

@ -172,6 +172,19 @@ typedef enum {
HAL_PROTO_ERR_MAGIC_PATTERN = 0xFFBC, HAL_PROTO_ERR_MAGIC_PATTERN = 0xFFBC,
HAL_PROTO_ERR_MAGIC_PATTERN_BOOT_DATA_CRC_WRONG = 0xFFBB, HAL_PROTO_ERR_MAGIC_PATTERN_BOOT_DATA_CRC_WRONG = 0xFFBB,
HAL_PROTO_ERR_DAP_NACK = 0xFFBA, HAL_PROTO_ERR_DAP_NACK = 0xFFBA,
HAL_PROTO_MESSAGE_NO_RESPONSE = 0x8000,
HAL_PROTO_EXCEPTION_NOT_IMPLEMENT_ERR = 0x8001,
HAL_PROTO_EXCEPTION_MSGID_ERR = 0x8002,
HAL_PROTO_EXCEPTION_CRC_ERR = 0x8003,
HAL_PROTO_EXCEPTION_RX_TIMEOUT_ERR = 0x8004,
HAL_PROTO_EXCEPTION_TX_TIMEOUT_ERR = 0x8005,
HAL_PROTO_EXCEPTION_RX_OVERFLOW_ERR = 0x8006,
HAL_PROTO_EXCEPTION_TX_NO_BUFFER = 0x8007,
HAL_PROTO_EXCEPTION_COM_RESET = 0x8008,
HAL_PROTO_EXCEPTION_RX_NO_BUFFER = 0x8009,
HAL_PROTO_EXCEPTION_RX_TO_SMALL_BUFFER = 0x800A,
HAL_PROTO_EXCEPTION_RX_LENGTH = 0x800B,
} hal_proto_error_t; } hal_proto_error_t;
#define HAL_MAX_PAYLOAD 253 #define HAL_MAX_PAYLOAD 253

201
drivers/v3hil.c
View File

@ -25,12 +25,11 @@
#include "output.h" #include "output.h"
#include "opdb.h" #include "opdb.h"
/*map: 1e -> 43 #ifdef DEBUG_V3HIL
map: 14 -> 3c*/ #define dbg_printc(fmt, ...) printc_dbg("v3hil: " fmt, ##__VA_ARGS__)
/* tilib: #else
* 3f; 43; 40; 3c; 04; 3b; 42; 40; 3d; 3f; 5a; 40...; 07...; 3f; 43; 40; 3c; #define dbg_printc(fmt, ...) do{}while(0)
* 06; HAL92 #endif
*/
/* HAL function IDs */ /* HAL function IDs */
typedef enum { typedef enum {
@ -65,8 +64,8 @@ typedef enum {
HAL_PROTO_FID_READ_ALL_CPU_REGS , HAL_PROTO_FID_READ_ALL_CPU_REGS ,
HAL_PROTO_FID_WRITE_ALL_CPU_REGS , HAL_PROTO_FID_WRITE_ALL_CPU_REGS ,
HAL_PROTO_FID_PSA , HAL_PROTO_FID_PSA ,
HAL_PROTO_FID_EXECUTE_FUNCLET , HAL_PROTO_FID_EXECUTE_FUNCLET , // 0x20
HAL_PROTO_FID_EXECUTE_FUNCLET_JTAG , // 0x20 HAL_PROTO_FID_EXECUTE_FUNCLET_JTAG ,
HAL_PROTO_FID_GET_DCO_FREQUENCY , HAL_PROTO_FID_GET_DCO_FREQUENCY ,
HAL_PROTO_FID_GET_DCO_FREQUENCY_JTAG , HAL_PROTO_FID_GET_DCO_FREQUENCY_JTAG ,
HAL_PROTO_FID_GET_FLL_FREQUENCY , HAL_PROTO_FID_GET_FLL_FREQUENCY ,
@ -82,8 +81,8 @@ typedef enum {
HAL_PROTO_FID_WRITE_MEM_WORDS_X , HAL_PROTO_FID_WRITE_MEM_WORDS_X ,
HAL_PROTO_FID_EEM_DX_X , HAL_PROTO_FID_EEM_DX_X ,
HAL_PROTO_FID_SINGLE_STEP_X , HAL_PROTO_FID_SINGLE_STEP_X ,
HAL_PROTO_FID_READ_ALL_CPU_REGS_X , // 0x30 HAL_PROTO_FID_READ_ALL_CPU_REGS_X ,
HAL_PROTO_FID_WRITE_ALL_CPU_REGS_X , HAL_PROTO_FID_WRITE_ALL_CPU_REGS_X , // 0x30
HAL_PROTO_FID_PSA_X , HAL_PROTO_FID_PSA_X ,
HAL_PROTO_FID_EXECUTE_FUNCLET_X , HAL_PROTO_FID_EXECUTE_FUNCLET_X ,
HAL_PROTO_FID_GET_DCO_FREQUENCY_X , HAL_PROTO_FID_GET_DCO_FREQUENCY_X ,
@ -97,8 +96,8 @@ typedef enum {
HAL_PROTO_FID_READ_MEM_WORDS_XV2 , HAL_PROTO_FID_READ_MEM_WORDS_XV2 ,
HAL_PROTO_FID_READ_MEM_QUICK_XV2 , HAL_PROTO_FID_READ_MEM_QUICK_XV2 ,
HAL_PROTO_FID_WRITE_MEM_WORDS_XV2 , HAL_PROTO_FID_WRITE_MEM_WORDS_XV2 ,
HAL_PROTO_FID_EEM_DX_XV2 , // 0x40 HAL_PROTO_FID_EEM_DX_XV2 ,
HAL_PROTO_FID_SINGLE_STEP_XV2 , HAL_PROTO_FID_SINGLE_STEP_XV2 , // 0x40
HAL_PROTO_FID_READ_ALL_CPU_REGS_XV2 , HAL_PROTO_FID_READ_ALL_CPU_REGS_XV2 ,
HAL_PROTO_FID_WRITE_ALL_CPU_REGS_XV2 , HAL_PROTO_FID_WRITE_ALL_CPU_REGS_XV2 ,
HAL_PROTO_FID_PSA_XV2 , HAL_PROTO_FID_PSA_XV2 ,
@ -113,9 +112,9 @@ typedef enum {
HAL_PROTO_FID_RESET_XV2 , HAL_PROTO_FID_RESET_XV2 ,
HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2 , HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2 ,
HAL_PROTO_FID_SEND_JTAG_MAILBOX_XV2 , HAL_PROTO_FID_SEND_JTAG_MAILBOX_XV2 ,
HAL_PROTO_FID_SINGLE_STEP_JSTATE_XV2 , // 0x50 HAL_PROTO_FID_SINGLE_STEP_JSTATE_XV2 ,
HAL_PROTO_FID_POLL_JSTATE_REG_ET8 , HAL_PROTO_FID_POLL_JSTATE_REG_ET8 ,
HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS , HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS , // 0x50
HAL_PROTO_FID_RESET_430I , HAL_PROTO_FID_RESET_430I ,
HAL_PROTO_FID_POLL_JSTATE_REG_430I , HAL_PROTO_FID_POLL_JSTATE_REG_430I ,
HAL_PROTO_FID_POLL_JSTATE_REG_20 , HAL_PROTO_FID_POLL_JSTATE_REG_20 ,
@ -172,6 +171,18 @@ typedef enum {
HAL_PROTO_CONFIG_JTAG_LOCK_5XX = 0x17 HAL_PROTO_CONFIG_JTAG_LOCK_5XX = 0x17
} hal_proto_config_t; } hal_proto_config_t;
static hal_proto_fid_t map_ver(const struct v3hil *h, hal_proto_fid_t src) {
hal_proto_fid_t dst;
if (h->proto_ver < 0x0300 && src > HAL_PROTO_FID_GET_DEVICE_ID_PTR) {
dst = src - 1;
} else {
dst = src;
}
dbg_printc("map ver: %02x -> %02x\n", src, dst);
return dst;
}
static hal_proto_fid_t map_fid(const struct v3hil *h, hal_proto_fid_t src) static hal_proto_fid_t map_fid(const struct v3hil *h, hal_proto_fid_t src)
{ {
hal_proto_fid_t src2 = src, dst, dst2; hal_proto_fid_t src2 = src, dst, dst2;
@ -183,17 +194,13 @@ static hal_proto_fid_t map_fid(const struct v3hil *h, hal_proto_fid_t src)
dst = h->chip->v3_functions[src2]; dst = h->chip->v3_functions[src2];
if (dst) { if (dst) {
if (h->proto_ver == 3 && dst >= HAL_PROTO_FID_GET_DEVICE_ID_PTR && false) {
dst2 = dst + 1;
} else {
dst2 = dst; dst2 = dst;
}
} else { } else {
dst2 = src; dst2 = src;
} }
printc_err("map: %02x -> %02x\n", src, dst2); dbg_printc("map fid: %02x -> %02x\n", src, dst2);
return dst2; return map_ver(h, dst2);
} }
void v3hil_init(struct v3hil *h, transport_t trans, void v3hil_init(struct v3hil *h, transport_t trans,
@ -208,7 +215,8 @@ int v3hil_set_vcc(struct v3hil *h, int vcc_mv)
uint8_t data[2]; uint8_t data[2];
w16le(data, vcc_mv); w16le(data, vcc_mv);
return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_VCC, data, 2); dbg_printc("Setting VCC...\n");
return hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_SET_VCC), data, 2);
} }
int v3hil_comm_init(struct v3hil *h) int v3hil_comm_init(struct v3hil *h)
@ -224,11 +232,12 @@ int v3hil_comm_init(struct v3hil *h)
if (h->hal.length < 8) { if (h->hal.length < 8) {
printc_err("warning: v3hil: short reply to version request\n"); printc_err("warning: v3hil: short reply to version request\n");
} else if (h->hal.length == 40) { } else if (h->hal.length == 40) {
// TODO #ifdef DEBUG_V3HIL
/*printc_dbg("Version:"); printc_dbg("v3hil: Version:");
for (int i = 0; i < h->hal.length; i++) for (int i = 0; i < h->hal.length; i++)
printc_dbg(" %02x", h->hal.payload[i]); printc_dbg(" %02x", h->hal.payload[i]);
printc_dbg("\n");*/ printc_dbg("\n");
#endif
const uint16_t sw_version = r32le(h->hal.payload + 0); const uint16_t sw_version = r32le(h->hal.payload + 0);
const uint16_t sw_build = r32le(h->hal.payload + 2); const uint16_t sw_build = r32le(h->hal.payload + 2);
const uint32_t hw_thing = r32le(h->hal.payload + 4); const uint32_t hw_thing = r32le(h->hal.payload + 4);
@ -258,7 +267,7 @@ int v3hil_comm_init(struct v3hil *h)
major, minor, patch, build, major, minor, patch, build,
core_version, hil_version, hw_thing); core_version, hil_version, hw_thing);
h->proto_ver = major; h->proto_ver = (major << 8) | minor;
} else { } else {
const uint8_t major = h->hal.payload[1] >> 6; const uint8_t major = h->hal.payload[1] >> 6;
const uint8_t minor = h->hal.payload[1] & 0x3f; const uint8_t minor = h->hal.payload[1] & 0x3f;
@ -269,12 +278,12 @@ int v3hil_comm_init(struct v3hil *h)
major, minor, patch, flavour, major, minor, patch, flavour,
r32le(h->hal.payload + 4)); r32le(h->hal.payload + 4));
h->proto_ver = major; h->proto_ver = (major << 8) | minor;
} }
printc_dbg("Reset firmware...\n"); printc_dbg("Reset firmware...\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS, NULL, 0) < 0) map_ver(h, HAL_PROTO_FID_RESET_STATIC_GLOBAL_VARS), NULL, 0) < 0)
return -1; return -1;
return 0; return 0;
@ -285,7 +294,8 @@ int v3hil_start_jtag(struct v3hil *h, v3hil_jtag_type_t type)
uint8_t data = type; uint8_t data = type;
uint8_t chain_id[2] = {0, 0}; uint8_t chain_id[2] = {0, 0};
if (hal_proto_execute(&h->hal, HAL_PROTO_FID_START_JTAG, dbg_printc("Start JTAG...\n");
if (hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_START_JTAG),
&data, 1) < 0) &data, 1) < 0)
return -1; return -1;
@ -300,17 +310,17 @@ int v3hil_start_jtag(struct v3hil *h, v3hil_jtag_type_t type)
} }
printc_dbg("Device count: %d\n", h->hal.payload[0]); printc_dbg("Device count: %d\n", h->hal.payload[0]);
return hal_proto_execute(&h->hal, HAL_PROTO_FID_SET_DEVICE_CHAIN_INFO, return hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_SET_DEVICE_CHAIN_INFO),
chain_id, 2); chain_id, 2);
} }
int v3hil_stop_jtag(struct v3hil *h) int v3hil_stop_jtag(struct v3hil *h)
{ {
//printc_dbg("Stop JTAG...\n"); dbg_printc("Stop JTAG...\n");
if (hal_proto_execute(&h->hal, HAL_PROTO_FID_STOP_JTAG, NULL, 0) < 0) if (hal_proto_execute(&h->hal, map_ver(h, HAL_PROTO_FID_STOP_JTAG), NULL, 0) < 0)
return -1; return -1;
//printc_dbg("Reset communications...\n"); dbg_printc("Reset communications...\n");
h->hal.ref_id = 0; h->hal.ref_id = 0;
if (hal_proto_send(&h->hal, HAL_PROTO_TYPE_EXCEPTION, NULL, 0) < 0) { if (hal_proto_send(&h->hal, HAL_PROTO_TYPE_EXCEPTION, NULL, 0) < 0) {
h->hal.ref_id = 0; h->hal.ref_id = 0;
@ -323,7 +333,7 @@ int v3hil_stop_jtag(struct v3hil *h)
int v3hil_sync(struct v3hil *h) int v3hil_sync(struct v3hil *h)
{ {
uint8_t data[32]; uint8_t data[64], datalen = 21;
h->cal.is_cal = 0; h->cal.is_cal = 0;
@ -338,8 +348,21 @@ int v3hil_sync(struct v3hil *h)
if (h->chip) { if (h->chip) {
int i; int i;
for (i = 0; i < 16; i++) for (i = 0; i < 16; i++) {
data[i + 20 - i] = h->chip->clock_map[i].value; dbg_printc("clock map %d = %02x -> %d\n",
i, h->chip->clock_map[i].value, 20-i);
data[16 + 4 - i] = h->chip->clock_map[i].value;
}
if (h->proto_ver >= 0x0308) {
datalen = 21+16;
for (i = 16; i < 32; i++) {
dbg_printc("clock map2 %d = %02x -> %d\n",
i, h->chip->clock_map[i].value, 16+4+16*2 - i);
data[16+4+16*2 - i] = h->chip->clock_map[i].value;
}
}
} else { } else {
data[5] = 1; data[5] = 1;
data[15] = 40; data[15] = 40;
@ -348,12 +371,36 @@ int v3hil_sync(struct v3hil *h)
/* We can't use map_fid() because h->chip might be NULL -- this /* We can't use map_fid() because h->chip might be NULL -- this
* function will be called before identification is complete. * function will be called before identification is complete.
*/ */
if (hal_proto_execute(&h->hal, hal_proto_fid_t cmdid = (h->jtag_id == 0x90)
(h->jtag_id == 0x89)
? HAL_PROTO_FID_SJ_ASSERT_POR_SC ? HAL_PROTO_FID_SJ_ASSERT_POR_SC
: HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2, : HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2;
data, 21) < 0)
dbg_printc("Sync: assert POR\n");
if (h->chip) {
if (hal_proto_execute(&h->hal, map_fid(h, cmdid), data, datalen) < 0) {
return -1; return -1;
}
} else {
/* Need to do something for X/Xv2 devices, so try each in turn... */
cmdid = map_ver(h, cmdid);
if (hal_proto_execute(&h->hal, cmdid, data, datalen) < 0) {
cmdid = map_ver(h, HAL_PROTO_FID_SJ_ASSERT_POR_SC_X);
if (hal_proto_execute(&h->hal, cmdid, data, datalen) < 0) {
cmdid = map_ver(h, HAL_PROTO_FID_SJ_ASSERT_POR_SC_XV2);
if (hal_proto_execute(&h->hal, cmdid, data, datalen) < 0) {
return -1;
}
}
}
}
#ifdef DEBUG_V3HIL
printc_dbg("v3hil: POR result: (len %d) ", h->hal.length);
for (int i = 0; i < h->hal.length; ++i) {
printc_dbg("%02x%s", h->hal.payload[i],
(i == h->hal.length - 1) ? "\n" : " ");
}
#endif
if (h->hal.length < 8) { if (h->hal.length < 8) {
printc_err("v3hil: short reply: %d\n", h->hal.length); printc_err("v3hil: short reply: %d\n", h->hal.length);
@ -384,6 +431,7 @@ int v3hil_read(struct v3hil *h, address_t addr,
w32le(req + 4, (m->bits == 8) ? size : (size >> 1)); w32le(req + 4, (m->bits == 8) ? size : (size >> 1));
w32le(req + 8, h->regs[MSP430_REG_PC]); w32le(req + 8, h->regs[MSP430_REG_PC]);
dbg_printc("do read\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_READ_MEM_BYTES : map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_READ_MEM_BYTES :
HAL_PROTO_FID_READ_MEM_WORDS), HAL_PROTO_FID_READ_MEM_WORDS),
@ -442,6 +490,7 @@ static int calibrate_dco(struct v3hil *h, uint8_t max_bcs)
w16le(data, ram->offset); w16le(data, ram->offset);
w16le(data + 2, max_bcs); w16le(data + 2, max_bcs);
dbg_printc("calibrate dco: get freq\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY), map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY),
data, 6) < 0) data, 6) < 0)
@ -460,6 +509,7 @@ static int calibrate_dco(struct v3hil *h, uint8_t max_bcs)
mem_write[9] = data[2]; /* BCS1 */ mem_write[9] = data[2]; /* BCS1 */
mem_write[10] = data[4]; /* BCS2 */ mem_write[10] = data[4]; /* BCS2 */
mem_write[11] = 0; /* pad */ mem_write[11] = 0; /* pad */
dbg_printc("calibrate dco: write\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES), map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES),
mem_write, 12) < 0) { mem_write, 12) < 0) {
@ -488,6 +538,7 @@ static int calibrate_fll(struct v3hil *h)
w16le(data, ram->offset); w16le(data, ram->offset);
w16le(data + 2, 0); w16le(data + 2, 0);
dbg_printc("calibrate fll: get dco freq\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY), map_fid(h, HAL_PROTO_FID_GET_DCO_FREQUENCY),
data, 10) < 0) data, 10) < 0)
@ -509,6 +560,7 @@ static int calibrate_fll(struct v3hil *h)
mem_write[12] = data[8]; /* FLLCTL1 */ mem_write[12] = data[8]; /* FLLCTL1 */
mem_write[13] = 0; /* pad */ mem_write[13] = 0; /* pad */
dbg_printc("calibrate fll: write\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES), map_fid(h, HAL_PROTO_FID_WRITE_MEM_BYTES),
mem_write, 14) < 0) { mem_write, 14) < 0) {
@ -580,6 +632,7 @@ static int upload_funclet(struct v3hil *h,
for (i = 0; i < n; i++) for (i = 0; i < n; i++)
w16le(data + 8 + i * 2, code[i]); w16le(data + 8 + i * 2, code[i]);
dbg_printc("upload funclet: %d\n", n);
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_WRITE_MEM_WORDS), map_fid(h, HAL_PROTO_FID_WRITE_MEM_WORDS),
data, n * 2 + 8) < 0) { data, n * 2 + 8) < 0) {
@ -613,8 +666,10 @@ static int write_flash(struct v3hil *h, address_t addr,
return -1; return -1;
} }
dbg_printc("write flash: calibrate\n");
if (calibrate(h) < 0) if (calibrate(h) < 0)
return -1; return -1;
dbg_printc("write flash: upload funclet\n");
if (upload_funclet(h, ram, f) < 0) if (upload_funclet(h, ram, f) < 0)
return -1; return -1;
@ -639,6 +694,7 @@ static int write_flash(struct v3hil *h, address_t addr,
w16le(data + 20, h->cal.cal1); w16le(data + 20, h->cal.cal1);
memcpy(data + 22, mem, size); memcpy(data + 22, mem, size);
dbg_printc("exec write flash funclet\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET), map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET),
data, size + 22) < 0) { data, size + 22) < 0) {
@ -654,16 +710,24 @@ static int write_ram(struct v3hil *h, const struct chipinfo_memory *m,
address_t addr, const uint8_t *mem, address_t size) address_t addr, const uint8_t *mem, address_t size)
{ {
uint8_t data[256]; uint8_t data[256];
bool fram = false;
if (h->chip->features & CHIPINFO_FEATURE_FRAM) {
if (!strcmp(m->name, "Main") || !strcmp(m->name, "Info")) {
dbg_printc("write ram: to FRAM!\n");
fram = true;
}
}
w32le(data, addr); w32le(data, addr);
w32le(data + 4, (m->bits == 8) ? size : (size >> 1)); w32le(data + 4, (m->bits == 8 || fram) ? size : (size >> 1));
memcpy(data + 8, mem, size); memcpy(data + 8, mem, size);
if (hal_proto_execute(&h->hal, dbg_printc("write ram\n");
map_fid(h, (m->bits == 8) ? HAL_PROTO_FID_WRITE_MEM_BYTES hal_proto_fid_t fid = (m->bits == 8) ? HAL_PROTO_FID_WRITE_MEM_BYTES
: HAL_PROTO_FID_WRITE_MEM_WORDS), : HAL_PROTO_FID_WRITE_MEM_WORDS;
data, size + 8) < 0) { if (fram) fid = HAL_PROTO_FID_WRITE_FRAM_QUICK_XV2;
if (hal_proto_execute(&h->hal, map_fid(h, fid), data, size + 8) < 0) {
printc_err("v3hil: failed writing %d bytes to 0x%05x\n", printc_err("v3hil: failed writing %d bytes to 0x%05x\n",
size, addr); size, addr);
return -1; return -1;
@ -686,9 +750,12 @@ int v3hil_write(struct v3hil *h, address_t addr,
if (size > 128) if (size > 128)
size = 128; size = 128;
if (m->type == CHIPINFO_MEMTYPE_FLASH) if (m->type == CHIPINFO_MEMTYPE_FLASH) {
dbg_printc("call write flash\n");
return write_flash(h, addr, mem, size); return write_flash(h, addr, mem, size);
}
dbg_printc("call write ram\n");
return write_ram(h, m, addr, mem, size); return write_ram(h, m, addr, mem, size);
} }
@ -713,6 +780,7 @@ static int call_erase(struct v3hil *h,
w16le(data + 20, h->cal.cal1); w16le(data + 20, h->cal.cal1);
w32le(data + 22, 0xdeadbeef); w32le(data + 22, 0xdeadbeef);
dbg_printc("call erase funclet\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET), map_fid(h, HAL_PROTO_FID_EXECUTE_FUNCLET),
data, 26) < 0) { data, 26) < 0) {
@ -746,8 +814,10 @@ int v3hil_erase(struct v3hil *h, address_t segment)
if (!flash) if (!flash)
printc_err("v3hil: can't find appropriate flash region\n"); printc_err("v3hil: can't find appropriate flash region\n");
dbg_printc("calibrate\n");
if (calibrate(h) < 0) if (calibrate(h) < 0)
return -1; return -1;
dbg_printc("upload erase funclet\n");
if (upload_funclet(h, ram, f) < 0) if (upload_funclet(h, ram, f) < 0)
return -1; return -1;
@ -759,6 +829,7 @@ int v3hil_erase(struct v3hil *h, address_t segment)
bank_size /= flash->banks; bank_size /= flash->banks;
for (i = flash->banks; i >= 0; i--) for (i = flash->banks; i >= 0; i--)
dbg_printc("Erase bank %d\n", i);
if (call_erase(h, ram, f, if (call_erase(h, ram, f,
flash->offset + i * bank_size - 2, 0xa502) < 0) flash->offset + i * bank_size - 2, 0xa502) < 0)
return -1; return -1;
@ -777,10 +848,13 @@ int v3hil_update_regs(struct v3hil *h)
{ {
const hal_proto_fid_t fid = const hal_proto_fid_t fid =
map_fid(h, HAL_PROTO_FID_READ_ALL_CPU_REGS); map_fid(h, HAL_PROTO_FID_READ_ALL_CPU_REGS);
const int reg_size = (fid == HAL_PROTO_FID_READ_ALL_CPU_REGS) ? 2 : 3; const int reg_size = (fid == HAL_PROTO_FID_READ_ALL_CPU_REGS
|| fid == HAL_PROTO_FID_READ_ALL_CPU_REGS - 1)
? 2 : 3;
int i; int i;
int sptr = 0; int sptr = 0;
dbg_printc("Read regs\n");
if (hal_proto_execute(&h->hal, fid, NULL, 0) < 0) { if (hal_proto_execute(&h->hal, fid, NULL, 0) < 0) {
printc_err("v3hil: can't read CPU registers\n"); printc_err("v3hil: can't read CPU registers\n");
return -1; return -1;
@ -814,7 +888,9 @@ int v3hil_flush_regs(struct v3hil *h)
{ {
const hal_proto_fid_t fid = const hal_proto_fid_t fid =
map_fid(h, HAL_PROTO_FID_WRITE_ALL_CPU_REGS); map_fid(h, HAL_PROTO_FID_WRITE_ALL_CPU_REGS);
const int reg_size = (fid == HAL_PROTO_FID_WRITE_ALL_CPU_REGS) ? 2 : 3; const int reg_size = (fid == HAL_PROTO_FID_READ_ALL_CPU_REGS
|| fid == HAL_PROTO_FID_READ_ALL_CPU_REGS - 1)
? 2 : 3;
int i; int i;
int dptr = 0; int dptr = 0;
uint8_t data[64]; uint8_t data[64];
@ -834,6 +910,7 @@ int v3hil_flush_regs(struct v3hil *h)
} }
} }
dbg_printc("Write regs\n");
if (hal_proto_execute(&h->hal, fid, data, reg_size * 13) < 0) { if (hal_proto_execute(&h->hal, fid, data, reg_size * 13) < 0) {
printc_err("v3hil: can't write CPU registers\n"); printc_err("v3hil: can't write CPU registers\n");
return -1; return -1;
@ -857,6 +934,7 @@ int v3hil_context_restore(struct v3hil *h, int free)
data[10] = free ? 7 : 6; data[10] = free ? 7 : 6;
data[14] = free ? 1 : 0; data[14] = free ? 1 : 0;
dbg_printc("Context restore\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_RC_RELEASE_JTAG), map_fid(h, HAL_PROTO_FID_RC_RELEASE_JTAG),
data, 18) < 0) { data, 18) < 0) {
@ -879,6 +957,7 @@ int v3hil_context_save(struct v3hil *h)
data[2] = h->wdtctl | 0x80; data[2] = h->wdtctl | 0x80;
data[3] = 0x5a; /* WDTPW */ data[3] = 0x5a; /* WDTPW */
dbg_printc("Context save\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_SJ_CONDITIONAL_SC), map_fid(h, HAL_PROTO_FID_SJ_CONDITIONAL_SC),
data, 8) < 0) data, 8) < 0)
@ -910,6 +989,7 @@ int v3hil_single_step(struct v3hil *h)
data[9] = h->regs[MSP430_REG_SR] >> 8; data[9] = h->regs[MSP430_REG_SR] >> 8;
data[10] = 7; data[10] = 7;
dbg_printc("Single-stepping...\n");
if (hal_proto_execute(&h->hal, if (hal_proto_execute(&h->hal,
map_fid(h, HAL_PROTO_FID_SINGLE_STEP), map_fid(h, HAL_PROTO_FID_SINGLE_STEP),
data, 18) < 0) { data, 18) < 0) {
@ -944,7 +1024,8 @@ static int set_param(struct v3hil *fet, hal_proto_config_t cfg,
} }
data[0] = cfg; data[0] = cfg;
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_CONFIGURE, dbg_printc("Set param 0x%02x to 0x%08x\n", cfg, value);
if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_CONFIGURE),
data, 8) < 0) { data, 8) < 0) {
printc_err("v3hil: can't set param 0x%02x to 0x%08x\n", printc_err("v3hil: can't set param 0x%02x to 0x%08x\n",
cfg, value); cfg, value);
@ -964,7 +1045,7 @@ static int idproc_89(struct v3hil *fet, uint32_t id_data_addr,
memset(data, 0, 8); memset(data, 0, 8);
w32le(data, id_data_addr); w32le(data, id_data_addr);
data[4] = 8; data[4] = 8;
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_WORDS, if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_READ_MEM_WORDS),
data, 8) < 0) data, 8) < 0)
return -1; return -1;
if (fet->hal.length < 16) { if (fet->hal.length < 16) {
@ -980,7 +1061,7 @@ static int idproc_89(struct v3hil *fet, uint32_t id_data_addr,
id->config = fet->hal.payload[13] & 0x7f; id->config = fet->hal.payload[13] & 0x7f;
printc_dbg("Read fuses...\n"); printc_dbg("Read fuses...\n");
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_GET_FUSES, NULL, 0) < 0) if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_GET_FUSES), NULL, 0) < 0)
return -1; return -1;
if (!fet->hal.length) { if (!fet->hal.length) {
printc_err("v3hil: short reply: %d\n", fet->hal.length); printc_err("v3hil: short reply: %d\n", fet->hal.length);
@ -1004,7 +1085,7 @@ static int idproc_9x(struct v3hil *fet, uint32_t dev_id_ptr,
memset(data, 0, 8); memset(data, 0, 8);
w32le(data, dev_id_ptr); w32le(data, dev_id_ptr);
data[4] = 4; data[4] = 4;
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_QUICK_XV2, if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_READ_MEM_QUICK_XV2),
data, 8) < 0) data, 8) < 0)
return -1; return -1;
if (fet->hal.length < 8) { if (fet->hal.length < 8) {
@ -1028,7 +1109,7 @@ static int idproc_9x(struct v3hil *fet, uint32_t dev_id_ptr,
w32le(data, dev_id_ptr); w32le(data, dev_id_ptr);
w32le(data + 4, tlv_size >> 1); w32le(data + 4, tlv_size >> 1);
w32le(data + 8, fet->regs[MSP430_REG_PC]); w32le(data + 8, fet->regs[MSP430_REG_PC]);
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_READ_MEM_QUICK_XV2, if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_READ_MEM_QUICK_XV2),
data, 8) < 0) data, 8) < 0)
return -1; return -1;
if (fet->hal.length < tlv_size) { if (fet->hal.length < tlv_size) {
@ -1062,28 +1143,32 @@ int v3hil_identify(struct v3hil *fet)
int i; int i;
printc_dbg("Fetching JTAG ID...\n"); printc_dbg("Fetching JTAG ID...\n");
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_GET_JTAG_ID, if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_GET_JTAG_ID),
NULL, 0) < 0) NULL, 0) < 0)
return -1; return -1;
printc_dbg("ID:"); #ifdef DEBUG_V3HIL
printc_dbg("v3hil: ID:");
for (i = 0; i < fet->hal.length; i++) for (i = 0; i < fet->hal.length; i++)
printc_dbg(" %02x", fet->hal.payload[i]); printc_dbg(" %02x", fet->hal.payload[i]);
printc_dbg("\n"); printc_dbg("\n");
#endif
if (fet->hal.length < 12) { if (fet->hal.length < 12) {
if (fet->hal.length == 2) { if (fet->hal.length == 2) {
fet->jtag_id = fet->hal.payload[0]; fet->jtag_id = fet->hal.payload[0];
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_GET_DEVICE_ID_PTR, if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_GET_DEVICE_ID_PTR),
NULL, 0) < 0) NULL, 0) < 0)
return -1; return -1;
//printc_dbg("len: %d\n", fet->hal.length); #ifdef DEBUG_V3HIL
printc_dbg("IDPtr:"); dbg_printc("len: %d\n", fet->hal.length);
printc_dbg("v3hil: IDPtr:");
for (i = 0; i < fet->hal.length; i++) for (i = 0; i < fet->hal.length; i++)
printc_dbg(" %02x", fet->hal.payload[i]); printc_dbg(" %02x", fet->hal.payload[i]);
printc_dbg("\n"); printc_dbg("\n");
#endif
if (fet->hal.length < 10) { if (fet->hal.length < 10) {
printc_err("v3hil: short reply: %d\n", fet->hal.length); printc_err("v3hil: short reply: %d\n", fet->hal.length);
@ -1119,7 +1204,7 @@ int v3hil_identify(struct v3hil *fet)
set_param(fet, HAL_PROTO_CONFIG_NO_BSL, 0); // is allowed to fail set_param(fet, HAL_PROTO_CONFIG_NO_BSL, 0); // is allowed to fail
printc_dbg("Check JTAG fuse...\n"); printc_dbg("Check JTAG fuse...\n");
if (hal_proto_execute(&fet->hal, HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN, if (hal_proto_execute(&fet->hal, map_ver(fet, HAL_PROTO_FID_IS_JTAG_FUSE_BLOWN),
NULL, 0) < 0) { NULL, 0) < 0) {
return -1; return -1;
} }

2
drivers/v3hil.h
View File

@ -45,7 +45,7 @@ struct v3hil {
uint8_t wdtctl; uint8_t wdtctl;
/* Is this a v2 or v3 firmware running on the eZ-FET? */ /* Is this a v2 or v3 firmware running on the eZ-FET? */
uint8_t proto_ver; uint16_t proto_ver;
/* Register cache: this must be flushed before restoring context /* Register cache: this must be flushed before restoring context
* and updated after saving context. * and updated after saving context.