[simio] support Timer_B compare latch double-buffering
This commit is contained in:
Tadashi G. Takaoka
parent
f9f897e95e
commit
c53f697b76
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@ -90,6 +90,8 @@ struct timer {
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uint16_t tar;
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uint16_t ctls[MAX_CCRS];
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uint16_t ccrs[MAX_CCRS];
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/* Compare latch for Timer_B */
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uint16_t bcls[MAX_CCRS];
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};
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static struct simio_device *timer_create(char **arg_text)
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@ -148,6 +150,7 @@ static void timer_reset(struct simio_device *dev)
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tr->go_down = false;
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memset(tr->ccrs, 0, sizeof(tr->ccrs));
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memset(tr->ctls, 0, sizeof(tr->ctls));
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memset(tr->bcls, 0, sizeof(tr->bcls));
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}
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static int config_addr(address_t *addr, char **arg_text)
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@ -334,6 +337,8 @@ static int timer_info(struct simio_device *dev)
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for (i = 0; i < tr->size; i++) {
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printc("T%cCCTL%d = 0x%04x, T%cCCR%d = 0x%04x",
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timer_type, i, tr->ctls[i], timer_type, i, tr->ccrs[i]);
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if (tr->timer_type == TIMER_TYPE_B)
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printc(", TBCL%d = 0x%04x", i, tr->bcls[i]);
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printc("\n");
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}
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@ -397,12 +402,19 @@ static int timer_write(struct simio_device *dev,
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int index = ((addr & 0xf) - 2) >> 1;
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tr->ccrs[index] = data;
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if (index == 0 && tr->ccrs[index] < tr->tar &&
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if (tr->timer_type == TIMER_TYPE_A &&
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index == 0 && data < tr->tar &&
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(tr->tactl & (MC1 | MC0)) == MC0) {
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/* When CCR[0] is set less than current TAR in up
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* mode, TAR rolls to 0. */
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tr->go_down = true;
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}
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if (tr->timer_type == TIMER_TYPE_B &&
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(tr->ctls[index] & (CLLD1 | CLLD0)) == 0) {
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/* Writing TBCCRx triggers update TBCLx immediately.
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* No grouping. */
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tr->bcls[index] = tr->ccrs[index];
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}
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return 0;
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}
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@ -477,6 +489,12 @@ static void timer_ack_interrupt(struct simio_device *dev, int irq)
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/* By design irq1 does not clear CCIFG or TAIFG automatically */
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}
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static uint16_t get_ccr(struct timer *tr, int index) {
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if (tr->timer_type == TIMER_TYPE_B)
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return tr->bcls[index];
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return tr->ccrs[index];
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}
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static uint16_t tar_increment(struct timer *tr)
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{
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tr->tar++;
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@ -497,7 +515,7 @@ static void tar_step(struct timer *tr)
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case 0:
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break;
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case 1:
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if (tr->tar == tr->ccrs[0] || tr->go_down) {
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if (tr->tar == get_ccr(tr, 0) || tr->go_down) {
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tr->tar = 0;
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tr->tactl |= TAIFG;
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tr->go_down = false;
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@ -512,9 +530,9 @@ static void tar_step(struct timer *tr)
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break;
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case 3:
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if (tr->tar >= tr->ccrs[0])
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if (tr->tar >= get_ccr(tr, 0))
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tr->go_down = true;
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if (!tr->tar)
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if (tr->tar == 0)
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tr->go_down = false;
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if (tr->go_down) {
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@ -530,7 +548,7 @@ static void tar_step(struct timer *tr)
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static void comparator_step(struct timer *tr, int index)
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{
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if (tr->timer_type == TIMER_TYPE_A) {
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if (tr->tar == tr->ccrs[index]) {
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if (tr->tar == get_ccr(tr, index)) {
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tr->ctls[index] |= CCIFG;
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if (tr->ctls[index] & CCI)
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tr->ctls[index] |= SCCI;
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@ -540,8 +558,19 @@ static void comparator_step(struct timer *tr, int index)
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}
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if (tr->timer_type == TIMER_TYPE_B) {
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if (tr->tar == tr->ccrs[index]) {
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const uint16_t mc = tr->tactl & (MC1 | MC0);
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const uint16_t clld = tr->ctls[index] & (CLLD1 | CLLD0);
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if (tr->tar == 0) {
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if (clld == CLLD0 || (clld == CLLD1 && mc != 0)) {
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tr->bcls[index] = tr->ccrs[index];
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}
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}
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if (tr->tar == get_ccr(tr, index)) {
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tr->ctls[index] |= CCIFG;
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if ((clld == CLLD1 && mc == (MC1 | MC0)) ||
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clld == (CLLD1 | CLLD0)) {
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tr->bcls[index] = tr->ccrs[index];
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}
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}
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}
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}
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@ -905,6 +905,324 @@ static void test_timer_b_length_16()
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assert(read_timer(dev, TxR) == 4);
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}
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static void test_timer_b_compare_latch_0_up()
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{
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dev = create_timer("");
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config_timer(dev, "type", "B");
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/* Up 16 bit, SMCLK, clear */
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write_timer(dev, TxCTL, MC0 | TACLR | TASSEL1);
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write_timer(dev, TxCCR(0), 2);
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write_timer(dev, TxCCR(2), 5);
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// When CLLD=0, new data is transferred from TBCCRx to TBCLx immediately
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// when TBCCRx is written to.
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write_timer(dev, TxCCTL(0), CCIE);
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write_timer(dev, TxCCTL(2), CCIE);
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step_smclk(dev, 2);
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assert(check_noirq(dev));
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// TBCCR[0] is immediately transferred to TBCL[0].
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write_timer(dev, TxCCR(0), 10);
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// Because now TBCL[0] is 10, no overflow interrupt should happen at TBR=2
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step_smclk(dev, 1);
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assert(read_timer(dev, TxR) == 3);
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assert(check_noirq(dev));
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// Because TBCL[2] is 5, comparator interrupt should happen at TBR=5.
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step_smclk(dev, 3);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(2));
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assert(check_noirq(dev));
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// Because TBCL[2] is 8, comparator interrupt should happen again at TBR=8.
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write_timer(dev, TxCCR(2), 8);
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step_smclk(dev, 3);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(2));
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assert(check_noirq(dev));
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// Because TBCL[0] is 10, overflow interrupt should happen again at TBR=10.
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step_smclk(dev, 2);
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assert(check_irq0(dev));
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ack_irq0(dev);
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assert(check_noirq(dev));
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assert(read_timer(dev, TxR) == 0);
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}
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static void test_timer_b_compare_latch_1_up()
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{
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dev = create_timer("3");
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config_timer(dev, "type", "B");
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/* Up 16 bit, SMCLK, clear */
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write_timer(dev, TxCTL, MC0 | TACLR | TASSEL1);
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write_timer(dev, TxCCR(0), 5);
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write_timer(dev, TxCCR(1), 2);
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// When CLLD=1, new data is transferred from TBCCRx to TBCLx when TBR
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// counts to 0.
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write_timer(dev, TxCCTL(0), CLLD0 | CCIE);
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write_timer(dev, TxCCTL(1), CLLD0 | CCIE);
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step_smclk(dev, 2);
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assert(check_noirq(dev));
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// TBCCR[0] will be transferred to TBCL[0] when next TBR=0.
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write_timer(dev, TxCCR(0), 10);
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// TBCCR[1] will be transferred to TBCL[1] when next TBR=0.
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write_timer(dev, TxCCR(1), 2);
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// Because TBCL[1] keeps 2, compare interrupt should happen at TBR=2.
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(1));
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assert(check_noirq(dev));
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// Because TBCL[0] keeps 5, compare interrupt should happen at TBR=5, then TBR=0.
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step_smclk(dev, 3);
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assert(check_irq0(dev));
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ack_irq0(dev);
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assert(check_noirq(dev));
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assert(read_iv(dev) == TxIV_TxIFG(0));
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// Now TBCL[1] becomes 2, compare interrupt should happen again at TBR=2.
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step_smclk(dev, 3);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(1));
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assert(check_noirq(dev));
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// Now TBCL[0] becomes 10, no compare interrupt should happen at TBR=5.
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step_smclk(dev, 7);
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assert(check_noirq(dev));
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// Then compare interrupt should happen at TBR=10, then TBR=0.
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step_smclk(dev, 1);
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assert(check_irq0(dev));
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ack_irq0(dev);
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assert(check_noirq(dev));
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assert(read_iv(dev) == TxIV_TxIFG(0));
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assert(read_timer(dev, TxR) == 0);
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}
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static void test_timer_b_compare_latch_2_continuous()
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{
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dev = create_timer("7");
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config_timer(dev, "type", "B");
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/* Continuous 8 bit, SMCLK, clear */
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write_timer(dev, TxCTL, MC1 | CNTL1 | CNTL0 | TACLR | TASSEL1);
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write_timer(dev, TxR, 0x00fe);
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write_timer(dev, TxCCR(6), 2);
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// When CLLD=2, new data is transferred from TBCCRx to TBCLx when TBR
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// counts to 0 for continuous mode.
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write_timer(dev, TxCCTL(6), CLLD1 | CCIE);
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// TBCCR[6] will be transferred to TBCL[6] when next TBR=0.
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write_timer(dev, TxCCR(6), 5);
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step_smclk(dev, 2);
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assert(read_timer(dev, TxR) == 0);
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// Now TBCL[6] becomes 5, compare interrupt should not happen at TBR=2.
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step_smclk(dev, 3);
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assert(check_noirq(dev));
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// Because TBCL[6] is 5, compare interrupt should happen at TBR=5.
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step_smclk(dev, 3);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(6));
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assert(check_noirq(dev));
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// Because TBCCR[6] will be transferred to TBCL[6] when next TBR=0,
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// no compare interrupt should happen at TBR=5.
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write_timer(dev, TxCCR(6), 10);
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step_smclk(dev, 0x100);
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assert(check_noirq(dev));
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assert(read_timer(dev, TxR) > 5);
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// Now TBCL[6] becomes 10, compare interrupt should happen.
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step_smclk(dev, 5);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(6));
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assert(check_noirq(dev));
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}
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static void test_timer_b_compare_latch_2_up()
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{
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dev = create_timer("5");
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config_timer(dev, "type", "B");
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/* Up 16 bit, SMCLK, clear */
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write_timer(dev, TxCTL, MC0 | TACLR | TASSEL1);
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write_timer(dev, TxCCR(0), 5);
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write_timer(dev, TxCCR(4), 2);
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// When CLLD=2, new data is transferred from TBCCRx to TBCLx when TBR
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// counts to 0.
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write_timer(dev, TxCCTL(0), CLLD0 | CCIE);
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write_timer(dev, TxCCTL(4), CLLD0 | CCIE);
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step_smclk(dev, 2);
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assert(check_noirq(dev));
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// TBCCR[0] will be transferred to TBCL[0] when next TBR=0.
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write_timer(dev, TxCCR(0), 10);
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// TBCCR[4] will be transferred to TBCL[4] when next TBR=0.
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write_timer(dev, TxCCR(4), 2);
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// Because TBCL[4] keeps 2, compare interrupt should happen at TBR=2.
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(4));
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assert(check_noirq(dev));
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// Because TBCL[0] keeps 5, compare interrupt should happen at TBR=5, then TBR=0.
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step_smclk(dev, 3);
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assert(check_irq0(dev));
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ack_irq0(dev);
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assert(check_noirq(dev));
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assert(read_iv(dev) == TxIV_TxIFG(0));
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// Now TBCL[4] becomes 2, compare interrupt should happen again at TBR=2.
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step_smclk(dev, 3);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(4));
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assert(check_noirq(dev));
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// Now TBCL[0] becomes 10, no compare interrupt should happen at TBR=5.
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step_smclk(dev, 7);
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assert(check_noirq(dev));
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// Then compare interrupt should happen at TBR=10, then TBR=0.
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step_smclk(dev, 1);
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assert(check_irq0(dev));
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ack_irq0(dev);
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assert(check_noirq(dev));
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assert(read_iv(dev) == TxIV_TxIFG(0));
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assert(read_timer(dev, TxR) == 0);
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}
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static void test_timer_b_compare_latch_2_updown()
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{
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dev = create_timer("7");
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config_timer(dev, "type", "B");
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/* Up/Down 16 bit, SMCLK, interrupt enable, clear */
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write_timer(dev, TxCTL, MC1 | MC0 | TACLR | TAIE | TASSEL1);
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write_timer(dev, TxCCR(0), 10);
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write_timer(dev, TxCCTL(0), CCIE);
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write_timer(dev, TxCCR(5), 5);
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// When CLLD=2, new data is transferred from TBCCRx to TBCLx when TBR
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// counts to the old TBCL0 value or to 0 for up/down mode.
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write_timer(dev, TxCCTL(5), CLLD1 | CCIE);
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step_smclk(dev, 4);
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assert(check_noirq(dev));
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assert(read_timer(dev, TxR) == 4);
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// TBCCR[5] will be transferred to TBCL[5] when next TBR=5.
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write_timer(dev, TxCCR(5), 8);
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// Because TBCL[0] is 5, compare interrupt should happen at TBR=TBCL[5]=5.
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step_smclk(dev, 2);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(5));
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assert(check_noirq(dev));
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// Now TBCL[5] becomes 8, compare interrupt should happen at TBR=8.
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step_smclk(dev, 3);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(5));
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assert(check_noirq(dev));
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// Because TBCL[0]=10, compare interrupt should happen at TBR=10.
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step_smclk(dev, 2);
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assert(check_irq0(dev));
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ack_irq0(dev);
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assert(check_noirq(dev));
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assert(read_iv(dev) == TxIV_TxIFG(0));
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assert(read_timer(dev, TxR) == 9);
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// Because TBCL[5] is still 8, compare interrupt should happen again at TBR=8.
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step_smclk(dev, 2);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(5));
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assert(check_noirq(dev));
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// Because TBCL[5] is still 8, no compare interrupt should happen.
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step_smclk(dev, 6);
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assert(read_timer(dev, TxR) == 1);
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// TBCCR[5] will be transferred to TBCL[5] when next TBR=0.
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write_timer(dev, TxCCR(5), 2);
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// Compare interrupt should happen at TBR=0.
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step_smclk(dev, 1);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TBIV_TBIFG);
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assert(check_noirq(dev));
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assert(read_iv(dev) == TxIV_TxIFG(0));
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assert(read_timer(dev, TxR) == 0);
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// Now TBCL[5] becomes 2, compare interrupt should happen at TBR=2.
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step_smclk(dev, 3);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(5));
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assert(check_noirq(dev));
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assert(read_timer(dev, TxR) == 3);
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}
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static void test_timer_b_compare_latch_3_up()
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{
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dev = create_timer("5");
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config_timer(dev, "type", "B");
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/* Up 16 bit, SMCLK, clear */
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write_timer(dev, TxCTL, MC0 | TACLR | TASSEL1);
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write_timer(dev, TxCCR(0), 10);
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write_timer(dev, TxCCTL(0), CCIE);
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write_timer(dev, TxCCR(2), 5);
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// When CLLD=3, new data is transferred from TBCCRx to TBCLx when TBR
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// counts to the old TBCL0 value.
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write_timer(dev, TxCCTL(2), CLLD1 | CLLD0 | CCIE);
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step_smclk(dev, 4);
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assert(check_noirq(dev));
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assert(read_timer(dev, TxR) == 4);
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// TBCCR[2] will be transferred to TBCL[2] when next TBR=5.
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write_timer(dev, TxCCR(2), 8);
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// Because TBCL[0] is 5, compare interrupt should happen at TBR=TBCL[2]=5.
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step_smclk(dev, 2);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TxIV_TxIFG(2));
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assert(check_noirq(dev));
|
||||
|
||||
// TBCCR[2] will be transferred to TBCL[2] when next TBR=8.
|
||||
write_timer(dev, TxCCR(2), 2);
|
||||
|
||||
// Now TBCL[2] becomes 8, compare interrupt should happen at TBR=8.
|
||||
step_smclk(dev, 3);
|
||||
assert(check_irq1(dev));
|
||||
assert(read_iv(dev) == TxIV_TxIFG(2));
|
||||
assert(check_noirq(dev));
|
||||
|
||||
// Because TBCL[0] is 10, compare interrupt should happen at TBR=10.
|
||||
step_smclk(dev, 2);
|
||||
assert(check_irq0(dev));
|
||||
ack_irq0(dev);
|
||||
assert(check_noirq(dev));
|
||||
assert(read_iv(dev) == TxIV_TxIFG(0));
|
||||
assert(read_timer(dev, TxR) == 0);
|
||||
|
||||
// Because TBCL[2] is 2, compare interrupt should happen again at TBR=2.
|
||||
step_smclk(dev, 3);
|
||||
assert(check_irq1(dev));
|
||||
assert(read_iv(dev) == TxIV_TxIFG(2));
|
||||
assert(check_noirq(dev));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Test runner.
|
||||
|
|
@ -953,4 +1271,10 @@ int main(int argc, char **argv)
|
|||
RUN_TEST(test_timer_b_length_10);
|
||||
RUN_TEST(test_timer_b_length_12);
|
||||
RUN_TEST(test_timer_b_length_16);
|
||||
RUN_TEST(test_timer_b_compare_latch_0_up);
|
||||
RUN_TEST(test_timer_b_compare_latch_1_up);
|
||||
RUN_TEST(test_timer_b_compare_latch_2_continuous);
|
||||
RUN_TEST(test_timer_b_compare_latch_2_up);
|
||||
RUN_TEST(test_timer_b_compare_latch_2_updown);
|
||||
RUN_TEST(test_timer_b_compare_latch_3_up);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue