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jtaglib: test previous commit on 0x89 device, properly write the wdt password

This commit is contained in:
Triss 2022-07-31 20:09:13 +02:00
parent 2373d33bbb
commit c801faeb80
3 changed files with 56 additions and 8 deletions
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9
drivers/jtaglib.c
View File

@ -581,8 +581,8 @@ void jtag_dev_default_context_save(struct jtdev *p, bool after_puc) {
p->regs[0] = jtag_read_reg(p, 0);
/* back up and disable watchdog */
p->wdtctl = jtag_read_mem(p, 16, wdtctl_a);
jtag_write_mem(p, 16, wdtctl_a, p->wdtctl | 0x0080);
p->wdtctl = jtag_read_mem(p, 16, wdtctl_a) & 0xff;
jtag_write_mem(p, 16, wdtctl_a, p->wdtctl | 0x5a80);
/* also back up stack pointer & status register */
p->regs[1] = jtag_read_reg(p, 1);
@ -595,7 +595,7 @@ void jtag_dev_default_context_restore(struct jtdev *p) {
jtag_write_reg(p, 1, p->regs[1]);
jtag_write_reg(p, 2, p->regs[2]);
jtag_write_mem(p, 16, wdtctl_a, p->wdtctl);
jtag_write_mem(p, 16, wdtctl_a, p->wdtctl | 0x5a00);
jtag_write_reg(p, 0, p->regs[0]);
}
@ -871,6 +871,9 @@ static int idproc_89(struct jtdev *p, uint32_t id_data_addr, struct chipinfo_id
iddata[i] = jtag_read_mem(p, 16, id_data_addr + i*2);
}*/
jtag_read_mem_quick(p, id_data_addr, 8, iddata);
for (int i = 0; i < 8; ++i) {
dbg_printc("IDbytes[%d] = %04x\n", i, iddata[i]);
}
id->ver_id = iddata[0];
id->ver_sub_id = 0;

47
drivers/jtaglib_cpu16.c
View File

@ -3,6 +3,12 @@
#include "jtaglib_defs.h"
#include "output.h"
#ifdef DEBUG_JTAGLIB
#define dbg_printc(fmt, ...) printc_dbg("jlf16: %s:%d " fmt, __func__, __LINE__, ##__VA_ARGS__)
#else
#define dbg_printc(fmt, ...) do{}while(0)
#endif
/* Set target CPU JTAG state machine into the instruction fetch state
* return: 1 - instruction fetch was set
* 0 - otherwise
@ -35,6 +41,8 @@ static int jlf16_set_instruction_fetch(struct jtdev *p)
static void jlf16_halt_cpu(struct jtdev *p)
{ // SLAU320AJ name: HaltCPU
/* Set CPU into instruction fetch mode */
dbg_printc("halt cpu\n");
jlf16_set_instruction_fetch(p);
/* Set device into JTAG mode + read */
@ -56,6 +64,8 @@ static void jlf16_halt_cpu(struct jtdev *p)
/* Release the target CPU from the controlled stop state */
static void jlf16_release_cpu(struct jtdev *p)
{ // SLAU320AJ name: ReleaseCPU
dbg_printc("release cpu\n");
jtag_tclk_clr(p);
/* clear the HALT_JTAG bit */
@ -87,6 +97,8 @@ static int jlf16_verify_mem(struct jtdev *p,
/* Start value for PSA calculation */
unsigned int psa_crc = start_address-2;
dbg_printc("verify: %04x..%04x\n", start_address, start_address+length*2);
jtag_execute_puc(p);
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
jtag_dr_shift_16(p, 0x2401);
@ -166,6 +178,8 @@ static unsigned int jlf16_get_device(struct jtdev *p)
}
}
dbg_printc("get device: jtag id=%02x\n", jtag_id);
if (loop_counter == 0) {
printc_err("jlf16_get_device: timed out\n");
p->failed = 1;
@ -185,6 +199,8 @@ static uint16_t jlf16_read_mem(struct jtdev *p, unsigned int format, address_t a
{ // SLAU320AJ name: ReadMem
uint16_t content;
dbg_printc("%dbit %04x\n", format, address);
jlf16_halt_cpu(p);
jtag_tclk_clr(p);
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
@ -209,6 +225,8 @@ static uint16_t jlf16_read_mem(struct jtdev *p, unsigned int format, address_t a
if (format == 8)
content &= 0x00ff;
dbg_printc("%dbit %04x -> %04x\n", format, address, content);
return content;
}
@ -223,6 +241,8 @@ static void jlf16_read_mem_quick(struct jtdev *p, address_t address,
unsigned int index;
address_t pc_bak;
dbg_printc("%04x..%04x\n", address, address+length*2);
pc_bak = jtag_read_reg(p, 0);
/* Initialize reading: */
@ -256,6 +276,8 @@ static void jlf16_read_mem_quick(struct jtdev *p, address_t address,
static void jlf16_write_mem(struct jtdev *p, unsigned int format,
address_t address, uint16_t data)
{ // SLAU320AJ name: WriteMem
dbg_printc("%dbit %04x <- %04x\n", format, address, data);
jlf16_halt_cpu(p);
jtag_tclk_clr(p);
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
@ -289,6 +311,8 @@ static void jlf16_write_mem_quick(struct jtdev *p, address_t address,
{ // SLAU320AJ name: WriteMemQuick
unsigned int index;
dbg_printc("%04x..%04x\n", address, address+length*2);
/* Initialize writing */
jtag_write_reg(p, 0, address-4);
jlf16_halt_cpu(p);
@ -320,6 +344,8 @@ static unsigned int jlf16_execute_puc(struct jtdev *p)
{ // SLAU320AJ name: ExecutePOR
unsigned int jtag_id;
dbg_printc("\n");
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
/* Apply and remove reset */
@ -338,7 +364,7 @@ static unsigned int jlf16_execute_puc(struct jtdev *p)
//jtag_tclk_set(p); // TODO: ???
/* Disable watchdog on target device */
jtag_write_mem(p, 16, 0x0120, 0x5A80); // FIXME
//jtag_write_mem(p, 16, 0x0120, 0x5A80); // FIXME
return jtag_id;
}
@ -354,8 +380,10 @@ static void jlf16_release_device(struct jtdev *p, address_t address)
{ // SLAU320AJ name: ReleaseDevice
switch (address) {
case 0xffff: /* Nothing to do */
dbg_printc("BOR\n");
break;
case 0xfffe: /* Perform reset */
dbg_printc("SRST\n");
/* delete all breakpoints */
jtag_set_breakpoint(p,-1,0);
/* issue reset */
@ -364,6 +392,7 @@ static void jlf16_release_device(struct jtdev *p, address_t address)
jtag_dr_shift_16(p, 0x2401);
break;
default: /* Set target CPU's PC */
dbg_printc("PC: %04x\n", address);
jtag_write_reg(p, 0, address);
break;
}
@ -392,6 +421,8 @@ static void jlf16_write_flash(struct jtdev *p, address_t start_address,
unsigned int index;
unsigned int address;
dbg_printc("%04x..%04x\n", address, address+length*2);
address = start_address;
jlf16_halt_cpu(p);
jtag_tclk_clr(p);
@ -494,6 +525,8 @@ static void jlf16_erase_flash(struct jtdev *p, unsigned int erase_mode,
unsigned int loop_counter;
unsigned int max_loop_count = 1; /* erase cycle repeating for mass erase */
dbg_printc("%04x: %04x\n", erase_mode, erase_address);
if ((erase_mode == JTAG_ERASE_MASS) || (erase_mode == JTAG_ERASE_MAIN)) {
number_of_strobes = 5300; /* Larger Flash memories require */
max_loop_count = 19; /* additional cycles for erase. */
@ -585,6 +618,8 @@ static address_t jlf16_read_reg(struct jtdev *p, int reg)
{ // libmsp430 BIOS name: ReadCpuReg
unsigned int value;
dbg_printc("%d\n", reg);
/* Set CPU into instruction fetch mode */
jlf16_set_instruction_fetch(p);
@ -639,6 +674,8 @@ static address_t jlf16_read_reg(struct jtdev *p, int reg)
jtag_tclk_set(p);
dbg_printc("%d -> %04x\n", reg, value);
/* Return value read from register */
return value;
}
@ -647,6 +684,8 @@ static address_t jlf16_read_reg(struct jtdev *p, int reg)
static void jlf16_write_reg(struct jtdev *p, int reg, address_t value)
{ // SLAU320AJ name: SetPC
/* Set CPU into instruction fetch mode */
dbg_printc("%d <- %04x\n", reg, value);
jlf16_set_instruction_fetch(p);
/* CPU controls RW & BYTE */
@ -690,6 +729,8 @@ static void jlf16_single_step( struct jtdev *p )
{ // libmsp430 BIOS name: SingleStep
unsigned int loop_counter;
dbg_printc("\n");
jlf16_set_instruction_fetch(p);
/* CPU controls RW & BYTE */
@ -741,6 +782,8 @@ static unsigned int jlf16_set_breakpoint( struct jtdev *p,int bp_num, address_t
return 0;
}
dbg_printc("num=%d addr=%04x\n", bp_num, bp_addr);
if (bp_num < 0) {
/* disable all breakpoints by deleting the BREAKREACT
* register */
@ -790,8 +833,10 @@ static unsigned int jlf16_cpu_state( struct jtdev *p )
jtag_ir_shift(p, IR_EMEX_READ_CONTROL);
if ((jtag_dr_shift_16(p, 0x0000) & 0x0080) == 0x0080) {
dbg_printc("halted\n");
return 1; /* halted */
} else {
dbg_printc("running\n");
return 0; /* running */
}
}

8
drivers/jtaglib_cpuxv2.c
View File

@ -788,7 +788,7 @@ static void jlfxv2_context_save(struct jtdev *p, bool after_puc) {
jtag_tclk_set(p);
jtag_tclk_clr(p);
jtag_ir_shift(p, IR_DATA_CAPTURE);
p->wdtctl = jtag_dr_shift_16(p, 0);
p->wdtctl = jtag_dr_shift_16(p, 0) & 0xff;
jtag_tclk_set(p);
jtag_tclk_clr(p);
jtag_tclk_set(p);
@ -830,9 +830,9 @@ static void jlfxv2_context_save(struct jtdev *p, bool after_puc) {
}
/* disable watchdog */
//p->wdtctl = jtag_read_mem(p, 16, wdtctl_a);
//p->wdtctl = jtag_read_mem(p, 16, wdtctl_a) & 0xff;
dbg_printc("WDTCTL: %04x\n", p->wdtctl);
jtag_write_mem(p, 16, wdtctl_a, p->wdtctl | 0x0080);
jtag_write_mem(p, 16, wdtctl_a, p->wdtctl | 0x5a80);
/* also back up stack pointer & status register */
p->regs[1] = jtag_read_reg(p, 1);
@ -850,7 +850,7 @@ static void jlfxv2_context_restore(struct jtdev *p) {
jtag_write_reg(p, 1, p->regs[1]);
jtag_write_reg(p, 2, p->regs[2]);
jtag_write_mem(p, 16, wdtctl_a, p->wdtctl);
jtag_write_mem(p, 16, wdtctl_a, p->wdtctl | 0x5a00);
jlfxv2_set_pc(p, p->regs[0]);
}