jtaglib: implement breakpoints.
This commit is contained in:
Peter Bägel (DF5EQ)
Daniel Beer
parent
320e560b99
commit
fdaad416b2
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@ -0,0 +1,192 @@
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/*
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* EEM_defs.h
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*
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* <FILEBRIEF>
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _EEM_DEFS_H_
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#define _EEM_DEFS_H_
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#define FALSE 0
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#define TRUE 1
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#define WRITE 0
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#define READ 1
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#define TRIGFLAG 0x8E
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#define EEMVER 0x86
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/* Definition for EEM General Clock Control Register */
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#define GENCLKCTRL 0x88
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/* Definitions for EEM General Clock Control Register */
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#define MCLK_SEL0 0x0000
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#define SMCLK_SEL0 0x0000
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#define ACLK_SEL0 0x0000
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#define MCLK_SEL3 0x6000
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#define SMCLK_SEL3 0x0C00
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#define ACLK_SEL3 0x0180
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#define STOP_MCLK 0x0008
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#define STOP_SMCLK 0x0004
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#define STOP_ACLK 0x0002
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/* Definition for EEM Module Clock Control Register 0 */
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#define MODCLKCTRL0 0x8A
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/* Definition for EEM General Debug Control Register */
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#define GENCTRL 0x82
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/* Definitions for EEM General Debug Control Register */
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#define EEM_EN 0x0001
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#define CLEAR_STOP 0x0002
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#define EMU_CLK_EN 0x0004
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#define EMU_FEAT_EN 0x0008
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#define DEB_TRIG_LATCH 0x0010
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#define EEM_RST 0x0040
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#define E_STOPPED 0x0080
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/* Defintions for Trigger Block base addresses */
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#define TB0 0x0000
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#define TB1 0x0008
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#define TB2 0x0010
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#define TB3 0x0018
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#define TB4 0x0020
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#define TB5 0x0028
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#define TB6 0x0030
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#define TB7 0x0038
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#define TB8 0x0040
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#define TB9 0x0048
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/* Definitions for Trigger Block register addresses */
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#define MBTRIGxVAL 0x0000
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#define MBTRIGxCTL 0x0002
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#define MBTRIGxMSK 0x0004
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#define MBTRIGxCMB 0x0006
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/* Definitions for MAB/MDB Trigger Control Register */
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#define MAB 0x0000
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#define MDB 0x0001
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#define TRIG_0 0x0000 // Instruction Fetch
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#define TRIG_1 0x0002 // Instruction Fetch Hold
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#define TRIG_2 0x0004 // No Instruction Fetch
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#define TRIG_3 0x0006 // Don't care
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#define TRIG_4 0x0020 // No Instruction Fetch & Read
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#define TRIG_5 0x0022 // No Instruction Fetch & Write
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#define TRIG_6 0x0024 // Read
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#define TRIG_7 0x0026 // Write
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#define TRIG_8 0x0040 // No Instruction Fetch & No DMA Access
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#define TRIG_9 0x0042 // DMA Access (Read or Write)
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#define TRIG_A 0x0044 // No DMA Access
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#define TRIG_B 0x0046 // Write & No DMA Access
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#define TRIG_C 0x0060 // No Instruction Fetch & Read & No DMA Access
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#define TRIG_D 0x0062 // Read & No DMA Access
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#define TRIG_E 0x0064 // Read & DMA Access
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#define TRIG_F 0x0066 // Write & DMA Access
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#define CMP_EQUAL 0x0000
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#define CMP_GREATER 0x0008
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#define CMP_LESS 0x0010
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#define CMP_NOT_EQUAL 0x0018
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/* Definitions for MAB/MDB Trigger Mask Register */
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#define NO_MASK 0x00000
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#define MASK_ALL 0xFFFFF
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#define MASK_XADDR 0xF0000
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#define MASK_HBYTE 0x0FF00
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#define MASK_LBYTE 0x000FF
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/* Definitions for MAB/MDB Combination Register & Reaction Registers*/
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#define EN0 0x0001
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#define EN1 0x0002
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#define EN2 0x0004
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#define EN3 0x0008
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#define EN4 0x0010
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#define EN5 0x0020
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#define EN6 0x0040
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#define EN7 0x0080
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#define EN8 0x0100
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#define EN9 0x0200
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#define STOR_CTL 0x9E
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/* Definitions for State Storage Control Register */
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#define VAR_WATCH0 0x0000 // Two
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#define VAR_WATCH1 0x2000 // Four
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#define VAR_WATCH2 0x4000 // Six
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#define VAR_WATCH3 0x6000 // Eight
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#define STOR_FULL 0x0200
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#define STOR_WRIT 0x0100
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#define STOR_TEST 0x0080
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#define STOR_RST 0x0040
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#define STOR_STOP_ON_TRIG 0x0020
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#define STOR_START_ON_TRIG 0x0010
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#define STOR_ONE_SHOT 0x0008
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#define STOR_MODE0 0x0000 // Store on enabled triggers
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#define STOR_MODE1 0x0002 // Store on Instruction Fetch
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#define STOR_MODE2 0x0004 // Variable Watch
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#define STOR_MODE3 0x0006 // Store all bus cycles
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#define STOR_EN 0x0001 // enable state storage
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/* Definitions for Reaction Registers */
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#define STOR_REACT 0x98
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#define BREAKREACT 0x80
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#define EVENT_REACT 0x94
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#define EVENT_CTRL 0x96
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#define EVENT_TRIG 0x0001
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/* Definitions for Cycle Counters */
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#define CCNT0CTL 0xB0
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#define CCNT0L 0xB2
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#define CCNT0H 0xB4
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#define CCNT1CTL 0xB8
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#define CCNT1L 0xBA
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#define CCNT1H 0xBC
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#define CCNT1REACT 0xBE
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/* Definitions for Cycle Counter Control Register */
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#define CCNTMODE0 0x0000 // Counter stopped
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#define CCNTMODE1 0x0001 // Increment on reaction
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#define CCNTMODE4 0x0004 // Increment on instruction fetch cycles
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#define CCNTMODE5 0x0005 // Increment on all bus cycles (including DMA cycles)
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#define CCNTMODE6 0x0006 // Increment on all CPU bus cycles (excluding DMA cycles)
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#define CCNTMODE7 0x0007 // Increment on all DMA bus cycles
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#define CCNT_RST 0x0040
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#define CCNTSTT0 0x0000 // Start when CPU released from JTAG/EEM
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#define CCNTSTT1 0x0100 // Start on reaction CCNT1REACT (only CCNT1)
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#define CCNTSTT2 0x0200 // Start when other (second) counter is started (only if available)
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#define CCNTSTT3 0x0300 // Start immediately
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#define CCNTSTP0 0x0000 // Stop when CPU is stopped by EEM or under JTAG control
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#define CCNTSTP1 0x0400 // Stop on reaction CCNT1REACT (only CCNT1)
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#define CCNTSTP2 0x0800 // Stop when other (second) counter is started (only if available)
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#define CCNTSTP3 0x0C00 // No stop event
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#define CCNTCLR0 0x0000 // No clear event
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#define CCNTCLR1 0x1000 // Clear on reaction CCNT1REACT (only CCNT1)
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#define CCNTCLR2 0x2000 // Clear when other (second) counter is started (only if available)
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#define CCNTCLR3 0x3000 // Reserved
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#define GCC_NONE 0x0000 // No clock control
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#define GCC_STANDARD 0x0001 // Standard clock control
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#define GCC_EXTENDED 0x0002 // Extended clock control
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#endif
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@ -1,6 +1,6 @@
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/* MSPDebug - debugging tool for MSP430 MCUs
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* Copyright (C) 2009-2012 Daniel Beer
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* Copyright (C) 2012-2014 Peter Bägel
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* Copyright (C) 2012-2015 Peter Bägel
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -19,16 +19,23 @@
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/* jtag functions are taken from TIs SLAA149–September 2002
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*
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* breakpoint implementation influenced by a posting of Ruisheng Lin
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* to Travis Goodspeed at 2012-09-20 found at:
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* http://sourceforge.net/p/goodfet/mailman/message/29860790/
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*
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* 2012-10-03 Peter Bägel (DF5EQ)
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* 2012-10-03 initial release Peter Bägel (DF5EQ)
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* 2014-12-26 jtag_single_step added Peter Bägel (DF5EQ)
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* jtag_read_reg corrected
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* jtag_write_reg corrected
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* 2015-02-21 jtag_set_breakpoint added Peter Bägel (DF5EQ)
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* jtag_cpu_state added
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*/
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#include <stdlib.h>
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#include "jtaglib.h"
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#include "output.h"
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#include "eem_defs.h"
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/* JTAG identification value for all existing Flash-based MSP430 devices
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*/
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@ -55,6 +62,10 @@
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#define IR_EX_BLOW 0x24 /* 0x24 */
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/* Bypass instruction */
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#define IR_BYPASS 0xFF /* 0xFF */
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/* Instructions for the EEM */
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#define IR_EMEX_DATA_EXCHANGE 0x90 /* 0x09 */
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#define IR_EMEX_WRITE_CONTROL 0x30 /* 0x0C */
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#define IR_EMEX_READ_CONTROL 0xD0 /* 0x0B */
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#define jtag_tms_set(p) p->f->jtdev_tms(p, 1)
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#define jtag_tms_clr(p) p->f->jtdev_tms(p, 0)
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@ -658,6 +669,9 @@ void jtag_release_device(struct jtdev *p, address_t address)
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case 0xffff: /* Nothing to do */
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break;
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case 0xfffe: /* Perform reset */
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/* delete all breakpoints */
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jtag_set_breakpoint(p,-1,0);
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/* issue reset */
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift(p, 0x2C01);
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jtag_dr_shift(p, 0x2401);
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@ -667,6 +681,15 @@ void jtag_release_device(struct jtdev *p, address_t address)
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break;
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}
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jtag_set_instruction_fetch(p);
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jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE);
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jtag_dr_shift(p, BREAKREACT + READ);
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jtag_dr_shift(p, 0x0000);
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jtag_ir_shift(p, IR_EMEX_WRITE_CONTROL);
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jtag_dr_shift(p, 0x000f);
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jtag_ir_shift(p, IR_CNTRL_SIG_RELEASE);
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}
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@ -1015,3 +1038,78 @@ void jtag_single_step( struct jtdev *p )
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p->failed = 1;
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}
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}
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/*----------------------------------------------------------------------------*/
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unsigned int jtag_set_breakpoint( struct jtdev *p,int bp_num, address_t bp_addr )
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{
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/* The breakpoint logic is explained in 'SLAU414c EEM.pdf' */
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/* A good overview is given with Figure 1-1 */
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/* MBx is TBx in EEM_defs.h */
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/* CPU Stop is BREAKREACT in EEM_defs.h */
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/* State Storage is STOR_REACT in EEM_defs.h */
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/* Cycle Counter is EVENT_REACT in EEM_defs.h */
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unsigned int breakreact;
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if (bp_num >= 8) {
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/* there are no more than 8 breakpoints in EEM */
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printc_err("jtag_set_breakpoint: failed setting "
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"breakpoint %d at %04x\n", bp_num, bp_addr);
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p->failed = 1;
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return 0;
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}
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if (bp_num < 0) {
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/* disable all breakpoints by deleting the BREAKREACT
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* register */
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jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE);
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jtag_dr_shift(p, BREAKREACT + WRITE);
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jtag_dr_shift(p, 0x0000);
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return 1;
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}
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/* set breakpoint */
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jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE);
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jtag_dr_shift(p, GENCTRL + WRITE);
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jtag_dr_shift(p, EEM_EN + CLEAR_STOP + EMU_CLK_EN + EMU_FEAT_EN);
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jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); //repeating may not needed
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jtag_dr_shift(p, 8*bp_num + MBTRIGxVAL + WRITE);
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jtag_dr_shift(p, bp_addr);
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jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); //repeating may not needed
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jtag_dr_shift(p, 8*bp_num + MBTRIGxCTL + WRITE);
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jtag_dr_shift(p, MAB + TRIG_0 + CMP_EQUAL);
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jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); //repeating may not needed
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jtag_dr_shift(p, 8*bp_num + MBTRIGxMSK + WRITE);
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jtag_dr_shift(p, NO_MASK);
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jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); //repeating may not needed
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jtag_dr_shift(p, 8*bp_num + MBTRIGxCMB + WRITE);
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jtag_dr_shift(p, 1<<bp_num);
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/* read the actual setting of the BREAKREACT register */
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/* while reading a 1 is automatically shifted into LSB */
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/* this will be undone and the bit for the new breakpoint set */
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/* then the updated value is stored back */
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jtag_ir_shift(p, IR_EMEX_DATA_EXCHANGE); //repeating may not needed
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breakreact = jtag_dr_shift(p, BREAKREACT + READ);
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breakreact += jtag_dr_shift(p, 0x000);
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breakreact = (breakreact >> 1) | (1 << bp_num);
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jtag_dr_shift(p, BREAKREACT + WRITE);
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jtag_dr_shift(p, breakreact);
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return 1;
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}
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/*----------------------------------------------------------------------------*/
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unsigned int jtag_cpu_state( struct jtdev *p )
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{
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jtag_ir_shift(p, IR_EMEX_READ_CONTROL);
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if ((jtag_dr_shift(p, 0x0000) & 0x0080) == 0x0080) {
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return 1; /* halted */
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} else {
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return 0; /* running */
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}
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}
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@ -1,6 +1,6 @@
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/* MSPDebug - debugging tool for MSP430 MCUs
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* Copyright (C) 2009-2012 Daniel Beer
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* Copyright (C) 2012-2014 Peter Bägel
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* Copyright (C) 2012-2015 Peter Bägel
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -18,10 +18,17 @@
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*/
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/* jtag functions are taken from TIs SLAA149–September 2002
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*
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* breakpoint implementation influenced by a posting of Ruisheng Lin
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* to Travis Goodspeed at 2012-09-20 found at:
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* http://sourceforge.net/p/goodfet/mailman/message/29860790/
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*
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*
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* 2012-10-03 Peter Bägel (DF5EQ)
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* 2012-10-03 initial release Peter Bägel (DF5EQ)
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* 2014-12-26 jtag_single_step added Peter Bägel (DF5EQ)
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* 2015-02-21 jtag_set_breakpoint added Peter Bägel (DF5EQ)
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* jtag_cpu_state added
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*/
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#ifndef JTAGLIB_H_
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@ -105,5 +112,8 @@ address_t jtag_read_reg(struct jtdev *p, int reg);
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/* Writes a value into a register of the target CPU */
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void jtag_write_reg(struct jtdev *p, int reg, address_t value);
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void jtag_single_step(struct jtdev *p);
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unsigned int jtag_set_breakpoint(struct jtdev *p,
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int bp_num, address_t bp_addr);
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unsigned int jtag_cpu_state(struct jtdev *p);
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#endif
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@ -1,6 +1,6 @@
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/* MSPDebug - debugging tool for MSP430 MCUs
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* Copyright (C) 2009-2012 Daniel Beer
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* Copyright (C) 2012-2014 Peter Bägel
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* Copyright (C) 2012-2015 Peter Bägel
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -20,8 +20,9 @@
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/* Driver for parallel port interface like the Olimex MSP430-JTAG
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* Starting point was the goodfet driver
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*
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* 2012-10-03 Peter Bägel (DF5EQ)
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* 2012-10-03 initial release Peter Bägel (DF5EQ)
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* 2014-12-26 single step implemented Peter Bägel (DF5EQ)
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* 2015-02-21 breakpoints implemented Peter Bägel (DF5EQ)
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*/
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#include <stdlib.h>
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@ -147,6 +148,43 @@ struct pif_device {
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struct jtdev jtag;
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};
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/*----------------------------------------------------------------------------*/
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static int refresh_bps(struct pif_device *dev)
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{
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int i;
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int ret;
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struct device_breakpoint *bp;
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address_t addr;
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ret = 0;
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for (i = 0; i < dev->base.max_breakpoints; i++) {
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bp = &dev->base.breakpoints[i];
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printc_dbg("refresh breakpoint %d: type=%d "
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"addr=%04x flags=%04x\n",
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i, bp->type, bp->addr, bp->flags);
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|
||||
if ( (bp->flags & DEVICE_BP_DIRTY) &&
|
||||
(bp->type == DEVICE_BPTYPE_BREAK) ) {
|
||||
addr = bp->addr;
|
||||
|
||||
if ( !(bp->flags & DEVICE_BP_ENABLED) ) {
|
||||
addr = 0;
|
||||
}
|
||||
|
||||
if ( jtag_set_breakpoint (&dev->jtag, i, addr) == 0) {
|
||||
printc_err("pif: failed to refresh "
|
||||
"breakpoint #%d\n", i);
|
||||
ret = -1;
|
||||
} else {
|
||||
bp->flags &= ~DEVICE_BP_DIRTY;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
static int pif_readmem( device_t dev_base,
|
||||
address_t addr,
|
||||
|
|
@ -278,6 +316,10 @@ static int pif_ctl(device_t dev_base, device_ctl_t type)
|
|||
break;
|
||||
|
||||
case DEVICE_CTL_RUN:
|
||||
/* transfer changed breakpoints to device */
|
||||
if (refresh_bps(dev) < 0) {
|
||||
return -1;
|
||||
}
|
||||
/* start program execution at current PC */
|
||||
jtag_release_device(&dev->jtag, 0xffff);
|
||||
break;
|
||||
|
|
@ -303,9 +345,15 @@ static int pif_ctl(device_t dev_base, device_ctl_t type)
|
|||
/*----------------------------------------------------------------------------*/
|
||||
static device_status_t pif_poll(device_t dev_base)
|
||||
{
|
||||
if (delay_ms(100) < 0)
|
||||
struct pif_device *dev = (struct pif_device *)dev_base;
|
||||
|
||||
if (delay_ms(100) < 0 || ctrlc_check())
|
||||
return DEVICE_STATUS_INTR;
|
||||
|
||||
if (jtag_cpu_state(&dev->jtag) == 1) {
|
||||
return DEVICE_STATUS_HALTED;
|
||||
}
|
||||
|
||||
return DEVICE_STATUS_RUNNING;
|
||||
}
|
||||
|
||||
|
|
@ -360,7 +408,7 @@ static device_t pif_open(const struct device_args *args)
|
|||
|
||||
memset(dev, 0, sizeof(*dev));
|
||||
dev->base.type = &device_pif;
|
||||
dev->base.max_breakpoints = 0;
|
||||
dev->base.max_breakpoints = 2; //supported by all devices
|
||||
(&dev->jtag)->f = &jtdev_func_pif;
|
||||
|
||||
if ((&dev->jtag)->f->jtdev_open(&dev->jtag, args->path) < 0) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue