78982 lines
1.4 MiB
78982 lines
1.4 MiB
/* MSP430 chip database
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*
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* THIS FILE WAS GENERATED FROM MSP430.DLL v3.3.1.4
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define CI_DLL430_VERSION_MAJOR 3
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#define CI_DLL430_VERSION_MINOR 3
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#define CI_DLL430_VERSION_PATCH 1
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#define CI_DLL430_VERSION_BUILD 4
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#define CI_DLL430_VERSION_STRING "3.3.1.4"
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static const struct chipinfo_funclet erase_fll = {
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.code_size = 48,
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.max_payload = 4,
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.entry_point = 0x0000,
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.code = {
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0x400a, 0x40b2, 0x5a80, 0x0120,
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0x503a, 0x005c, 0x40ba, 0xbeef,
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0x0000, 0x3c06, 0xffff, 0xffff,
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0xffff, 0xffff, 0xffff, 0xffff,
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0x403b, 0xdead, 0xea2b, 0x23fc,
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0x403b, 0x000a, 0x4982, 0x0128,
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0x450c, 0x40bc, 0xdead, 0x0000,
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0x403c, 0x227a, 0x831c, 0x23fe,
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0x40b2, 0xa500, 0x0128, 0x831b,
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0x23f1, 0x3c08, 0xffff, 0xffff,
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0xffff, 0xffff, 0xffff, 0xffff,
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0xffff, 0xffff, 0x3fff, 0x4303,
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}
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};
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static const struct chipinfo_funclet erase_dco = {
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.code_size = 48,
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.max_payload = 4,
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.entry_point = 0x0000,
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.code = {
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0x400a, 0x40b2, 0x5a80, 0x0120,
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0x4bc2, 0x0056, 0x4cc2, 0x0057,
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0x503a, 0x005c, 0x40ba, 0xbeef,
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0x0000, 0x3c02, 0x0000, 0x0000,
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0x403b, 0xdead, 0xea2b, 0x23fc,
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0x403b, 0x000a, 0x4982, 0x0128,
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0x450c, 0x40bc, 0xdead, 0x0000,
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0x403c, 0x227a, 0x831c, 0x23fe,
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0x40b2, 0xa500, 0x0128, 0x831b,
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0x23f1, 0x40f2, 0x0087, 0x0057,
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0x3c05, 0x0000, 0x0000, 0x0000,
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0x0000, 0x0000, 0x3fff, 0x4303,
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}
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};
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static const struct chipinfo_funclet write_fll = {
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.code_size = 48,
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.max_payload = 128,
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.entry_point = 0x0000,
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.code = {
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0x400a, 0x40b2, 0x5a80, 0x0120,
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0x503a, 0x005c, 0x40ba, 0xbeef,
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0x0000, 0x3c06, 0xffff, 0xffff,
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0xffff, 0xffff, 0xffff, 0xffff,
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0x403b, 0xdead, 0xea2b, 0x23fc,
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0x4a0b, 0x532b, 0x450c, 0x9bac,
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0x0000, 0x240e, 0x40b2, 0xa540,
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0x0128, 0x4bac, 0x0000, 0xb392,
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0x012c, 0x23fd, 0x40b2, 0xa500,
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0x0128, 0x40b2, 0xa500, 0x012c,
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0x532b, 0x532c, 0x8316, 0x23eb,
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0x3c01, 0xffff, 0x3fff, 0x4303,
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}
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};
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static const struct chipinfo_funclet write_430i = {
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.code_size = 48,
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.max_payload = 128,
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.entry_point = 0x0000,
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.code = {
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0x400a, 0x40b2, 0x5a80, 0x0120,
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0x503a, 0x005c, 0x40ba, 0xbeef,
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0x0000, 0x3c06, 0xffff, 0xffff,
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0xffff, 0xffff, 0xffff, 0xffff,
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0x403b, 0xdead, 0xea2b, 0x23fc,
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0x4a0b, 0x532b, 0x450c, 0x40b2,
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0xa540, 0x0128, 0x4bac, 0x0000,
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0xb392, 0x012c, 0x23fd, 0x40b2,
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0xa500, 0x0128, 0x532b, 0x532c,
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0x8316, 0x23f1, 0x40b2, 0xa500,
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0x012c, 0x3c04, 0xffff, 0xffff,
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0xffff, 0xffff, 0x3fff, 0x4303,
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}
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};
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static const struct chipinfo_funclet write_dco = {
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.code_size = 48,
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.max_payload = 128,
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.entry_point = 0x0000,
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.code = {
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0x400a, 0x40b2, 0x5a80, 0x0120,
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0x4bc2, 0x0056, 0x4cc2, 0x0057,
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0x503a, 0x005c, 0x40ba, 0xbeef,
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0x0000, 0x3c02, 0x0000, 0x0000,
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0x403b, 0xdead, 0xea2b, 0x23fc,
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0x4a0b, 0x532b, 0x450c, 0x40b2,
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0xa540, 0x0128, 0x4bac, 0x0000,
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0xb392, 0x012c, 0x23fd, 0x40b2,
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0xa500, 0x0128, 0x40b2, 0xa500,
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0x012c, 0x532b, 0x532c, 0x8316,
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0x23ee, 0x40f2, 0x0087, 0x0057,
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0x3c01, 0x0000, 0x3fff, 0x4303,
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}
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};
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static const struct chipinfo_funclet erase_xfll = {
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.code_size = 54,
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.max_payload = 4,
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.entry_point = 0x0000,
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.code = {
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0x1800, 0x404a, 0x40b2, 0x5a80,
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0x0120, 0x1840, 0x503a, 0x0066,
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0x1840, 0x40ba, 0xbeef, 0x0000,
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0x3c04, 0x0000, 0x0000, 0x0000,
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0x0000, 0x403b, 0xdead, 0x1840,
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0xea1b, 0x0000, 0x23fa, 0x1840,
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0x403b, 0x000a, 0x1840, 0x4982,
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0x0128, 0x1800, 0x454c, 0x1840,
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0x40bc, 0xdead, 0x0000, 0x1840,
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0x403c, 0x227a, 0x832c, 0x23fe,
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0x1840, 0x40b2, 0xa500, 0x0128,
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0x832b, 0x23ec, 0x3c05, 0x0000,
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0x0000, 0x0000, 0x0000, 0x0000,
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0x3fff, 0x4303,
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}
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};
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static const struct chipinfo_funclet erase_xdco = {
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.code_size = 54,
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.max_payload = 4,
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.entry_point = 0x0000,
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.code = {
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0x1800, 0x404a, 0x40b2, 0x5a80,
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0x0120, 0x4bc2, 0x0056, 0x4cc2,
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0x0057, 0x1840, 0x503a, 0x0066,
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0x1840, 0x40ba, 0xbeef, 0x0000,
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0x3c00, 0x403b, 0xdead, 0x1840,
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0xea1b, 0x0000, 0x23fa, 0x1840,
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0x403b, 0x000a, 0x1840, 0x4982,
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0x0128, 0x1800, 0x454c, 0x1840,
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0x40bc, 0xdead, 0x0000, 0x1840,
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0x403c, 0x227a, 0x832c, 0x23fe,
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0x1840, 0x40b2, 0xa500, 0x0128,
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0x832b, 0x23ec, 0x40f2, 0x0087,
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0x0057, 0x3c02, 0x0000, 0x0000,
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0x3fff, 0x4303,
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}
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};
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static const struct chipinfo_funclet write_xfll = {
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.code_size = 54,
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.max_payload = 256,
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.entry_point = 0x0000,
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.code = {
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0x1800, 0x404a, 0x40b2, 0x5a80,
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0x0120, 0x1840, 0x503a, 0x0066,
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0x1840, 0x40ba, 0xbeef, 0x0000,
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0x3c04, 0xffff, 0xffff, 0xffff,
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0xffff, 0x403b, 0xdead, 0x1840,
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0xea1b, 0x0000, 0x23fa, 0x1840,
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0x4a0b, 0x1840, 0x532b, 0x1800,
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0x454c, 0x1840, 0x9bac, 0x0000,
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0x240e, 0x40b2, 0xa540, 0x0128,
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0x4bac, 0x0000, 0xb392, 0x012c,
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0x23fd, 0x40b2, 0xa500, 0x0128,
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0x40b2, 0xa500, 0x012c, 0x03eb,
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0x03ec, 0x8316, 0x23ea, 0x3c00,
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0x3fff, 0x4303,
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}
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};
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static const struct chipinfo_funclet write_xdco = {
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.code_size = 54,
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.max_payload = 256,
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.entry_point = 0x0000,
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.code = {
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0x1800, 0x404a, 0x40b2, 0x5a80,
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0x0120, 0x4bc2, 0x0056, 0x4cc2,
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0x0057, 0x1840, 0x503a, 0x0066,
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0x1840, 0x40ba, 0xbeef, 0x0000,
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0x3c00, 0x403b, 0xdead, 0x1840,
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0xea1b, 0x0000, 0x23fa, 0x1840,
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0x4a0b, 0x1840, 0x532b, 0x1800,
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0x454c, 0x40b2, 0xa540, 0x0128,
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0x4bac, 0x0000, 0xb392, 0x012c,
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0x23fd, 0x40b2, 0xa500, 0x0128,
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0x40b2, 0xa500, 0x012c, 0x03eb,
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0x03ec, 0x8316, 0x23ee, 0x40f2,
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0x0087, 0x0057, 0x3c01, 0x0000,
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0x3fff, 0x4303,
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}
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};
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static const struct chipinfo_funclet erase_xv2_fram = {
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.code_size = 60,
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.max_payload = 0,
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.entry_point = 0x000c,
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.code = {
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0x000c, 0x0076, 0xdead, 0x000b,
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0xdead, 0x000b, 0x40b2, 0x5a80,
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0x015c, 0x180f, 0x4ac0, 0xffee,
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0x180f, 0x4bc0, 0xffec, 0x40b2,
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0x00d0, 0x0186, 0x40b2, 0xabad,
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0x018e, 0x40b2, 0xbabe, 0x018c,
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0xb3a2, 0x0186, 0x27fd, 0x90b2,
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0xbeef, 0x0188, 0x23f9, 0x90b2,
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0xdead, 0x018a, 0x23f5, 0x1800,
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0x454a, 0x1800, 0x464b, 0x43ba,
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0x0000, 0x1800, 0x536a, 0x1800,
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0x836b, 0x930b, 0x23f8, 0x1f80,
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0x405a, 0xffa2, 0x1f80, 0x405b,
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0xffa0, 0x40b2, 0xcafe, 0x018e,
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0x40b2, 0xbabe, 0x018c, 0x3fff,
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}
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};
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static const struct chipinfo_funclet write_xv2_fram = {
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.code_size = 71,
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.max_payload = 0,
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.entry_point = 0x0012,
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.code = {
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0x0012, 0x008c, 0x0000, 0xa500,
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0xa500, 0xdead, 0x000b, 0xdead,
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0x000b, 0x40b2, 0x5a80, 0x015c,
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0x40b2, 0xabad, 0x018e, 0x40b2,
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0xbabe, 0x018c, 0x180f, 0x4ac0,
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0xffe2, 0x180f, 0x4bc0, 0xffe0,
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0x1800, 0x454a, 0x1800, 0x464b,
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0x40b2, 0x00d0, 0x0186, 0xb3a2,
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0x0186, 0x27fd, 0x429a, 0x0188,
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0x0000, 0xc392, 0x0186, 0x1800,
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0x536a, 0x1800, 0x835b, 0x930b,
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0x2001, 0x3c0c, 0x429a, 0x018a,
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0x0000, 0xc3a2, 0x0186, 0x1800,
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0x536a, 0x1800, 0x835b, 0x930b,
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0x23e6, 0x3c00, 0x1f80, 0x405a,
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0xff92, 0x1f80, 0x405b, 0xff90,
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0x40b2, 0xcafe, 0x018e, 0x40b2,
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0xbabe, 0x018c, 0x3fff,
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}
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};
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static const struct chipinfo_funclet bsl_unlock_xv2 = {
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.code_size = 72,
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.max_payload = 0,
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.entry_point = 0x0018,
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.code = {
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0x0018, 0x008e, 0xdead, 0x000b,
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0xdead, 0x000b, 0xdead, 0x000b,
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0xdead, 0x000b, 0xdead, 0x000b,
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0x40b2, 0x5a80, 0x015c, 0x4180,
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0xfff4, 0x180f, 0x4bc0, 0xffea,
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0x180f, 0x4cc0, 0xffd8, 0x180f,
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0x4dc0, 0xffd6, 0x40b2, 0x00d0,
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0x0186, 0x40b2, 0xabad, 0x018e,
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0x40b2, 0xbabe, 0x018c, 0xb3a2,
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0x0186, 0x27fd, 0x90b2, 0xbeef,
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0x0188, 0x23f9, 0x90b2, 0xdead,
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0x018a, 0x23f5, 0x1800, 0x435c,
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0x403d, 0xdead, 0x403e, 0xbeef,
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0x13b0, 0x1002, 0x4011, 0xffa6,
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0x1f80, 0x405b, 0xff9c, 0x1f80,
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0x405c, 0xff8a, 0x1f80, 0x405d,
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0xff88, 0x40b2, 0xcafe, 0x018e,
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0x40b2, 0xbabe, 0x018c, 0x3fff,
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}
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};
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static const struct chipinfo_funclet erase_xv2 = {
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.code_size = 102,
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.max_payload = 0,
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.entry_point = 0x000e,
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.code = {
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0x000e, 0x00ca, 0xa508, 0xa500,
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0xa500, 0xdead, 0x000b, 0x40b2,
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0x5a80, 0x015c, 0x4213, 0xfffe,
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0x4290, 0x0140, 0xffea, 0x4290,
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0x0144, 0xffe6, 0x180f, 0x4ac0,
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0xffe2, 0x40b2, 0x00d0, 0x0186,
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0x40b2, 0xabad, 0x018e, 0x40b2,
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0xbabe, 0x018c, 0xb3a2, 0x0186,
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0x27fd, 0x90b2, 0xbeef, 0x0188,
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0x23f9, 0x90b2, 0xdead, 0x018a,
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0x23f5, 0xb392, 0x0144, 0x23fd,
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0x4882, 0x0144, 0x4290, 0x0144,
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0xffa4, 0x98c0, 0xffa0, 0x2405,
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0x480a, 0xd03a, 0x0040, 0x4a82,
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0x0144, 0x1800, 0x454a, 0x4982,
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0x0140, 0x40ba, 0xdead, 0x0000,
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0xb392, 0x0144, 0x23fd, 0x1f80,
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0x405a, 0xff80, 0xe0b0, 0x3300,
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0xff76, 0xe0b0, 0x3300, 0xff72,
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0x4092, 0xff6c, 0x0140, 0x4092,
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0xff68, 0x0144, 0x4290, 0x0144,
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0xff5c, 0x90d0, 0xff5c, 0xff56,
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0x2406, 0xd0b0, 0x0040, 0xff52,
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0x4092, 0xff4e, 0x0144, 0x40b2,
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0xcafe, 0x018e, 0x40b2, 0xbabe,
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0x018c, 0x3fff,
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}
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};
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static const struct chipinfo_funclet write_xv2 = {
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.code_size = 122,
|
|
.max_payload = 0,
|
|
.entry_point = 0x0012,
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.code = {
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0x0012, 0x00f2, 0xa508, 0xa500,
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0xa500, 0xdead, 0x000b, 0xdead,
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0x000b, 0x40b2, 0x5a80, 0x015c,
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0x40b2, 0xabad, 0x018e, 0x40b2,
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0xbabe, 0x018c, 0x4290, 0x0140,
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0xffde, 0x4290, 0x0144, 0xffda,
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0x180f, 0x4ac0, 0xffd6, 0x180f,
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0x4bc0, 0xffd4, 0xb392, 0x0144,
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0x23fd, 0x4882, 0x0144, 0x4290,
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0x0144, 0xffba, 0x98c0, 0xffb6,
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0x2405, 0x480a, 0xd03a, 0x0040,
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0x4a82, 0x0144, 0x1800, 0x454a,
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0x1800, 0x464b, 0x40b2, 0x00d0,
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0x0186, 0xb3a2, 0x0186, 0x27fd,
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0x40b2, 0xa580, 0x0140, 0x429a,
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0x0188, 0x0000, 0x1800, 0x536a,
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0x1800, 0x835b, 0x429a, 0x018a,
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0x0000, 0xc3a2, 0x0186, 0xc392,
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0x0186, 0xb392, 0x0144, 0x23fd,
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0x40b2, 0xa500, 0x0140, 0x1800,
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0x536a, 0x1800, 0x835b, 0x23e1,
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0x1f80, 0x405a, 0xff5e, 0x1f80,
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0x405b, 0xff5c, 0xe0b0, 0x3300,
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0xff4e, 0xe0b0, 0x3300, 0xff4a,
|
|
0x4092, 0xff44, 0x0140, 0x4092,
|
|
0xff40, 0x0144, 0x4290, 0x0144,
|
|
0xff34, 0x90d0, 0xff34, 0xff2e,
|
|
0x2406, 0xd0b0, 0x0040, 0xff2a,
|
|
0x4092, 0xff26, 0x0144, 0x40b2,
|
|
0xcafe, 0x018e, 0x40b2, 0xbabe,
|
|
0x018c, 0x3fff,
|
|
}
|
|
};
|
|
|
|
static const struct chipinfo_funclet write_xv2_word = {
|
|
.code_size = 144,
|
|
.max_payload = 0,
|
|
.entry_point = 0x0012,
|
|
.code = {
|
|
0x0012, 0x011e, 0xa508, 0xa500,
|
|
0xa500, 0xdead, 0x000b, 0xdead,
|
|
0x000b, 0x40b2, 0x5a80, 0x015c,
|
|
0x40b2, 0xabad, 0x018e, 0x40b2,
|
|
0xbabe, 0x018c, 0x4290, 0x0140,
|
|
0xffde, 0x4290, 0x0144, 0xffda,
|
|
0x180f, 0x4ac0, 0xffd6, 0x180f,
|
|
0x4bc0, 0xffd4, 0xb392, 0x0144,
|
|
0x23fd, 0x4882, 0x0144, 0x4290,
|
|
0x0144, 0xffba, 0x98c0, 0xffb6,
|
|
0x2405, 0x480a, 0xd03a, 0x0040,
|
|
0x4a82, 0x0144, 0x1800, 0x454a,
|
|
0x1800, 0x464b, 0x40b2, 0x00d0,
|
|
0x0186, 0xb392, 0x0186, 0x27fd,
|
|
0x421d, 0x0188, 0xc392, 0x0186,
|
|
0xb392, 0x0144, 0x23fd, 0x40b2,
|
|
0xa500, 0x0140, 0x40b2, 0xa540,
|
|
0x0140, 0x4d8a, 0x0000, 0x1800,
|
|
0x536a, 0x1800, 0x835b, 0x2417,
|
|
0xb3a2, 0x0186, 0x27fd, 0x421e,
|
|
0x018a, 0xc3a2, 0x0186, 0xb392,
|
|
0x0144, 0x23fd, 0x40b2, 0xa500,
|
|
0x0140, 0x40b2, 0xa540, 0x0140,
|
|
0x4e8a, 0x0000, 0x1800, 0x536a,
|
|
0x1800, 0x835b, 0x23d2, 0xb392,
|
|
0x0144, 0x23fd, 0xc3a2, 0x0186,
|
|
0xc392, 0x0186, 0x1f80, 0x405a,
|
|
0xff32, 0x1f80, 0x405b, 0xff30,
|
|
0xe0b0, 0x3300, 0xff22, 0xe0b0,
|
|
0x3300, 0xff1e, 0x4092, 0xff18,
|
|
0x0140, 0x4092, 0xff14, 0x0144,
|
|
0x4290, 0x0144, 0xff08, 0x90d0,
|
|
0xff08, 0xff02, 0x2406, 0xd0b0,
|
|
0x0040, 0xfefe, 0x4092, 0xfefa,
|
|
0x0144, 0x40b2, 0xcafe, 0x018e,
|
|
0x40b2, 0xbabe, 0x018c, 0x3fff,
|
|
}
|
|
};
|
|
|
|
const struct chipinfo chipinfo_db[] = { {
|
|
.name = "DeviceUnknown",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x0000,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x0000,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0xff,
|
|
.fab = 0xff,
|
|
.self = 0xffff,
|
|
.config = 0xff,
|
|
.fuses = 0xff,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0xff,
|
|
.fab = 0xff,
|
|
.self = 0xffff,
|
|
.config = 0xff,
|
|
.fuses = 0xff,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "DeviceUnknown",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 0,
|
|
.offset = 0x00000,
|
|
.seg_size = 0,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "F20x1_G2x0x_G2x1x",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x01f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x01,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x0f800,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "F20x2_G2x2x_G2x3x",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x01f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x02,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x0f800,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F20x3",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x01f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x03,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x0f800,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F11x1",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x12f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x10,
|
|
.fab = 0x40,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0xff,
|
|
.fab = 0xff,
|
|
.self = 0xffff,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F11x1A",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x12f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x13,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0xff,
|
|
.fab = 0x00,
|
|
.self = 0xffff,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5513",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x1355,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F21x1",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x13f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x01,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2132",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x13f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x02,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2122",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x13f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x02,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2112",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x13f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x02,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x0f800,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F41x",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x13f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x02,
|
|
.fab = 0x40,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0xff,
|
|
.fab = 0xff,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x1f] = 0x20,
|
|
[0x21] = 0x24,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_JTAG
|
|
| CHIPINFO_FEATURE_INSTR,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 13,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5514",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x1455,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5515",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x1555,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5517",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x1755,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 6144,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5418",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x1854,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5419",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x1954,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5519",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x1955,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430I204x_I203x_I202x",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x03,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2040,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x49] = 0x53,
|
|
[0x4c] = 0x52,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_430i,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 1024,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01000,
|
|
.seg_size = 1024,
|
|
.bank_size = 1024,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5521",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2155,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5522",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2255,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F12x",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x23f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x1f] = 0x20,
|
|
[0x21] = 0x22,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_JTAG,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5524",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2455,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5525",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2555,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F6125",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2561,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5526",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2655,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 6144,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F6126",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2661,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5527",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2755,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 6144,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F6127",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2761,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2274",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_PSACH,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2254",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_PSACH,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2234",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_PSACH,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2272_G2744",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_PSACH,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2252_G2544",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x05,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_PSACH,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2232_G2444",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_PSACH,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FE427",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FE425",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FE423",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F427",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F425",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x05,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F423",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FG42x0",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2500,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC
|
|
| CHIPINFO_FEATURE_INSTR,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FG4250",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2500,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC
|
|
| CHIPINFO_FEATURE_INSTR,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F42x0",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2500,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC
|
|
| CHIPINFO_FEATURE_INSTR,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F4250",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x05,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2500,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC
|
|
| CHIPINFO_FEATURE_INSTR,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F4230",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2500,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC
|
|
| CHIPINFO_FEATURE_INSTR,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FW42x/F41x",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x27f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x57,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 13,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5528",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2855,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5529",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x2955,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FW429",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x29f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x57,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_INSTR,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F11x2",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3211,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F12x2/F11x2",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3212,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F5133",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3351,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F5135",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3551,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5435",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3554,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 196608,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F6135",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3561,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5436",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3654,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 196608,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F5137",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3751,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5437",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3754,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F6137",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3761,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2370",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x37f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2350",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x37f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2330",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x37f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F43x",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{0},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x37f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5438",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x3854,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FG43x_F43x",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{0},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x39f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 13,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F149",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F148",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F147",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F1471",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 5120,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F135",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F133",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x05,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F1491",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x00,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 5120,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F249",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F248",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F247",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F235",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{0},
|
|
{0},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2491",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2481",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x05,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2471",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F233",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{0},
|
|
{0},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2410",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x08,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x02,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x03,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 57088,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F44x",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USART1", 0x00},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F43x",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{0},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F4794",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD16", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB/MCLK (Pin)", 0x00},
|
|
{"TimerA/SMCLK (Pin)", 0x00},
|
|
{"Watchdog Timer/ACLK (Pin)", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x02,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2560,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F4784",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD16", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB/MCLK (Pin)", 0x00},
|
|
{"TimerA/SMCLK (Pin)", 0x00},
|
|
{"Watchdog Timer/ACLK (Pin)", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x02,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F4793",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD16", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB/MCLK (Pin)", 0x00},
|
|
{"TimerA/SMCLK (Pin)", 0x00},
|
|
{"Watchdog Timer/ACLK (Pin)", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x02,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2560,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F4783",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD16", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB/MCLK (Pin)", 0x00},
|
|
{"TimerA/SMCLK (Pin)", 0x00},
|
|
{"Watchdog Timer/ACLK (Pin)", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x49f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x02,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430G2xx2",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5224,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F4152",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Controller", 0x00},
|
|
{0},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer/RTC", 0x00},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5241,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F4132",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Controller", 0x00},
|
|
{0},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer/RTC", 0x00},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5241,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FE4272",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5242,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x10,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FE42x2",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5242,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x11,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FE4232",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5242,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x12,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE253",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE233",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE223",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE252",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE232",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE222",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE251",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x08,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE231",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0a,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE221",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0b,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE250",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0c,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE230",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0e,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430AFE220",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5302,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430G2xx3",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5325,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430G2x55",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x03,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5529,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x19] = 0x1a,
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 57088,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430TCH5E",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x5c25,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_NO_BSL,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F169",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USART1", 0x00},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x69f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_I2C
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F168",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USART1", 0x00},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x69f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_I2C
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F167",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USART1", 0x00},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x69f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_I2C
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F157",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{0},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x69f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_I2C
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F156",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{0},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x69f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x05,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_I2C
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 24576,
|
|
.offset = 0x0a000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F155",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{0},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x69f1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_I2C
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F1611",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USART1", 0x00},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6cf1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_I2C
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 10240,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F1610",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USART1", 0x00},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6cf1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_I2C
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 5120,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F1612",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USART1", 0x00},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6cf1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_I2C
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 56064,
|
|
.offset = 0x02500,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 5120,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F169",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USART1", 0x00},
|
|
{"USART0", 0x00},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6cf1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
},
|
|
.v3_erase = &erase_dco,
|
|
.v3_write = &write_dco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_1XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_I2C
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2619",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x34,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xdco,
|
|
.v3_write = &write_xdco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 122624,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2618",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x34,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xdco,
|
|
.v3_write = &write_xdco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 118528,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2617",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x34,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xdco,
|
|
.v3_write = &write_xdco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2616",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x34,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xdco,
|
|
.v3_write = &write_xdco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2419",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x34,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xdco,
|
|
.v3_write = &write_xdco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 122624,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2418",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x05,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x34,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xdco,
|
|
.v3_write = &write_xdco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 118528,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2417",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x34,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xdco,
|
|
.v3_write = &write_xdco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F2416",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x34,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xdco,
|
|
.v3_write = &write_xdco,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_BC_2XX,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FG4619",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 122624,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 13,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FG4618",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 118528,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 13,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FG4617",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 13,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FG4616",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{"ADC12", 0x00},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"LCD Frequency", 0x00},
|
|
{"BasicTimer", 0x00},
|
|
{0},
|
|
{"TimerB", 0x00},
|
|
{"TimerA", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x6ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 13,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FG479",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Controller", 0x00},
|
|
{0},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer/RTC", 0x00},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x79f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FG478",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Controller", 0x00},
|
|
{0},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer/RTC", 0x00},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x79f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FG477",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Controller", 0x00},
|
|
{0},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer/RTC", 0x00},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x79f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F479",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Controller", 0x00},
|
|
{0},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer/RTC", 0x00},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x79f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 61184,
|
|
.offset = 0x01100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F478",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Controller", 0x00},
|
|
{0},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer/RTC", 0x00},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x79f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x05,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F477",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Controller", 0x00},
|
|
{0},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BasicTimer/RTC", 0x00},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x79f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x47,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FE427A",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7a42,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FE425A",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7a42,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FE423A",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7a42,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F427A",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7a42,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F425A",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7a42,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x05,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F423A",
|
|
.bits = 16,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x01,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7a42,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x45,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x7f,
|
|
.fuses = 0x1f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x01,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x00,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x00,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x00,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 2700,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2700,
|
|
.vcc_secure_min = 2700,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x21] = 0x23,
|
|
},
|
|
.v3_erase = &erase_fll,
|
|
.v3_write = &write_fll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_SFLLDH
|
|
| CHIPINFO_FEATURE_SYNC,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47197",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 122624,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47187",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x01,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 118528,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47177",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x02,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47167",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x03,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47196",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x04,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 122624,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47186",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x05,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 118528,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47176",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x06,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47166",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x07,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47193",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x08,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 122624,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47183",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x09,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 118528,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47173",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0a,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x03100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47163",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0b,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 93952,
|
|
.offset = 0x02100,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47127",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0c,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 57344,
|
|
.offset = 0x02000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F47126",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x60d7,
|
|
.clock_map = {
|
|
{0},
|
|
{"MCLK (Pin)", 0x00},
|
|
{"SMCLK (Pin)", 0x00},
|
|
{"ACLK (Pin)", 0x00},
|
|
{0},
|
|
{"Flash Control", 0x00},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"BTRTC", 0x29},
|
|
{0},
|
|
{"TimerB3", 0x00},
|
|
{"TimerA3", 0x00},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x7ff4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0d,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x0f,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x00,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x03,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x08,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x00,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x01,
|
|
.seq_start = 0x02,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 2200,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x11] = 0x26,
|
|
[0x12] = 0x27,
|
|
[0x13] = 0x28,
|
|
[0x15] = 0x2a,
|
|
[0x16] = 0x2b,
|
|
[0x18] = 0x2d,
|
|
[0x19] = 0x2e,
|
|
[0x1b] = 0x2f,
|
|
[0x1c] = 0x30,
|
|
[0x1d] = 0x31,
|
|
[0x1e] = 0x32,
|
|
[0x1f] = 0x33,
|
|
[0x21] = 0x35,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xfll,
|
|
.v3_write = &write_xfll,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 57344,
|
|
.offset = 0x02000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01000,
|
|
.seg_size = 64,
|
|
.bank_size = 64,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x00c00,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "lcd",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 21,
|
|
.offset = 0x00090,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x00200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00100,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral8bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 8,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5418A",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8000,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5419A",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8001,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5435A",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8002,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 196608,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5436A",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8003,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 196608,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5437A",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8004,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5438A",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8005,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5438A",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8005,
|
|
.ver_sub_id = 0x0001,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5635",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x800e,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5636",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8010,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5637",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8012,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 196608,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5638",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8014,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6635",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8016,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6636",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8018,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6637",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x801a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 196608,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6638",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x801c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5131",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer1_D3", 0x13},
|
|
{"Timer0_D3", 0x12},
|
|
{"Timer0_A3", 0x08},
|
|
{0},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8026,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5132",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer1_D3", 0x13},
|
|
{"Timer0_D3", 0x12},
|
|
{"Timer0_A3", 0x08},
|
|
{0},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8028,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5151",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer1_D3", 0x13},
|
|
{"Timer0_D3", 0x12},
|
|
{"Timer0_A3", 0x08},
|
|
{0},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x802a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5152",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer1_D3", 0x13},
|
|
{"Timer0_D3", 0x12},
|
|
{"Timer0_A3", 0x08},
|
|
{0},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x802c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5171",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer1_D3", 0x13},
|
|
{"Timer0_D3", 0x12},
|
|
{"Timer0_A3", 0x08},
|
|
{0},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x802e,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5172",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer1_D3", 0x13},
|
|
{"Timer0_D3", 0x12},
|
|
{"Timer0_A3", 0x08},
|
|
{0},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8030,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5510",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8031,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5501",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8032,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5502",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8033,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 24576,
|
|
.offset = 0x0a000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5503",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8034,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5504",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8035,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5505",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8036,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5506",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8037,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 24576,
|
|
.offset = 0x0a000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5507",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8038,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5508",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8039,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5509",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x803a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 24576,
|
|
.offset = 0x0a000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5500",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x803b,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 2,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5630",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x803c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5631",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x803e,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 196608,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5632",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8040,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5633",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8042,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5634",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8044,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 196608,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6630",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8046,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6631",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8048,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 196608,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6632",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x804a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6633",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x804c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6634",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x804e,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 196608,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6720",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8058,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6721",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8059,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6722",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8060,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6723",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8061,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6730",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8062,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6731",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8063,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6732",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8064,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 49152,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6733",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8065,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5721",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{"Timer1_B3", 0x17},
|
|
{"Timer2_B3", 0x18},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8077,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5725",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{"Timer1_B3", 0x17},
|
|
{"Timer2_B3", 0x18},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8078,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5727",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{"Timer1_B3", 0x17},
|
|
{"Timer2_B3", 0x18},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8079,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 15872,
|
|
.offset = 0x0c200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5728",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{0},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x807a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 15872,
|
|
.offset = 0x0c200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5729",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{"Timer1_B3", 0x17},
|
|
{"Timer2_B3", 0x18},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x807b,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 15872,
|
|
.offset = 0x0c200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5730",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{0},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x807c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5731",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{"Timer1_B3", 0x17},
|
|
{"Timer2_B3", 0x18},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x807e,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5733",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{"Timer1_B3", 0x17},
|
|
{"Timer2_B3", 0x18},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x807f,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5734",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{0},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8100,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5737",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{"Timer1_B3", 0x17},
|
|
{"Timer2_B3", 0x18},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8101,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 15872,
|
|
.offset = 0x0c200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5738",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{0},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8102,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 15872,
|
|
.offset = 0x0c200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5739",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{"Timer1_B3", 0x17},
|
|
{"Timer2_B3", 0x18},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8103,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 15872,
|
|
.offset = 0x0c200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5304",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8112,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5308",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8113,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5309",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8114,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 24576,
|
|
.offset = 0x0a000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5310",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8115,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5324",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8116,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5325",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8117,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5326",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8118,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 6144,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5327",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8119,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 6144,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5328",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x811a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5329",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x811b,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5340",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x811c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5341",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x811d,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 6144,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5342",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x811e,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6433",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x811f,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6435",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8121,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6436",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8122,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6438",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8124,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5333",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8125,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5335",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8127,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5336",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8128,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5338",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x812a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6659",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x812b,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0xf0000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6658",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x812c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 393216,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0xf8000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6459",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x812d,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0xf0000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6458",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x812e,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 393216,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0xf8000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5659",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8130,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0xf0000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5658",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"USB", 0x03},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8131,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 393216,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0xf8000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5359",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8132,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0xf0000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5358",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"DAC12", 0x32},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{0},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8133,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2_word,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 393216,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "usbram",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0xf8000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F6147",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8135,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 3968,
|
|
.offset = 0x01c80,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F6145",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8136,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1920,
|
|
.offset = 0x01c80,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F6143",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8137,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1920,
|
|
.offset = 0x01c80,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F5147",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8138,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x08000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 3968,
|
|
.offset = 0x01c80,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F5145",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8139,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1920,
|
|
.offset = 0x01c80,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F5143",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x813a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1920,
|
|
.offset = 0x01c80,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F5125",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x813b,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1920,
|
|
.offset = 0x01c80,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "CC430F5123",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x813c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1920,
|
|
.offset = 0x01c80,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5212",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8140,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5213",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8141,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5214",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8142,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5217",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8145,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5218",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8146,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5219",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8147,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5222",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x814a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5223",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x814b,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5224",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x814c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5227",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x814f,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5228",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8150,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5229",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8151,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5949",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8161,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x12,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0xff,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x0a] = 0x0a,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10018,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5949",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8161,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x20,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0xff,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x0a] = 0x49,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x4f,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10018,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x0c020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5949",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8161,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x21,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0xff,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x0a] = 0x49,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x4f,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10018,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x0c020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5959",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8165,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x30,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0xff,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x0a] = 0x0a,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10018,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5959",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8165,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x31,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0xff,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x0a] = 0x49,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x4f,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10018,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x0c020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5959",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8165,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x40,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0xff,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x0a] = 0x49,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x4f,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10018,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x0c020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5969",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8169,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x30,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0xff,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x0a] = 0x0a,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10018,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5969",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8169,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x31,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0xff,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x0a] = 0x49,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x4f,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10018,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x0c020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5969",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8169,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x40,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0xff,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x0a] = 0x49,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x4f,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10018,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x0c020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
|
|
{
|
|
.name = "MSP430F6734",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x816a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6735",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x816b,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6736",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x816c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6724",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x816d,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 98304,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 3,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6725",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x816e,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6726",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x816f,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04000,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5720",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{0},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8170,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x0f000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5722",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{0},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8171,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5723",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{"Timer1_B3", 0x17},
|
|
{"Timer2_B3", 0x18},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8172,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5724",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{0},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8173,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5726",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{0},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8174,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 15872,
|
|
.offset = 0x0c200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5732",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{0},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8175,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5735",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC10B", 0x37},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{"Timer1_B3", 0x17},
|
|
{"Timer2_B3", 0x18},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8176,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x0e000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5736",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{0},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B3", 0x16},
|
|
{0},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8177,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10010,
|
|
.disable_lpm5 = 0x00018,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 15872,
|
|
.offset = 0x0c200,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1024,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6745",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8188,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6746",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8189,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6747",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x818a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6748",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x818b,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6749",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x818c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6765",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x818d,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6766",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x818e,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6767",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x818f,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6768",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8190,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6769",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8191,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6775",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8192,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6776",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8193,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6777",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8194,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6778",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8195,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F6779",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{"AES128", 0x04},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8196,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67451",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8197,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67461",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8198,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67471",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8199,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67481",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x819a,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67491",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x819b,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67651",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x819c,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67661",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x819d,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67671",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x819e,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67681",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x819f,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67691",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81a0,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67751",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81a1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67761",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81a2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67771",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81a3,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67781",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81a4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F67791",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x2407,
|
|
.clock_map = {
|
|
{0},
|
|
{"eUSCIA3", 0x26},
|
|
{"eUSCIA2", 0x25},
|
|
{"SD24B", 0x35},
|
|
{"ADC10", 0x36},
|
|
{"RTC", 0x28},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"eUSCIB1", 0x3b},
|
|
{"Comparator B", 0x2a},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A2", 0x06},
|
|
{"Timer2_A2", 0x07},
|
|
{"Timer3_A2", 0x0b},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81a5,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x04020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 524288,
|
|
.offset = 0x0c000,
|
|
.seg_size = 512,
|
|
.bank_size = 131072,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6987",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81a6,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6988",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81a7,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 97280,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6989",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81a8,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 130048,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5988",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81aa,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 97280,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5989",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81ab,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 130048,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6977",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81ac,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6978",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81ad,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 97280,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6979",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81ae,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 130048,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5977",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81af,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5978",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81b0,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 97280,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5979",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81b1,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 130048,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6928",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81b3,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 97280,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6929",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{"AES128", 0x04},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81b4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 130048,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6887",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81be,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 64512,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6888",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81bf,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 97280,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR6889",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{"LCDB", 0x2c},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81c0,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 130048,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5888",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81c2,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 97280,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5889",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81c3,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 130048,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5878",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81c8,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 97280,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430FR5879",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0xbdff,
|
|
.clock_map = {
|
|
{"Timer1_A2", 0x06},
|
|
{0},
|
|
{0},
|
|
{"Comparator D", 0x2b},
|
|
{"ADC12B", 0x38},
|
|
{"RTC", 0x28},
|
|
{0},
|
|
{"eUSCIB0", 0x27},
|
|
{"eUSCIA1", 0x24},
|
|
{"eUSCIA0", 0x23},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Timer2_A3", 0x0a},
|
|
{"Timer0_A2", 0x05},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81c9,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x38,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
},
|
|
.v3_erase = &erase_xv2_fram,
|
|
.v3_write = &write_xv2_fram,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_FRAM,
|
|
.power = {
|
|
.reg_mask = 0x10018,
|
|
.enable_lpm5 = 0x10000,
|
|
.disable_lpm5 = 0x10000,
|
|
.reg_mask_3v = 0x0c020,
|
|
.enable_lpm5_3v = 0x04020,
|
|
.disable_lpm5_3v = 0x04020,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 130048,
|
|
.offset = 0x04400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x03c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430SL5438A",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x040f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81ee,
|
|
.ver_sub_id = 0x0001,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x08,
|
|
.cycle_counter = 0x02,
|
|
.cycle_counter_ops = 0x01,
|
|
.trig_emulation_level = 0x07,
|
|
.trig_mem = 0x08,
|
|
.trig_reg = 0x02,
|
|
.trig_combinations = 0x0a,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x02,
|
|
.trig_mem_umask_level = 0x01,
|
|
.seq_states = 0x03,
|
|
.seq_start = 0x04,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 262144,
|
|
.offset = 0x05c00,
|
|
.seg_size = 512,
|
|
.bank_size = 65536,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5249",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81f3,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5247",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81f4,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5244",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81f5,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5242",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81f6,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5239",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81f7,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5237",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81f8,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5234",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81f9,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5232",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81fa,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 65536,
|
|
.offset = 0x04400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 2,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 8192,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5259",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x81ff,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0a400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5258",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8200,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0a400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5257",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8201,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0a400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5256",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8202,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0a400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5255",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8203,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0a400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5254",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8204,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0a400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32768,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5253",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{"ADC12A", 0x38},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8205,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0a400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430F5252",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_ENHANCED,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x041f,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"Comparator B", 0x2a},
|
|
{0},
|
|
{"RTC", 0x28},
|
|
{"USCI3", 0x22},
|
|
{"USCI2", 0x21},
|
|
{"USCI1", 0x20},
|
|
{"USCI0", 0x1f},
|
|
{0},
|
|
{"Timer0_B7", 0x1c},
|
|
{"Timer2_A3", 0x3a},
|
|
{"Timer1_A3", 0x39},
|
|
{"Timer0_A5", 0x0c},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0x8206,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x00000000,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x05,
|
|
.trig_mem = 0x03,
|
|
.trig_reg = 0x01,
|
|
.trig_combinations = 0x04,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x01,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 1800,
|
|
.vcc_max = 3600,
|
|
.vcc_flash_min = 1800,
|
|
.vcc_secure_min = 2500,
|
|
.vpp_secure_min = 6000,
|
|
.vpp_secure_max = 7000,
|
|
.has_test_vpp = 1,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_MOD_OSC,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_LCFE
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ
|
|
| CHIPINFO_FEATURE_1337,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 131072,
|
|
.offset = 0x0a400,
|
|
.seg_size = 512,
|
|
.bank_size = 32768,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "information",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 512,
|
|
.offset = 0x01800,
|
|
.seg_size = 128,
|
|
.bank_size = 128,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "boot",
|
|
.type = CHIPINFO_MEMTYPE_FLASH,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2048,
|
|
.offset = 0x01000,
|
|
.seg_size = 512,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 256,
|
|
.offset = 0x01a00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 16384,
|
|
.offset = 0x02400,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 4,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430L092",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x0417,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"CCS", 0x02},
|
|
{"APOOL", 0x2d},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0xc092,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0x5aa55aa5,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0xffffffff,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x04,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 900,
|
|
.vcc_max = 1800,
|
|
.vcc_flash_min = 0,
|
|
.vcc_secure_min = 0,
|
|
.vpp_secure_min = 0,
|
|
.vpp_secure_max = 0,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1888,
|
|
.offset = 0x0f880,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x02380,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x0f800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "VectorTable",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x0ffe0,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430L092",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x0417,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"CCS", 0x02},
|
|
{"APOOL", 0x2d},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0xc092,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0xa55aa55a,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0xffffffff,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x04,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 900,
|
|
.vcc_max = 1800,
|
|
.vcc_flash_min = 0,
|
|
.vcc_secure_min = 0,
|
|
.vpp_secure_min = 0,
|
|
.vpp_secure_max = 0,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0
|
|
| CHIPINFO_FEATURE_QUICK_MEM_READ,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 1920,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x02380,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2016,
|
|
.offset = 0x0f800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "VectorTable",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x0ffe0,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{
|
|
.name = "MSP430C092",
|
|
.bits = 20,
|
|
.psa = CHIPINFO_PSA_REGULAR,
|
|
.clock_control = 0x02,
|
|
.mclk_control = 0x0417,
|
|
.clock_map = {
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{"CCS", 0x02},
|
|
{"APOOL", 0x2d},
|
|
{0},
|
|
{"Timer0_A3", 0x08},
|
|
{"Timer1_A3", 0x09},
|
|
{"Watchdog Timer", 0x01},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
{0},
|
|
},
|
|
.id = {
|
|
.ver_id = 0xc092,
|
|
.ver_sub_id = 0x0000,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0xdeadbabe,
|
|
},
|
|
.id_mask = {
|
|
.ver_id = 0xffff,
|
|
.ver_sub_id = 0xffff,
|
|
.revision = 0x00,
|
|
.fab = 0x00,
|
|
.self = 0x0000,
|
|
.config = 0x00,
|
|
.fuses = 0x00,
|
|
.activation_key = 0xffffffff,
|
|
},
|
|
.eem = {
|
|
.state_storage = 0x00,
|
|
.cycle_counter = 0x01,
|
|
.cycle_counter_ops = 0x00,
|
|
.trig_emulation_level = 0x04,
|
|
.trig_mem = 0x02,
|
|
.trig_reg = 0x00,
|
|
.trig_combinations = 0x02,
|
|
.trig_options = 0x01,
|
|
.trig_dma = 0x01,
|
|
.trig_read_write = 0x01,
|
|
.trig_reg_ops = 0x00,
|
|
.trig_comp_level = 0x02,
|
|
.trig_mem_cond_level = 0x00,
|
|
.trig_mem_umask_level = 0x00,
|
|
.seq_states = 0x00,
|
|
.seq_start = 0x00,
|
|
.seq_end = 0x00,
|
|
.seq_reset = 0x00,
|
|
.seq_blocked = 0x00,
|
|
},
|
|
.voltage = {
|
|
.vcc_min = 900,
|
|
.vcc_max = 1800,
|
|
.vcc_flash_min = 0,
|
|
.vcc_secure_min = 0,
|
|
.vpp_secure_min = 0,
|
|
.vpp_secure_max = 0,
|
|
.has_test_vpp = 0,
|
|
},
|
|
.v3_functions = {
|
|
[0x09] = 0x37,
|
|
[0x11] = 0x39,
|
|
[0x12] = 0x3a,
|
|
[0x13] = 0x3b,
|
|
[0x14] = 0x3c,
|
|
[0x15] = 0x3c,
|
|
[0x16] = 0x3d,
|
|
[0x17] = 0x3e,
|
|
[0x18] = 0x3e,
|
|
[0x19] = 0x3f,
|
|
[0x1b] = 0x40,
|
|
[0x1c] = 0x41,
|
|
[0x1d] = 0x42,
|
|
[0x1e] = 0x43,
|
|
[0x1f] = 0x44,
|
|
[0x25] = 0x36,
|
|
[0x49] = 0x4a,
|
|
},
|
|
.v3_erase = &erase_xv2,
|
|
.v3_write = &write_xv2,
|
|
.v3_unlock = &bsl_unlock_xv2,
|
|
.clock_sys = CHIPINFO_CLOCK_SYS_FLL_PLUS,
|
|
.features = 0,
|
|
.power = {
|
|
.reg_mask = 0x00000,
|
|
.enable_lpm5 = 0x00000,
|
|
.disable_lpm5 = 0x00000,
|
|
.reg_mask_3v = 0x00000,
|
|
.enable_lpm5_3v = 0x00000,
|
|
.disable_lpm5_3v = 0x00000,
|
|
},
|
|
.memory = {
|
|
{
|
|
.name = "main",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 96,
|
|
.offset = 0x01c00,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "system",
|
|
.type = CHIPINFO_MEMTYPE_RAM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 128,
|
|
.offset = 0x02380,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "bootcode",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 2016,
|
|
.offset = 0x0f800,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "peripheral16bit",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 4096,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "CPU",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 16,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "EEM",
|
|
.type = CHIPINFO_MEMTYPE_REGISTER,
|
|
.bits = 0,
|
|
.mapped = 0,
|
|
.size = 128,
|
|
.offset = 0x00000,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{
|
|
.name = "VectorTable",
|
|
.type = CHIPINFO_MEMTYPE_ROM,
|
|
.bits = 16,
|
|
.mapped = 1,
|
|
.size = 32,
|
|
.offset = 0x0ffe0,
|
|
.seg_size = 1,
|
|
.bank_size = 0,
|
|
.banks = 1,
|
|
},
|
|
{0}
|
|
},
|
|
},
|
|
|
|
{0}
|
|
};
|