193 lines
7.2 KiB
C
193 lines
7.2 KiB
C
/*
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* EEM_defs.h
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*
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* <FILEBRIEF>
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _EEM_DEFS_H_
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#define _EEM_DEFS_H_
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#define FALSE 0
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#define TRUE 1
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#define WRITE 0
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#define READ 1
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#define TRIGFLAG 0x8E
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#define EEMVER 0x86
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/* Definition for EEM General Clock Control Register */
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#define GENCLKCTRL 0x88
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/* Definitions for EEM General Clock Control Register */
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#define MCLK_SEL0 0x0000
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#define SMCLK_SEL0 0x0000
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#define ACLK_SEL0 0x0000
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#define MCLK_SEL3 0x6000
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#define SMCLK_SEL3 0x0C00
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#define ACLK_SEL3 0x0180
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#define STOP_MCLK 0x0008
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#define STOP_SMCLK 0x0004
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#define STOP_ACLK 0x0002
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/* Definition for EEM Module Clock Control Register 0 */
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#define MODCLKCTRL0 0x8A
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/* Definition for EEM General Debug Control Register */
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#define GENCTRL 0x82
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/* Definitions for EEM General Debug Control Register */
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#define EEM_EN 0x0001
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#define CLEAR_STOP 0x0002
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#define EMU_CLK_EN 0x0004
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#define EMU_FEAT_EN 0x0008
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#define DEB_TRIG_LATCH 0x0010
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#define EEM_RST 0x0040
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#define E_STOPPED 0x0080
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/* Defintions for Trigger Block base addresses */
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#define TB0 0x0000
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#define TB1 0x0008
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#define TB2 0x0010
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#define TB3 0x0018
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#define TB4 0x0020
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#define TB5 0x0028
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#define TB6 0x0030
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#define TB7 0x0038
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#define TB8 0x0040
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#define TB9 0x0048
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/* Definitions for Trigger Block register addresses */
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#define MBTRIGxVAL 0x0000
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#define MBTRIGxCTL 0x0002
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#define MBTRIGxMSK 0x0004
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#define MBTRIGxCMB 0x0006
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/* Definitions for MAB/MDB Trigger Control Register */
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#define MAB 0x0000
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#define MDB 0x0001
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#define TRIG_0 0x0000 // Instruction Fetch
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#define TRIG_1 0x0002 // Instruction Fetch Hold
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#define TRIG_2 0x0004 // No Instruction Fetch
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#define TRIG_3 0x0006 // Don't care
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#define TRIG_4 0x0020 // No Instruction Fetch & Read
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#define TRIG_5 0x0022 // No Instruction Fetch & Write
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#define TRIG_6 0x0024 // Read
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#define TRIG_7 0x0026 // Write
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#define TRIG_8 0x0040 // No Instruction Fetch & No DMA Access
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#define TRIG_9 0x0042 // DMA Access (Read or Write)
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#define TRIG_A 0x0044 // No DMA Access
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#define TRIG_B 0x0046 // Write & No DMA Access
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#define TRIG_C 0x0060 // No Instruction Fetch & Read & No DMA Access
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#define TRIG_D 0x0062 // Read & No DMA Access
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#define TRIG_E 0x0064 // Read & DMA Access
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#define TRIG_F 0x0066 // Write & DMA Access
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#define CMP_EQUAL 0x0000
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#define CMP_GREATER 0x0008
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#define CMP_LESS 0x0010
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#define CMP_NOT_EQUAL 0x0018
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/* Definitions for MAB/MDB Trigger Mask Register */
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#define NO_MASK 0x00000
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#define MASK_ALL 0xFFFFF
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#define MASK_XADDR 0xF0000
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#define MASK_HBYTE 0x0FF00
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#define MASK_LBYTE 0x000FF
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/* Definitions for MAB/MDB Combination Register & Reaction Registers*/
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#define EN0 0x0001
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#define EN1 0x0002
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#define EN2 0x0004
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#define EN3 0x0008
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#define EN4 0x0010
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#define EN5 0x0020
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#define EN6 0x0040
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#define EN7 0x0080
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#define EN8 0x0100
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#define EN9 0x0200
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#define STOR_CTL 0x9E
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/* Definitions for State Storage Control Register */
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#define VAR_WATCH0 0x0000 // Two
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#define VAR_WATCH1 0x2000 // Four
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#define VAR_WATCH2 0x4000 // Six
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#define VAR_WATCH3 0x6000 // Eight
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#define STOR_FULL 0x0200
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#define STOR_WRIT 0x0100
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#define STOR_TEST 0x0080
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#define STOR_RST 0x0040
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#define STOR_STOP_ON_TRIG 0x0020
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#define STOR_START_ON_TRIG 0x0010
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#define STOR_ONE_SHOT 0x0008
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#define STOR_MODE0 0x0000 // Store on enabled triggers
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#define STOR_MODE1 0x0002 // Store on Instruction Fetch
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#define STOR_MODE2 0x0004 // Variable Watch
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#define STOR_MODE3 0x0006 // Store all bus cycles
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#define STOR_EN 0x0001 // enable state storage
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/* Definitions for Reaction Registers */
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#define STOR_REACT 0x98
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#define BREAKREACT 0x80
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#define EVENT_REACT 0x94
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#define EVENT_CTRL 0x96
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#define EVENT_TRIG 0x0001
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/* Definitions for Cycle Counters */
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#define CCNT0CTL 0xB0
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#define CCNT0L 0xB2
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#define CCNT0H 0xB4
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#define CCNT1CTL 0xB8
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#define CCNT1L 0xBA
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#define CCNT1H 0xBC
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#define CCNT1REACT 0xBE
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/* Definitions for Cycle Counter Control Register */
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#define CCNTMODE0 0x0000 // Counter stopped
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#define CCNTMODE1 0x0001 // Increment on reaction
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#define CCNTMODE4 0x0004 // Increment on instruction fetch cycles
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#define CCNTMODE5 0x0005 // Increment on all bus cycles (including DMA cycles)
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#define CCNTMODE6 0x0006 // Increment on all CPU bus cycles (excluding DMA cycles)
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#define CCNTMODE7 0x0007 // Increment on all DMA bus cycles
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#define CCNT_RST 0x0040
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#define CCNTSTT0 0x0000 // Start when CPU released from JTAG/EEM
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#define CCNTSTT1 0x0100 // Start on reaction CCNT1REACT (only CCNT1)
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#define CCNTSTT2 0x0200 // Start when other (second) counter is started (only if available)
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#define CCNTSTT3 0x0300 // Start immediately
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#define CCNTSTP0 0x0000 // Stop when CPU is stopped by EEM or under JTAG control
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#define CCNTSTP1 0x0400 // Stop on reaction CCNT1REACT (only CCNT1)
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#define CCNTSTP2 0x0800 // Stop when other (second) counter is started (only if available)
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#define CCNTSTP3 0x0C00 // No stop event
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#define CCNTCLR0 0x0000 // No clear event
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#define CCNTCLR1 0x1000 // Clear on reaction CCNT1REACT (only CCNT1)
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#define CCNTCLR2 0x2000 // Clear when other (second) counter is started (only if available)
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#define CCNTCLR3 0x3000 // Reserved
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#define GCC_NONE 0x0000 // No clock control
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#define GCC_STANDARD 0x0001 // Standard clock control
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#define GCC_EXTENDED 0x0002 // Extended clock control
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#endif
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