712 lines
18 KiB
C
712 lines
18 KiB
C
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#include <stdbool.h>
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#include "jtaglib.h"
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#include "jtaglib_defs.h"
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#include "output.h"
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#define SAFE_FRAM_PC 0x0004
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// FIXME:
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// * read reg (nonsense values)
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// * write reg?
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// * implement flash write, erase, verify stuff
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// * other stuff?
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// * single step: check if it works
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// * breakpoints are a big TODO
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static int jlfxv2_check_full_emu_state_ex(struct jtdev *p, const char* fnname)
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{ // see SLAU320AJ ExecutePOR
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uint16_t dr;
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uint8_t jtag_id;
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for (int i = 0; i < 1/*10*/; ++i) {
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jtag_id = jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
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if (((dr = jtag_dr_shift_16(p, 0)) & 0x0301) == 0x0301) {
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return 1; // OK
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}
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printc_err("jlfxv2: %s: not in full emu state, while expected!"
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" (dr=%04x jid=%02x)\n", fnname, dr, jtag_id);
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}
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p->failed = 1;
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return 0;
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}
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#define jlfxv2_check_full_emu_state(p) jlfxv2_check_full_emu_state_ex((p), __func__)
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static void jlfxv2_set_pc(struct jtdev *p, address_t addr)
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{
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printc_dbg("set pc %06x\n", addr);
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jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
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jtag_dr_shift_16(p, 0);
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jtag_tclk_clr(p);
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jtag_ir_shift(p, IR_DATA_16BIT);
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jtag_tclk_set(p);
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jtag_dr_shift_16(p, 0x0080 | ((addr >> 8) & 0x0f00));
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jtag_tclk_clr(p);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x1400);
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jtag_ir_shift(p, IR_DATA_16BIT);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_dr_shift_16(p, addr & 0xffff);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_dr_shift_16(p, 0x4303);
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jtag_tclk_clr(p);
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jtag_ir_shift(p, IR_ADDR_CAPTURE);
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jtag_dr_shift_20(p, 0);
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}
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/* Compares the computed PSA (Pseudo Signature Analysis) value to the PSA
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* value shifted out from the target device. It is used for very fast data
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* block write or erasure verification.
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* start_address: start of data
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* length : number of data
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* data : pointer to data, 0 for erase check
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* RETURN : 1 - comparison was successful
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* 0 - otherwise
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*/
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static int jlfxv2_verify_mem(struct jtdev *p,
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unsigned int start_address,
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unsigned int length,
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const uint16_t *data)
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{ // SLAU320AJ name: VerifyMem/VerifyPSA
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uint16_t crc, psaval;
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jtag_execute_puc(p);
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crc = start_address - 2;
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jlfxv2_set_pc(p, start_address);
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jtag_tclk_set(p);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x0501);
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jtag_ir_shift(p, IR_DATA_16BIT);
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jtag_dr_shift_16(p, start_address - 2);
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jtag_ir_shift(p, IR_DATA_PSA);
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for (unsigned int addr = 0; addr < length; ++addr) {
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if (crc & 0x8000) {
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crc ^= 0x0805;
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crc <<= 1;
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crc |= 1;
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} else {
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crc <<= 1;
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}
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if (data) crc ^= data[addr];
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else crc ^= 0xffff;
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jtag_tclk_clr(p);
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/* Go through DR path without shifting data in/out */
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jtag_tms_sequence(p, 6, 0x19); /* TMS=1 0 0 1 1 0 ; 6 clocks */
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jtag_tclk_set(p);
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}
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jtag_ir_shift(p, IR_SHIFT_OUT_PSA);
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psaval = jtag_dr_shift_16(p, 0);
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jtag_execute_puc(p);
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return (psaval == crc) ? 1 : 0;
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}
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/* ------------------------------------------------------------------------- */
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static int jlfxv2_erase_check(struct jtdev *p, unsigned int start_address,
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unsigned int length)
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{
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return jlfxv2_verify_mem(p, start_address, length, NULL);
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}
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static unsigned int jlfxv2_get_device(struct jtdev *p)
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{ // SLAU320AJ name: GetDevice (and SyncJtag_AssertPor)
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unsigned int jtag_id = 0;
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int i;
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x1501);
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jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
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for (i = 0; i < 50; ++i) {
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if ((jtag_dr_shift_16(p, 0) & (1<<9)) == (1<<9))
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break;
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}
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if (i == 50) {
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printc_err("jlfxv2_get_device: failed\n");
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p->failed = 1;
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return 0;
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}
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jtag_id = jtag_execute_puc(p);
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return jtag_id;
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}
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static void jlfxv2_read_mem_quick(struct jtdev *p, address_t address,
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unsigned int length, uint16_t *data);
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/* Reads one byte/word from a given address
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* format : 8-byte, 16-word
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* address: address of memory
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* return : content of memory
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*/
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static uint16_t jlfxv2_read_mem(struct jtdev *p, unsigned int format, address_t address)
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{ // SLAU320AJ name: ReadMem
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uint16_t r = 0;
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if (!jlfxv2_check_full_emu_state(p))
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return 0;
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// the code below (an attempt at implementing the real read_mem) doesn't
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// work, so let's use read_mem_quick as a backup
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jlfxv2_read_mem_quick(p, address ^ (address & 1), 1, &r);
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if (format == 8) {
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if (address & 1) return (r >> 8) & 0xff;
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else return r & 0xff;
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} else return r;
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/*//jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
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//uint16_t dr = jtag_dr_shift_16(p, 0);
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jtag_tclk_clr(p);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, (format == 16) ? 0x0501 : 0x0511);
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jtag_ir_shift(p, IR_ADDR_16BIT);
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jtag_dr_shift_20(p, address);
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jtag_ir_shift(p, IR_DATA_TO_ADDR);
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jtag_tclk_set(p);
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jtag_tclk_clr(p);
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jtag_ir_shift(p, IR_DATA_CAPTURE);
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r = jtag_dr_shift_16(p, 0);
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jtag_tclk_set(p);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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return r;*/
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}
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/* Reads an array of words from target memory
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* address: address to read from
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* length : number of word to read
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* data : memory to write to
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*/
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static void jlfxv2_read_mem_quick(struct jtdev *p, address_t address,
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unsigned int length, uint16_t *data)
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{ // SLAU320AJ name: ReadMemQuick
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address_t pc_bak;
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if (!jlfxv2_check_full_emu_state(p))
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return;
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//pc_bak = jlfxv2_read_reg(p, 0); // FIXME
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jlfxv2_set_pc(p, address);
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//jtag_tclk_set(p);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x0501);
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jtag_tclk_set(p);
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jtag_ir_shift(p, IR_ADDR_CAPTURE);
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jtag_ir_shift(p, IR_DATA_QUICK);
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for (unsigned int i = 0; i < length; ++i) {
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jtag_tclk_set(p);
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jtag_tclk_clr(p);
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data[i] = jtag_dr_shift_16(p, 0);
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}
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jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
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jtag_dr_shift_16(p, 0);
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jlfxv2_set_pc(p, SAFE_FRAM_PC);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x0501);
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jtag_tclk_set(p);
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jtag_ir_shift(p, IR_ADDR_CAPTURE);
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//jlfxv2_write_reg(p, 0, pc_bak); // FIXME
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}
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static void jlfxv2_write_mem_quick(struct jtdev *p, address_t address,
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unsigned int length, const uint16_t *data);
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/* Writes one byte/word at a given address
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* format : 8-byte, 16-word
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* address: address to be written
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* data : data to write
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*/
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static void jlfxv2_write_mem(struct jtdev *p, unsigned int format,
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address_t address, uint16_t data)
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{ // SLAU320AJ name: WriteMem
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printc_dbg("jlfxv2 write mem: %d %06x <- %04x\n", format, address, data);
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if (format == 8) {
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p->failed = 1;
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printc_err("jlfxv2 write mem: byte access not yet implemented!\n");
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return;
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}
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// same story as with read_mem
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jlfxv2_write_mem_quick(p, address, 1, &data);
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/*if (!jlfxv2_check_full_emu_state(p))
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return;
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jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
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uint16_t dr = jtag_dr_shift_16(p, 0);
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printc_dbg("write mem %d: %06x<-%04x: dr=%04x\n", format, address, data, dr);
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jtag_tclk_clr(p);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, (format == 16) ? 0x0500 : 0x0510);
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jtag_ir_shift(p, IR_ADDR_16BIT);
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jtag_dr_shift_20(p, address);
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jtag_tclk_set(p);
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jtag_ir_shift(p, IR_DATA_TO_ADDR);
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jtag_dr_shift_16(p, data);
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jtag_tclk_clr(p);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x0501);
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jtag_tclk_set(p);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);*/
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}
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/* Writes an array of words into target memory
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* address: address to write to
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* length : number of word to write
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* data : data to write
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*/
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static void jlfxv2_write_mem_quick(struct jtdev *p, address_t address,
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unsigned int length, const uint16_t *data)
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{ // SLAU320AJ name: WriteMemQuick
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uint16_t pc_bak;
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/*for (unsigned int i = 0; i < length; ++i) {
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jlfxv2_write_mem(p, 16, address + i*2, data[i]);
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}*/
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if (!jlfxv2_check_full_emu_state(p))
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return;
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//pc_bak = jlfxv2_read_reg(p, 0); // FIXME
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jlfxv2_set_pc(p, address);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x0500);
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jtag_tclk_set(p);
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jtag_ir_shift(p, IR_DATA_QUICK);
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for (unsigned int i = 0; i < length; ++i) {
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jtag_tclk_set(p);
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jtag_dr_shift_16(p, data[i]);
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jtag_tclk_clr(p);
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}
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x0501);
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jtag_tclk_set(p);
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jlfxv2_set_pc(p, SAFE_FRAM_PC);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x0501);
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jtag_tclk_set(p);
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jtag_ir_shift(p, IR_ADDR_CAPTURE);
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//jlfxv2_write_reg(p, 0, pc_bak);
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}
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/* Execute a Power-Up Clear (PUC) using JTAG CNTRL SIG register
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* return: JTAG ID
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*/
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static unsigned int jlfxv2_execute_puc(struct jtdev *p)
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{ // SLAU320AJ name: ExecutePOR
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unsigned int jtag_id;
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jtag_id = jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
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// empty CPU pipeline
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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/* Apply and remove reset */
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jtag_dr_shift_16(p, 0x0C01);
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jtag_dr_shift_16(p, 0x0401);
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if (jtag_id == 0x91) { // TODO: is this correct?
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_tclk_clr(p); // two more cycles to release CPU internal POR delay signals
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jtag_tclk_set(p);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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} else { // FRAM
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jtag_ir_shift(p, IR_DATA_16BIT);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_dr_shift_16(p, SAFE_FRAM_PC);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_ir_shift(p, IR_DATA_CAPTURE);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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}
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x0501);
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jtag_tclk_clr(p);
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jtag_tclk_set(p);
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jtag_write_mem(p, 16, 0x015c, 0x5a80); // disable WDT
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// TODO: disable WDT
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// Disable Watchdog Timer on target device now by setting the HOLD signal
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// in the WDT_CNTRL register (i.e. by using WriteMem_430Xv2 – note
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// different WDT addresses for individual FRAM device groups)
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//
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// Initialize Test Memory with default values to ensure consistency between
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// PC value and MAB (MAB is +2 after sync) – Use WriteMem_430Xv2 to write
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// 0x3FFF to addresses 0x06 and 0x08 (this is only applicable for devices
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// with JTAG ID 0x91 or 0x99)
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return jtag_id;
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}
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/* Release the target device from JTAG control
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* address: 0xFFFE - perform Reset,
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* load Reset Vector into PC
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* 0xFFFF - start execution at current
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* PC position
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* other - load Address into PC
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*/
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static void jlfxv2_release_device(struct jtdev *p, address_t address)
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{ // SLAU320AJ name: ReleaseDevice. from Replicator430 code, not in the PDF
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switch (address) {
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case 0xffff: // BOR
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jtag_ir_shift(p, IR_TEST_REG);
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jtag_dr_shift_16(p, 0x0200);
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delay_ms(5);
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break;
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case 0xfffe: // reset
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x0C01);
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jtag_dr_shift_16(p, 0x0401);
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jtag_ir_shift(p, IR_CNTRL_SIG_RELEASE);
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break;
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default:
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jlfxv2_set_pc(p, address);
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jtag_tclk_set(p);
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jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
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jtag_dr_shift_16(p, 0x0401);
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jtag_ir_shift(p, IR_ADDR_CAPTURE);
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jtag_ir_shift(p, IR_CNTRL_SIG_RELEASE);
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break;
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}
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}
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/* Programs/verifies an array of words into a FLASH by using the
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* FLASH controller. The JTAG FLASH register isn't needed.
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* start_address: start in FLASH
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* length : number of words
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* data : pointer to data
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*/
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static void jlfxv2_write_flash(struct jtdev *p, address_t start_address,
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unsigned int length, const uint16_t *data)
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{ // SLAU320AJ name: WriteFLASH
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}
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/* Performs a mass erase (with and w/o info memory) or a segment erase of a
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* FLASH module specified by the given mode and address. Large memory devices
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* get additional mass erase operations to meet the spec.
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* erase_mode : ERASE_MASS, ERASE_MAIN, ERASE_SGMT
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* erase_address: address within the selected segment
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*/
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static void jlfxv2_erase_flash(struct jtdev *p, unsigned int erase_mode,
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address_t erase_address)
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{ // SLAU320AJ name: EraseFLASH
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}
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/* Reads a register from the target CPU */
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static address_t jlfxv2_read_reg(struct jtdev *p, int reg)
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{ // libmsp430 BIOS name: ReadCpuReg
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uint16_t reglo, reghi;
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uint16_t jtag_id, jmb_addr;
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const bool alt_addr = false;//true;
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if (reg == 2 || reg == 3) return 0; // CG
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printc_dbg("read reg %d\n", reg);
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if (!jlfxv2_check_full_emu_state(p))
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return 0;
|
||
|
||
jtag_id = jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
|
||
jtag_tclk_clr(p);
|
||
jtag_ir_shift(p, IR_DATA_16BIT);
|
||
jtag_tclk_set(p);
|
||
jtag_dr_shift_16(p, ((reg << 8) & 0x0f00) | 0x0060);
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
|
||
jtag_dr_shift_16(p, 0x1401);
|
||
jtag_ir_shift(p, IR_DATA_16BIT);
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
|
||
if (alt_addr) {
|
||
jtag_dr_shift_16(p, 0x0ff6);
|
||
} else {
|
||
jmb_addr = (jtag_id == 0x98) ? 0x14c : 0x18c;
|
||
jtag_dr_shift_16(p, jmb_addr);
|
||
}
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
jtag_dr_shift_16(p, 0x3ffd);
|
||
jtag_tclk_clr(p);
|
||
|
||
if (alt_addr) {
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
|
||
jtag_dr_shift_16(p, 0x0501);
|
||
}
|
||
|
||
jtag_ir_shift(p, IR_DATA_CAPTURE);
|
||
jtag_tclk_set(p);
|
||
reglo = jtag_dr_shift_16(p, 0);
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
reghi = jtag_dr_shift_16(p, 0);
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
|
||
if (!alt_addr) {
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
|
||
jtag_dr_shift_16(p, 0x0501);
|
||
}
|
||
|
||
jtag_tclk_clr(p);
|
||
jtag_ir_shift(p, IR_DATA_CAPTURE);
|
||
jtag_tclk_set(p);
|
||
|
||
printc_dbg("read reg %d: lo=%04x hi=%04x\n", reg, reglo, reghi);
|
||
|
||
jlfxv2_set_pc(p, SAFE_FRAM_PC);
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
|
||
jtag_dr_shift_16(p, 0x0501);
|
||
jtag_tclk_set(p);
|
||
jtag_ir_shift(p, IR_ADDR_CAPTURE);
|
||
|
||
return reglo | ((address_t)reghi << 16);
|
||
}
|
||
|
||
/* Writes a value into a register of the target CPU */
|
||
static void jlfxv2_write_reg(struct jtdev *p, int reg, address_t value)
|
||
{ // SLAU320AJ name: SetPC
|
||
jlfxv2_check_full_emu_state(p);
|
||
printc_dbg("write reg %d %06x\n", reg, value);
|
||
|
||
/*jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
|
||
jtag_dr_shift_16(p, 0);*/
|
||
|
||
jtag_tclk_clr(p);
|
||
jtag_ir_shift(p, IR_DATA_16BIT);
|
||
jtag_tclk_set(p);
|
||
jtag_dr_shift_16(p, 0x0080 | ((value >> 8) & 0x0f00) | (reg & 0xf));
|
||
|
||
//jtag_tclk_clr(p);
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
|
||
jtag_dr_shift_16(p, 0x1401/*1400*/);
|
||
jtag_ir_shift(p, IR_DATA_16BIT);
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
jtag_dr_shift_16(p, value & 0xffff);
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
|
||
jtag_dr_shift_16(p, 0x3ffd); // rewind PC
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
jtag_tclk_clr(p);
|
||
|
||
jtag_ir_shift(p, IR_ADDR_CAPTURE);
|
||
jtag_dr_shift_20(p, 0);
|
||
jtag_tclk_set(p);
|
||
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
|
||
jtag_dr_shift_16(p, /*0x4303*/0x0501); // insert NOP to be prefetched by the CPU
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
jtag_tclk_clr(p);
|
||
|
||
jtag_ir_shift(p, IR_DATA_CAPTURE);
|
||
jtag_tclk_set(p);
|
||
//jtag_dr_shift_20(p, 0);
|
||
}
|
||
|
||
/*----------------------------------------------------------------------------*/
|
||
static void jlfxv2_single_step( struct jtdev *p )
|
||
{ // libmsp430 BIOS name: SingleStep
|
||
|
||
int i, timeout;
|
||
uint16_t tmp;
|
||
printc_dbg("jlfxv2: single step\n");
|
||
|
||
/*jtag_ir_shift(p, IR_EMEX_READ_CONTROL);
|
||
timeout = 3000;
|
||
for (i = 0; i < timeout; ++i)
|
||
if (jtag_dr_shift_16(p, 0) & EEM_STOPPED)
|
||
break;
|
||
if (i == timeout) {
|
||
printc_err("jlfxv2_single_step: EEM timeout\n");
|
||
goto err;
|
||
}*/
|
||
|
||
jtag_ir_shift(p, IR_EMEX_WRITE_CONTROL);
|
||
jtag_dr_shift_16(p, EMU_CLK_EN | EEM_EN);
|
||
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
|
||
jtag_dr_shift_16(p, 0x1501);
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
|
||
timeout = 50;
|
||
for (i = 0; i < timeout; ++i) {
|
||
tmp = jtag_dr_shift_16(p, 0);
|
||
if (tmp != 0xffff && (tmp & 0x200) == 0x0200)
|
||
break;
|
||
}
|
||
if (i == timeout) {
|
||
printc_err("jlfxv2_single_step: JTAG sync timeout\n");
|
||
goto err;
|
||
}
|
||
|
||
jtag_ir_shift(p, IR_EMEX_WRITE_CONTROL);
|
||
jtag_dr_shift_16(p, EMU_CLK_EN | CLEAR_STOP);
|
||
jtag_dr_shift_16(p, EMU_CLK_EN | CLEAR_STOP | EEM_EN);
|
||
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
|
||
jtag_dr_shift_16(p, 0x1501);
|
||
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
|
||
timeout = 30000;
|
||
for (i = 0; i < timeout; ++i) {
|
||
if ((jtag_dr_shift_16(p, 0) & 8) == 0) break;
|
||
|
||
jtag_tclk_clr(p);
|
||
jtag_tclk_set(p);
|
||
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
|
||
}
|
||
if (i == timeout) {
|
||
printc_err("jlfxv2_single_step: single-step timeout\n");
|
||
goto err;
|
||
}
|
||
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_CAPTURE);
|
||
timeout = 10000;
|
||
for (i = 0; i < timeout; ++i) {
|
||
jtag_tclk_clr(p);
|
||
tmp = jtag_dr_shift_16(p, 0);
|
||
jtag_tclk_set(p);
|
||
|
||
if ((tmp & CNTRL_SIG_CPUSUSP) == CNTRL_SIG_CPUSUSP) break;
|
||
}
|
||
if (i == timeout) {
|
||
printc_err("jlfxv2_single_step: pipeline empty timeout\n");
|
||
goto err;
|
||
}
|
||
|
||
jtag_ir_shift(p, IR_CNTRL_SIG_16BIT);
|
||
jtag_dr_shift_16(p, 0x0501);
|
||
|
||
return;
|
||
err:
|
||
p->failed = 1;
|
||
}
|
||
|
||
/*----------------------------------------------------------------------------*/
|
||
static unsigned int jlfxv2_set_breakpoint( struct jtdev *p,int bp_num, address_t bp_addr )
|
||
{
|
||
/* The breakpoint logic is explained in 'SLAU414c EEM.pdf' */
|
||
/* A good overview is given with Figure 1-1 */
|
||
/* MBx is TBx in EEM_defs.h */
|
||
/* CPU Stop is BREAKREACT in EEM_defs.h */
|
||
/* State Storage is STOR_REACT in EEM_defs.h */
|
||
/* Cycle Counter is EVENT_REACT in EEM_defs.h */
|
||
|
||
return 0;
|
||
}
|
||
|
||
/*----------------------------------------------------------------------------*/
|
||
static unsigned int jlfxv2_cpu_state( struct jtdev *p )
|
||
{ // libmsp430 BIOS name: WaitForEem(?)
|
||
// TODO: does this need an update?
|
||
jtag_ir_shift(p, IR_EMEX_READ_CONTROL);
|
||
|
||
if ((jtag_dr_shift_16(p, 0x0000) & EEM_STOPPED) == EEM_STOPPED) {
|
||
printc_dbg("jlfxv2_cpu_state: halted\n");
|
||
return 1; /* halted */
|
||
} else {
|
||
printc_dbg("jlfxv2_cpu_state: running\n");
|
||
return 0; /* running */
|
||
}
|
||
}
|
||
|
||
/*----------------------------------------------------------------------------*/
|
||
static int jlfxv2_get_config_fuses( struct jtdev *p )
|
||
{ // always the same?
|
||
// TODO: does this need an update?
|
||
jtag_ir_shift(p, IR_CONFIG_FUSES);
|
||
|
||
return jtag_dr_shift_8(p, 0);
|
||
}
|
||
|
||
/* ------------------------------------------------------------------------- */
|
||
|
||
const struct jtaglib_funcs jlf_cpuxv2 = {
|
||
.jlf_get_device = jlfxv2_get_device,
|
||
|
||
.jlf_read_mem = jlfxv2_read_mem,
|
||
.jlf_read_mem_quick = jlfxv2_read_mem_quick,
|
||
.jlf_write_mem = jlfxv2_write_mem,
|
||
.jlf_write_mem_quick = jlfxv2_write_mem_quick,
|
||
|
||
.jlf_execute_puc = jlfxv2_execute_puc,
|
||
.jlf_release_device = jlfxv2_release_device,
|
||
|
||
.jlf_verify_mem = jlfxv2_verify_mem,
|
||
.jlf_erase_check = jlfxv2_erase_check,
|
||
|
||
.jlf_write_flash = jlfxv2_write_flash,
|
||
.jlf_erase_flash = jlfxv2_erase_flash,
|
||
|
||
.jlf_read_reg = jlfxv2_read_reg,
|
||
.jlf_write_reg = jlfxv2_write_reg,
|
||
.jlf_single_step = jlfxv2_single_step,
|
||
.jlf_set_breakpoint = jlfxv2_set_breakpoint,
|
||
.jlf_cpu_state = jlfxv2_cpu_state,
|
||
.jlf_get_config_fuses = jlfxv2_get_config_fuses,
|
||
};
|
||
|