387 lines
12 KiB
C
387 lines
12 KiB
C
/* MSPDebug - debugging tool for MSP430 MCUs
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* Copyright (C) 2009-2011 Daniel Beer
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef TILIB_DEFS_H_
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#define TILIB_DEFS_H_
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/* This header file contains various constants used by the TI MSP430
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* library. The original copyright notice is:
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*
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* Copyright (C) 2004 - 2011 Texas Instruments Incorporated -
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* http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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/* this is the definition for the DLL functions return value */
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typedef long STATUS_T;
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typedef long LONG;
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typedef unsigned long ULONG;
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typedef char CHAR;
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typedef uint16_t WORD;
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typedef uint8_t BYTE;
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enum READ_WRITE {
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WRITE = 0,
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READ = 1,
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};
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enum RESET_METHOD {
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PUC_RESET = (1 << 0), /**< Power up clear (i.e., a "soft") reset */
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RST_RESET = (1 << 1), /**< RST/NMI (i.e., "hard") reset */
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VCC_RESET = (1 << 2), /**< Cycle Vcc (i.e., a "power on") reset */
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FORCE_RESET = (1 << 3)
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};
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/* FLASH erase type. */
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enum ERASE_TYPE {
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ERASE_SEGMENT = 0, /**< Erase a segment */
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ERASE_MAIN = 1, /**< Erase all MAIN memory */
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ERASE_ALL = 2, /**< Erase all MAIN and INFORMATION memory */
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};
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/* Run modes. */
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enum RUN_MODES {
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/* Run the device. Set breakpoints (if any) are disabled */
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FREE_RUN = 1,
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/* A single device instruction is executed. Interrupt
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* processing is supported
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*/
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SINGLE_STEP = 2,
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/* Run the device. Set breakpoints (if any) are enabled */
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RUN_TO_BREAKPOINT = 3
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};
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/* State modes. */
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enum STATE_MODES {
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/* The device is stopped */
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STOPPED = 0,
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/* The device is running or is being single stepped */
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RUNNING = 1,
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/* The device is stopped after the single step operation is
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* complete */
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SINGLE_STEP_COMPLETE = 2,
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/* The device is stopped as a result of hitting an enabled
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* breakpoint */
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BREAKPOINT_HIT = 3,
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/* The device is in LPMx.5 low power mode */
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LPMX5_MODE = 4,
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/* The device woke up from LPMx.5 low power mode */
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LPMX5_WAKEUP = 5
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};
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/* Configurations to set with MSP430_Configure. */
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enum CONFIG_MODE {
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/* Verify data downloaded to FLASH memories */
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VERIFICATION_MODE = 0,
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/* 4xx emulation mode */
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EMULATION_MODE = 1,
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/* Clock control mode (on emulation stop) */
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CLK_CNTRL_MODE = 2,
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/* Module Clock control mode (on emulation stop) */
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MCLK_CNTRL_MODE = 3,
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/* Flash test mode for Automotive Devices - Marginal Read */
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FLASH_TEST_MODE = 4,
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/* Allows Locked Info Mem Segment A access (if set to '1') */
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LOCKED_FLASH_ACCESS = 5,
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/* Flash Swop mode for Automotive Devices */
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FLASH_SWOP = 6,
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/* Trace mode in EDT file format */
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EDT_TRACE_MODE = 7,
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/* Configure interface protocol: JTAG or Spy-bi-Wire
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* (see enum INTERFACE_TYPE) */
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INTERFACE_MODE = 8,
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/* Configure a value that will be placed on the devices'
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* MemoryDataBus right before the device gets released from JTAG.
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* Useful fro supporting Emulated Hardware Breakpoints.
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*/
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SET_MDB_BEFORE_RUN = 9,
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/*
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* Configure whether RAM content should be preserved/restored
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* in MSP430_Erase() and MSP430_Memory() or not.
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* RAM_PRESERVE_MODE is set to ENABLE by default.
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* Usage Example for initial flash programming:
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* (1) MSP430_Configure(RAM_PRESERVE_MODE, DISABLE);
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* (2) MSP430_Erase(ERASE_ALL,..,..);
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* (3) MSP430_Memory(..., ..., ..., WRITE );
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* (4) MSP430_Memory(..., ..., ..., READ );
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* ..... Flash Programming/Download finished
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* (n) MSP430_Configure(RAM_PRESERVE_MODE, ENABLE);
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*/
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RAM_PRESERVE_MODE = 10,
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/* Configure the DLL to allow read/write/erase access to the 5xx
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* Bootstrap Loader (BSL) memory segments. */
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UNLOCK_BSL_MODE =11,
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/* just used internal for the device code of L092 and C092 */
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DEVICE_CODE = 12,
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/* set true to write the external SPI image of the L092 */
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WRITE_EXTERNAL_MEMORY = 13,
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/* set DEBUG_LPM_X true to start debugging of LPMx.5 */
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DEBUG_LPM_X = 14
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};
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typedef void (*DLL430_EVENTNOTIFY_FUNC)
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(unsigned int MsgId, unsigned int wParam, long lParam, long clientHandle);
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typedef struct MESSAGE_ID {
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ULONG uiMsgIdSingleStep;
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ULONG uiMsgIdBreakpoint;
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ULONG uiMsgIdStorage;
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ULONG uiMsgIdState;
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ULONG uiMsgIdWarning;
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ULONG uiMsgIdCPUStopped;
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} MessageID_t;
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typedef enum BpMode {
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BP_CLEAR = 0,
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BP_CODE = 1,
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BP_RANGE = 2,
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BP_COMPLEX = 3
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} BpMode_t;
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typedef enum BpType {
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BP_MAB = 0,
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BP_MDB = 1,
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BP_REGISTER = 2
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} BpType_t;
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typedef enum BpAccess {
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BP_FETCH = 0,
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BP_FETCH_HOLD = 1,
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BP_NO_FETCH = 2,
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BP_DONT_CARE = 3,
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BP_NO_FETCH_READ = 4,
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BP_NO_FETCH_WRITE = 5,
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BP_READ = 6,
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BP_WRITE = 7,
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BP_NO_FETCH_NO_DMA = 8,
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BP_DMA = 9,
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BP_NO_DMA = 10,
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BP_WRITE_NO_DMA = 11,
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BP_NO_FETCH_READ_NO_DMA = 12,
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BP_READ_NO_DMA = 13,
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BP_READ_DMA = 14,
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BP_WRITE_DMA = 15
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} BpAccess_t;
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typedef enum BpOperat {
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BP_EQUAL = 0,
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BP_GREATER = 1,
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BP_LOWER = 2,
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BP_UNEQUAL = 3
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} BpOperat_t;
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typedef enum BpRangeAction {
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BP_INSIDE = 0,
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BP_OUTSIDE = 1
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} BpRangeAction_t;
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typedef enum BpCondition {
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BP_NO_COND = 0,
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BP_COND = 1
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} BpCondition_t;
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typedef enum BpAction {
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BP_NONE = 0,
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BP_BRK = 1,
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BP_STO = 2,
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BP_BRK_STO = 3
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} BpAction_t;
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typedef struct BREAKPOINT {
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/* Breakpoint modes */
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BpMode_t bpMode;
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/* Breakpoint address/value (ignored for clear breakpoint) */
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LONG lAddrVal;
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/* Breakpoint type (used for range and complex breakpoints) */
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BpType_t bpType;
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/* Breakpoint register (used for complex breakpoints with
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* register-write trigger) */
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LONG lReg;
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/* Breakpoint access (used only for range and complex
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* breakpoints) */
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BpAccess_t bpAccess;
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/* Breakpoint action (break/storage) (used for range and complex
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* breakpoints) */
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BpAction_t bpAction;
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/* Breakpoint operator (used for complex breakpoints) */
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BpOperat_t bpOperat;
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/* Breakpoint mask (used for complex breakpoints) */
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LONG lMask;
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/* Range breakpoint end address (used for range breakpoints) */
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LONG lRangeEndAdVa;
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/* Range breakpoint action (inside/outside) (used for range
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* breakpoints) */
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BpRangeAction_t bpRangeAction;
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/* Complex breakpoint: Condition available */
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BpCondition_t bpCondition;
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/* Complex breakpoint: MDB value (used for complex breakpoints) */
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ULONG lCondMdbVal;
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/* Complex breakpoint: Access (used for complex breakpoints) */
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BpAccess_t bpCondAccess;
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/* Complex breakpoint: Mask Value(used for complex breakpoints) */
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LONG lCondMask;
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/* Complex breakpoint: Operator (used for complex breakpoints) */
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BpOperat_t bpCondOperat;
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/* Combine breakpoint: Reference of a combination handle */
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WORD wExtCombine;
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} BpParameter_t;
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typedef void (*DLL430_FET_NOTIFY_FUNC) (unsigned int MsgId,
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unsigned long wParam,
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unsigned long lParam,
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long clientHandle);
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typedef enum UPDATE_STATUS_MESSAGES {
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/* Initializing Update Bootloader */
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BL_INIT = 0,
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/* Erasing mapped interrupt vectors */
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BL_ERASE_INT_VECTORS = 1,
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/* Erasing firmware memory section */
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BL_ERASE_FIRMWARE = 2,
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/* Program new firmware */
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BL_PROGRAM_FIRMWARE = 3,
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/* One data block of the new firmware was successfully programmed */
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BL_DATA_BLOCK_PROGRAMMED = 4,
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/* Exit Update Bootlader and reboot firmware */
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BL_EXIT = 5,
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/* Update was successfully finished */
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BL_UPDATE_DONE = 6,
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/* An error occured during firmware update */
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BL_UPDATE_ERROR = 7,
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/* An error occured during firmware update */
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BL_WAIT_FOR_TIMEOUT = 8
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} UPDATE_STATUS_MESSAGES_t;
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union DEVICE_T {
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/* this buffer holds the complete device information */
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/* and is overlayed by the following information structure */
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CHAR buffer[110];
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struct { /* actually 106 Bytes */
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/* The value 0xaa55. */
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WORD endian;
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/* Identification number. */
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WORD id;
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/* Identification string. */
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BYTE string[32];
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/* MAIN MEMORY (FLASH) starting address. */
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WORD mainStart;
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/* INFORMATION MEMORY (FLASH) starting address. */
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WORD infoStart;
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/* RAM ending address. */
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WORD ramEnd;
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/* Number of breakpoints. */
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WORD nBreakpoints;
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/* Emulation level. */
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WORD emulation;
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/* Clock control level. */
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WORD clockControl;
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/* LCD starting address. */
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WORD lcdStart;
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/* LCD ending address. */
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WORD lcdEnd;
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/* Vcc minimum during operation [mVolts]. */
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WORD vccMinOp;
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/* Vcc maximum during operation [mVolts]. */
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WORD vccMaxOp;
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/* Device has TEST/VPP. */
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WORD hasTestVpp;
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/* RAM starting address. */
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WORD ramStart;
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/* RAM2 starting address. */
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WORD ram2Start;
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/* RAM2 ending address. */
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WORD ram2End;
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/* INFO ending address. */
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WORD infoEnd;
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/* MAIN ending address. */
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ULONG mainEnd;
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/* BSL starting address. */
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WORD bslStart;
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/* BSL ending address. */
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WORD bslEnd;
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/* Number of CPU Register Trigger. */
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WORD nRegTrigger;
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/* Number of EEM Trigger Combinations. */
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WORD nCombinations;
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/* The MSP430 architecture (non-X, X or Xv2). */
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BYTE cpuArch;
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/* The JTAG ID - value returned on an instruction shift. */
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BYTE jtagId;
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/* The CoreIP ID. */
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WORD coreIpId;
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/* The Device-ID Pointer. */
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ULONG deviceIdPtr;
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/* The EEM Version Number. */
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WORD eemVersion;
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/* Breakpoint Modes */
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WORD nBreakpointsOptions;
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WORD nBreakpointsReadWrite;
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WORD nBreakpointsDma;
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/* Trigger Mask for Breakpoint */
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WORD TrigerMask;
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/* Register Trigger modes */
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WORD nRegTriggerOperations;
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/* MSP430 has Stage Storage */
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WORD nStateStorage ;
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/* Numbr of cycle counters of MSP430 */
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WORD nCycleCounter;
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/* Cycle couter modes */
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WORD nCycleCounterOperations;
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/* Msp430 has Sqeuncer */
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WORD nSequencer;
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/* Msp430 has FRAM Memroy */
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WORD HasFramMemroy;
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} __attribute__((packed));
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};
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#endif
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