635 lines
13 KiB
C
635 lines
13 KiB
C
/* MSPDebug - debugging tool for the eZ430
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* Copyright (C) 2009, 2010 Daniel Beer
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <stdio.h>
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#include <ctype.h>
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#include "device.h"
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#include "dis.h"
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#include "util.h"
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#include "stab.h"
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#define MEM_SIZE 65536
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static u_int8_t *memory;
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static u_int16_t sim_regs[DEVICE_NUM_REGS];
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#define MEM_GETB(offset) (memory[offset])
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#define MEM_SETB(offset, value) (memory[offset] = (value))
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#define MEM_GETW(offset) \
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(memory[offset] | (memory[(offset + 1) & 0xffff] << 8))
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#define MEM_SETW(offset, value) \
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do { \
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memory[offset] = (value) & 0xff; \
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memory[(offset + 1) & 0xffff] = (value) >> 8; \
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} while (0);
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#define MEM_IO_END 0x200
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/* PC at the start of the current instruction */
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static u_int16_t current_insn;
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static void io_prefix(const char *prefix, u_int16_t addr, int is_byte)
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{
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char name[64];
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u_int16_t pc = current_insn;
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if (!stab_nearest(pc, name, sizeof(name), &pc)) {
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printf("%s", name);
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if (pc)
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printf("+0x%x", pc);
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} else {
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printf("0x%04x", pc);
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}
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printf(": IO %s.%c: 0x%04x", prefix, is_byte ? 'B' : 'W', addr);
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if (!stab_nearest(addr, name, sizeof(name), &addr)) {
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printf(" (%s", name);
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if (addr)
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printf("+0x%x", addr);
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printf(")");
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}
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}
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static int fetch_io(u_int16_t addr, int is_byte, u_int32_t *data_ret)
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{
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io_prefix("READ", addr, is_byte);
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for (;;) {
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char text[128];
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int len;
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int data;
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printf("? ");
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fflush(stdout);
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if (!fgets(text, sizeof(text), stdin)) {
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printf("\nAborted IO request\n");
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return -1;
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}
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len = strlen(text);
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while (len && isspace(text[len - 1]))
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len--;
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text[len] = 0;
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if (!stab_parse(text, &data)) {
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if (data_ret)
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*data_ret = data;
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return 0;
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}
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}
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return 0;
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}
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static void store_io(u_int16_t addr, int is_byte, u_int16_t data)
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{
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io_prefix("WRITE", addr, is_byte);
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if (is_byte)
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printf(" => 0x%02x\n", data & 0xff);
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else
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printf(" => 0x%04x\n", data);
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}
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static int fetch_operand(int amode, int reg, int is_byte,
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u_int16_t *addr_ret, u_int32_t *data_ret)
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{
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u_int16_t addr = 0;
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u_int32_t mask = is_byte ? 0xff : 0xffff;
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switch (amode) {
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case MSP430_AMODE_REGISTER:
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if (reg == MSP430_REG_R3) {
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if (data_ret)
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*data_ret = 0;
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return 0;
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}
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if (data_ret)
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*data_ret = sim_regs[reg] & mask;
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return 0;
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case MSP430_AMODE_INDEXED:
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if (reg == MSP430_REG_R3) {
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if (data_ret)
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*data_ret = 1;
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return 0;
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}
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addr = MEM_GETW(sim_regs[MSP430_REG_PC]);
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sim_regs[MSP430_REG_PC] += 2;
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if (reg != MSP430_REG_SR)
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addr += sim_regs[reg];
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break;
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case MSP430_AMODE_INDIRECT:
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if (reg == MSP430_REG_SR) {
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if (data_ret)
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*data_ret = 4;
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return 0;
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}
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if (reg == MSP430_REG_R3) {
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if (data_ret)
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*data_ret = 2;
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return 0;
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}
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addr = sim_regs[reg];
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break;
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case MSP430_AMODE_INDIRECT_INC:
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if (reg == MSP430_REG_SR) {
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if (data_ret)
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*data_ret = 8;
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return 0;
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}
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if (reg == MSP430_REG_R3) {
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if (data_ret)
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*data_ret = mask;
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return 0;
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}
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addr = sim_regs[reg];
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sim_regs[reg] += 2;
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break;
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}
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if (addr_ret)
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*addr_ret = addr;
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if (data_ret) {
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if (addr < MEM_IO_END)
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return fetch_io(addr, is_byte, data_ret);
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*data_ret = MEM_GETW(addr) & mask;
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}
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return 0;
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}
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static void store_operand(int amode, int reg, int is_byte,
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u_int16_t addr, u_int16_t data)
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{
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if (amode == MSP430_AMODE_REGISTER)
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sim_regs[reg] = data;
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else if (addr < MEM_IO_END)
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store_io(addr, is_byte, data);
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else if (is_byte)
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MEM_SETB(addr, data);
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else
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MEM_SETW(addr, data);
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}
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#define ARITH_BITS (MSP430_SR_V | MSP430_SR_N | MSP430_SR_Z | MSP430_SR_C)
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static int step_double(u_int16_t ins)
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{
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u_int16_t opcode = ins & 0xf000;
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int sreg = (ins >> 8) & 0xf;
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int amode_dst = (ins >> 7) & 1;
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int is_byte = ins & 0x0040;
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int amode_src = (ins >> 4) & 0x3;
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int dreg = ins & 0x000f;
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u_int32_t src_data;
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u_int16_t dst_addr = 0;
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u_int32_t dst_data;
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u_int32_t res_data;
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u_int32_t msb = is_byte ? 0x80 : 0x8000;
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u_int32_t mask = is_byte ? 0xff : 0xffff;
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if (fetch_operand(amode_src, sreg, is_byte, NULL, &src_data) < 0)
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return -1;
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if (fetch_operand(amode_dst, dreg, is_byte, &dst_addr,
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opcode == MSP430_OP_MOV ? NULL : &dst_data) < 0)
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return -1;
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switch (opcode) {
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case MSP430_OP_MOV:
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res_data = src_data;
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break;
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case MSP430_OP_SUB:
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case MSP430_OP_SUBC:
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case MSP430_OP_CMP:
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src_data = ~src_data;
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case MSP430_OP_ADD:
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case MSP430_OP_ADDC:
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if (opcode == MSP430_OP_ADDC || opcode == MSP430_OP_SUBC)
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res_data = (sim_regs[MSP430_REG_SR] &
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MSP430_SR_C) ? 1 : 0;
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else if (opcode == MSP430_OP_SUB || opcode == MSP430_OP_CMP)
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res_data = 1;
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else
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res_data = 0;
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res_data += src_data;
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res_data += dst_data;
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sim_regs[MSP430_REG_SR] &= ~ARITH_BITS;
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if (!(res_data & mask))
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sim_regs[MSP430_REG_SR] |= MSP430_SR_Z;
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if (res_data & msb)
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sim_regs[MSP430_REG_SR] |= MSP430_SR_N;
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if (res_data & (msb << 1))
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sim_regs[MSP430_REG_SR] |= MSP430_SR_C;
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if (!((src_data ^ dst_data) & msb) &&
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(src_data ^ dst_data) & msb)
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sim_regs[MSP430_REG_SR] |= MSP430_SR_V;
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break;
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case MSP430_OP_DADD:
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res_data = src_data + dst_data;
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if (sim_regs[MSP430_REG_SR] & MSP430_SR_C)
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res_data++;
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sim_regs[MSP430_REG_SR] &= ~ARITH_BITS;
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if (!(res_data & mask))
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sim_regs[MSP430_REG_SR] |= MSP430_SR_Z;
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if (res_data == 1)
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sim_regs[MSP430_REG_SR] |= MSP430_SR_N;
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if ((is_byte && res_data > 99) ||
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(!is_byte && res_data > 9999))
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sim_regs[MSP430_REG_SR] |= MSP430_SR_C;
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break;
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case MSP430_OP_BIT:
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case MSP430_OP_AND:
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res_data = src_data & dst_data;
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sim_regs[MSP430_REG_SR] &= ~ARITH_BITS;
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sim_regs[MSP430_REG_SR] |=
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(res_data & mask) ? MSP430_SR_C : MSP430_SR_Z;
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if (res_data & msb)
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sim_regs[MSP430_REG_SR] |= MSP430_SR_N;
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break;
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case MSP430_OP_BIC:
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res_data = dst_data & ~src_data;
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break;
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case MSP430_OP_BIS:
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res_data = dst_data | src_data;
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break;
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case MSP430_OP_XOR:
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res_data = dst_data ^ src_data;
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sim_regs[MSP430_REG_SR] &= ~ARITH_BITS;
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sim_regs[MSP430_REG_SR] |=
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(res_data & mask) ? MSP430_SR_C : MSP430_SR_Z;
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if (res_data & msb)
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sim_regs[MSP430_REG_SR] |= MSP430_SR_N;
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if (src_data & dst_data & msb)
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sim_regs[MSP430_REG_SR] |= MSP430_SR_V;
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break;
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default:
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fprintf(stderr, "sim: invalid double-operand opcode: "
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"0x%04x (PC = 0x%04x)\n",
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opcode, current_insn);
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return -1;
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}
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if (opcode != MSP430_OP_CMP && opcode != MSP430_OP_BIT)
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store_operand(amode_dst, dreg, is_byte, dst_addr, res_data);
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return 0;
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}
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static int step_single(u_int16_t ins)
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{
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u_int16_t opcode = ins & 0xff80;
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int is_byte = ins & 0x0040;
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int amode = (ins >> 4) & 0x3;
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int reg = ins & 0x000f;
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u_int16_t msb = is_byte ? 0x80 : 0x8000;
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u_int32_t mask = is_byte ? 0xff : 0xffff;
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u_int16_t src_addr = 0;
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u_int32_t src_data;
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u_int32_t res_data;
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if (fetch_operand(amode, reg, is_byte, &src_addr, &src_data) < 0)
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return -1;
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switch (opcode) {
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case MSP430_OP_RRC:
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case MSP430_OP_RRA:
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res_data = (src_data >> 1) & ~msb;
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if (opcode == MSP430_OP_RRC) {
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if (sim_regs[MSP430_REG_SR] & MSP430_SR_C)
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res_data |= msb;
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} else {
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res_data |= src_data & msb;
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}
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sim_regs[MSP430_REG_SR] &= ~ARITH_BITS;
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if (!(res_data & mask))
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sim_regs[MSP430_REG_SR] |= MSP430_SR_Z;
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if (res_data & msb)
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sim_regs[MSP430_REG_SR] |= MSP430_SR_N;
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if (src_data & 1)
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sim_regs[MSP430_REG_SR] |= MSP430_SR_C;
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break;
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case MSP430_OP_SWPB:
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res_data = ((src_data & 0xff) << 8) | ((src_data >> 8) & 0xff);
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break;
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case MSP430_OP_SXT:
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res_data = src_data & 0xff;
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sim_regs[MSP430_REG_SR] &= ~ARITH_BITS;
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if (src_data & 0x80) {
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res_data |= 0xff00;
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sim_regs[MSP430_REG_SR] |= MSP430_SR_N;
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}
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sim_regs[MSP430_REG_SR] |=
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(res_data & mask) ? MSP430_SR_C : MSP430_SR_Z;
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break;
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case MSP430_OP_PUSH:
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sim_regs[MSP430_REG_SP] -= 2;
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MEM_SETW(sim_regs[MSP430_REG_SP], src_data);
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break;
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case MSP430_OP_CALL:
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sim_regs[MSP430_REG_SP] -= 2;
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MEM_SETW(sim_regs[MSP430_REG_SP], sim_regs[MSP430_REG_PC]);
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sim_regs[MSP430_REG_PC] = src_data;
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break;
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case MSP430_OP_RETI:
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sim_regs[MSP430_REG_SR] = MEM_GETW(sim_regs[MSP430_REG_SP]);
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sim_regs[MSP430_REG_SP] += 2;
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sim_regs[MSP430_REG_PC] = MEM_GETW(sim_regs[MSP430_REG_SP]);
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sim_regs[MSP430_REG_SP] += 2;
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break;
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default:
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fprintf(stderr, "sim: unknown single-operand opcode: 0x%04x "
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"(PC = 0x%04x)\n", opcode, current_insn);
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return -1;
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}
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if (opcode != MSP430_OP_PUSH && opcode != MSP430_OP_CALL &&
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opcode != MSP430_OP_RETI)
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store_operand(amode, reg, is_byte, src_addr, res_data);
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return 0;
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}
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static int step_jump(u_int16_t ins)
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{
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u_int16_t opcode = ins & 0xfc00;
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u_int16_t pc_offset = (ins & 0x03ff) << 1;
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u_int16_t sr = sim_regs[MSP430_REG_SR];
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if (pc_offset & 0x0400)
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pc_offset |= 0xff800;
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switch (opcode) {
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case MSP430_OP_JNZ:
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sr = !(sr & MSP430_SR_Z);
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break;
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case MSP430_OP_JZ:
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sr &= MSP430_SR_Z;
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break;
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case MSP430_OP_JNC:
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sr = !(sr & MSP430_SR_C);
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break;
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case MSP430_OP_JC:
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sr &= MSP430_SR_C;
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break;
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case MSP430_OP_JN:
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sr &= MSP430_SR_N;
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break;
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case MSP430_OP_JGE:
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sr = ((sr & MSP430_SR_N) ? 1 : 0) !=
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((sr & MSP430_SR_V) ? 1 : 0);
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break;
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case MSP430_OP_JL:
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sr = ((sr & MSP430_SR_N) ? 1 : 0) ==
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((sr & MSP430_SR_V) ? 1 : 0);
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break;
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case MSP430_OP_JMP:
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sr = 1;
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break;
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}
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if (sr)
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sim_regs[MSP430_REG_PC] += pc_offset;
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return 0;
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}
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static int step_cpu(void)
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{
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u_int16_t ins;
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int ret;
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/* Fetch the instruction */
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current_insn = sim_regs[MSP430_REG_PC];
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ins = MEM_GETW(current_insn);
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sim_regs[MSP430_REG_PC] += 2;
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/* Handle different instruction types */
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if ((ins & 0xf000) >= 0x4000)
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ret = step_double(ins);
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else if ((ins & 0xf000) >= 0x2000)
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ret = step_jump(ins);
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else
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ret = step_single(ins);
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/* If things went wrong, restart at the current instruction */
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if (ret < 0)
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sim_regs[MSP430_REG_PC] = current_insn;
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return ret;
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}
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/************************************************************************
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* Device interface
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*/
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static enum {
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RUN_HALTED = 0,
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RUN_FREE,
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RUN_TO_BREAKPOINT
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} run_mode;
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static u_int16_t run_breakpoint;
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static void sim_close(void)
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{
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if (memory) {
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free(memory);
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memory = NULL;
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}
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}
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static int sim_control(device_ctl_t action)
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{
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switch (action) {
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case DEVICE_CTL_RESET:
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memset(sim_regs, 0, sizeof(sim_regs));
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sim_regs[MSP430_REG_PC] = MEM_GETW(0xfffe);
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return 0;
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case DEVICE_CTL_ERASE:
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memset(memory, 0xff, MEM_SIZE);
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return 0;
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case DEVICE_CTL_HALT:
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run_mode = RUN_HALTED;
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return 0;
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case DEVICE_CTL_STEP:
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return step_cpu();
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case DEVICE_CTL_RUN_BP:
|
|
run_mode = RUN_TO_BREAKPOINT;
|
|
ctrlc_reset();
|
|
return 0;
|
|
|
|
case DEVICE_CTL_RUN:
|
|
run_mode = RUN_FREE;
|
|
ctrlc_reset();
|
|
return 0;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int run_burst(void)
|
|
{
|
|
int i = 1000000;
|
|
|
|
while (i--) {
|
|
if (run_mode == RUN_TO_BREAKPOINT &&
|
|
sim_regs[MSP430_REG_PC] == run_breakpoint) {
|
|
printf("Breakpoint reached\n");
|
|
run_mode = RUN_HALTED;
|
|
return 0;
|
|
}
|
|
|
|
if (sim_regs[MSP430_REG_SR] & MSP430_SR_CPUOFF) {
|
|
run_mode = RUN_HALTED;
|
|
printf("CPU disabled\n");
|
|
return 0;
|
|
}
|
|
|
|
if (step_cpu() < 0) {
|
|
run_mode = RUN_HALTED;
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
static device_status_t sim_wait(int blocking)
|
|
{
|
|
if (run_mode != RUN_HALTED) {
|
|
do {
|
|
int ret = run_burst();
|
|
|
|
if (ret < 0)
|
|
return DEVICE_STATUS_ERROR;
|
|
if (!ret)
|
|
return DEVICE_STATUS_HALTED;
|
|
|
|
if (ctrlc_check()) {
|
|
ctrlc_reset();
|
|
return DEVICE_STATUS_INTR;
|
|
}
|
|
} while (blocking);
|
|
|
|
return DEVICE_STATUS_RUNNING;
|
|
}
|
|
|
|
return DEVICE_STATUS_HALTED;
|
|
}
|
|
|
|
static int sim_breakpoint(u_int16_t addr)
|
|
{
|
|
run_breakpoint = addr;
|
|
return 0;
|
|
}
|
|
|
|
static int sim_getregs(u_int16_t *regs)
|
|
{
|
|
memcpy(regs, sim_regs, sizeof(sim_regs));
|
|
return 0;
|
|
}
|
|
|
|
static int sim_setregs(const u_int16_t *regs)
|
|
{
|
|
memcpy(sim_regs, regs, sizeof(sim_regs));
|
|
return 0;
|
|
}
|
|
|
|
static int sim_readmem(u_int16_t addr, u_int8_t *mem, int len)
|
|
{
|
|
if (addr + len > MEM_SIZE)
|
|
len = MEM_SIZE - addr;
|
|
|
|
memcpy(mem, memory + addr, len);
|
|
return 0;
|
|
}
|
|
|
|
static int sim_writemem(u_int16_t addr, const u_int8_t *mem, int len)
|
|
{
|
|
if (addr + len > MEM_SIZE)
|
|
len = MEM_SIZE - addr;
|
|
|
|
memcpy(memory + addr, mem, len);
|
|
return 0;
|
|
}
|
|
|
|
static const struct device sim_device = {
|
|
.close = sim_close,
|
|
.control = sim_control,
|
|
.wait = sim_wait,
|
|
.breakpoint = sim_breakpoint,
|
|
.getregs = sim_getregs,
|
|
.setregs = sim_setregs,
|
|
.readmem = sim_readmem,
|
|
.writemem = sim_writemem
|
|
};
|
|
|
|
const struct device *sim_open(void)
|
|
{
|
|
memory = malloc(MEM_SIZE);
|
|
if (!memory) {
|
|
perror("sim: can't allocate memory");
|
|
return NULL;
|
|
}
|
|
|
|
memset(memory, 0xff, MEM_SIZE);
|
|
printf("Simulation started, 0x%x bytes of RAM\n", MEM_SIZE);
|
|
return &sim_device;
|
|
}
|