957 lines
26 KiB
C
957 lines
26 KiB
C
/* MSPDebug - debugging tool for MSP430 MCUs
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* Copyright (C) 2009, 2010 Daniel Beer
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* Copyright (C) 2018 Tadashi G. Takaoka
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <string.h>
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#include "ctrlc.h"
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#include "simio.h"
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#include "stab.h"
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/* Module under test */
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#include "simio_timer.c"
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/*
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* Helper functions for testing timer simio.
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*/
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static char **setup_args(const char *text)
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{
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static char args_buf[80];
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static char *args;
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strncpy(args_buf, text, sizeof(args_buf));
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args = args_buf;
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return &args;
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}
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static int* setup_clocks(int mclk, int smclk, int aclk)
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{
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static int clocks[SIMIO_NUM_CLOCKS];
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clocks[SIMIO_MCLK] = mclk;
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clocks[SIMIO_SMCLK] = smclk;
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clocks[SIMIO_ACLK] = aclk;
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return clocks;
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}
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static struct simio_device *create_timer(const char *arg)
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{
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return simio_timer.create(setup_args(arg));
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}
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static int config_timer(struct simio_device *dev, const char *param,
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const char *arg)
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{
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return simio_timer.config(dev, param, setup_args(arg));
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}
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/* Register offset from base_addr */
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#define TxCTL 0x00
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#define TxR 0x10
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#define TxCCTL(index) (0x02 + (index) * 2)
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#define TxCCR(index) (0x12 + (index) * 2)
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#define TxIV_TxIFG(index) ((index) * 2)
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static uint16_t read_timer(struct simio_device *dev, int offset)
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{
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struct timer *tmr = (struct timer *)dev;
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uint16_t data;
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assert(simio_timer.read(dev, tmr->base_addr + offset, &data) == 0);
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return data;
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}
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static void write_timer(struct simio_device *dev, int offset, uint16_t data)
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{
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struct timer *tmr = (struct timer *)dev;
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assert(simio_timer.write(dev, tmr->base_addr + offset, data) == 0);
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}
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static uint16_t read_iv(struct simio_device *dev)
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{
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struct timer *tmr = (struct timer *)dev;
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uint16_t iv;
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assert(simio_timer.read(dev, tmr->iv_addr, &iv) == 0);
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return iv;
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}
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static void step_smclk(struct simio_device *dev, int smclk)
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{
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uint16_t status_register = 0;
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simio_timer.step(dev, status_register, setup_clocks(0, smclk, 0));
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}
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static void step_aclk(struct simio_device *dev, int aclk)
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{
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uint16_t status_register = 0;
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simio_timer.step(dev, status_register, setup_clocks(0, 0, aclk));
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}
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static bool check_noirq(struct simio_device *dev)
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{
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return simio_timer.check_interrupt(dev) < 0;
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}
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static bool check_irq0(struct simio_device *dev)
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{
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struct timer *tmr = (struct timer *)dev;
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return simio_timer.check_interrupt(dev) == tmr->irq0;
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}
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static int check_irq1(struct simio_device *dev)
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{
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struct timer *tmr = (struct timer *)dev;
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return simio_timer.check_interrupt(dev) == tmr->irq1;
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}
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static void ack_irq0(struct simio_device *dev)
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{
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struct timer *tmr = (struct timer *)dev;
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simio_timer.ack_interrupt(dev, tmr->irq0);
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}
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/*
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* Working variables for tests.
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*/
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static struct simio_device *dev;
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/*
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* Set up and tear down for each test.
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*/
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static void set_up()
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{
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setup_args("");
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setup_clocks(0, 0, 0);
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dev = NULL;
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}
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static void tear_down()
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{
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if (dev != NULL) {
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simio_timer.destroy(dev);
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dev = NULL;
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}
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}
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#define assert_not(e) assert(!(e))
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/*
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* Set up for globals.
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*/
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static void set_up_globals()
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{
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ctrlc_init();
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stab_init();
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}
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/*
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* Tests for timer simio.
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*/
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static void test_create_no_option()
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{
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dev = create_timer("");
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assert(dev != NULL);
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assert(dev->type != NULL);
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assert(strcmp(dev->type->name, "timer") == 0);
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// Check default values.
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struct timer *tmr = (struct timer *)dev;
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assert(tmr->size == 3);
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assert(tmr->timer_type == TIMER_TYPE_A);
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assert(tmr->base_addr == 0x0160);
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assert(tmr->iv_addr == 0x012e);
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assert(tmr->irq0 == 9);
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assert(tmr->irq1 == 8);
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}
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static void test_create_with_size_7()
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{
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dev = create_timer("7");
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// Timer can have 7 comparators/captures at most.
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struct timer *tmr = (struct timer *)dev;
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assert(tmr->size == 7);
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}
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static void test_create_with_size_2()
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{
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dev = create_timer("2");
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// Timer should have 2 comparators/captures at least.
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struct timer *tmr = (struct timer *)dev;
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assert(tmr->size == 2);
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}
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static void test_create_with_size_8()
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{
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dev = create_timer("8");
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// Timer can't have 8 or more comparators/captures.
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assert(dev == NULL);
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}
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static void test_create_with_size_1()
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{
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dev = create_timer("1");
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// Timer can't have 1 or no comparator/capture.
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assert(dev == NULL);
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}
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static void test_config_type_default()
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{
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dev = create_timer("");
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// Default timer type is A.
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struct timer *tmr = (struct timer *)dev;
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assert(tmr->timer_type == TIMER_TYPE_A);
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}
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static void test_config_type_A()
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{
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dev = create_timer("");
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// Timer can configured as type A.
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assert(config_timer(dev, "type", "A") == 0);
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struct timer *tmr = (struct timer *)dev;
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assert(tmr->timer_type == TIMER_TYPE_A);
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}
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static void test_config_type_B()
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{
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dev = create_timer("");
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// Timer can configured as type B.
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struct timer *tmr = (struct timer *)dev;
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assert(config_timer(dev, "type", "B") == 0);
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assert(tmr->timer_type == TIMER_TYPE_B);
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}
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static void test_config_type_bad()
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{
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dev = create_timer("");
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struct timer *tmr = (struct timer *)dev;
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// Timer can't configured other than A/B.
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assert(config_timer(dev, "type", "bad") != 0);
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}
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static void test_config_type_empty()
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{
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dev = create_timer("");
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struct timer *tmr = (struct timer *)dev;
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// Timer type can't be empty.
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assert(config_timer(dev, "type", "") != 0);
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}
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static void test_address_space()
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{
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dev = create_timer("7");
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struct timer *tmr = (struct timer *)dev;
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for (uint32_t a = 0; a < 0x10000; a += 2) {
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const address_t addr = (address_t)a;
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uint16_t data;
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// Timer has 16 word registers from its base address.
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if (addr >= tmr->base_addr && addr < tmr->base_addr + 0x20) {
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assert(simio_timer.read(dev, addr, &data) == 0);
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assert(simio_timer.write(dev, addr, data) == 0);
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}
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// Timer has 1 word register as vector register.
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else if (addr == tmr->iv_addr) {
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assert(simio_timer.read(dev, addr, &data) == 0);
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assert(simio_timer.write(dev, addr, data) == 0);
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}
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// Timer has no register other than above.
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else {
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assert(simio_timer.read(dev, addr, &data) != 0);
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assert(simio_timer.write(dev, addr, data) != 0);
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}
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}
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}
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static void test_timer_continuous()
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{
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dev = create_timer("");
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/* Continuous mode, SMCLK, clear */
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write_timer(dev, TxCTL, MC1 | TASSEL1 | TACLR);
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// When TxCCR[0]=0 in continuous mode, then counter stops.
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write_timer(dev, TxCCTL(0), 0);
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write_timer(dev, TxCCR(0), 0);
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assert(read_timer(dev, TxR) == 0);
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step_smclk(dev, 10);
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assert(read_timer(dev, TxR) == 10);
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step_aclk(dev, 10);
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assert(read_timer(dev, TxR) == 10);
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}
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static void test_timer_stop()
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{
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dev = create_timer("");
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/* Stop mode, SMCLK, clear */
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write_timer(dev, TxCTL, TASSEL1 | TACLR);
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// When TxCCR[0]>0 in stop mode, then counter stops.
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write_timer(dev, TxCCTL(0), 0);
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write_timer(dev, TxCCR(0), 100);
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assert(read_timer(dev, TxR) == 0);
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step_smclk(dev, 10);
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assert(read_timer(dev, TxR) == 0);
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}
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static void test_timer_up_stop()
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{
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dev = create_timer("");
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/* Up mode, SMCLK, clear */
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write_timer(dev, TxCTL, MC0 | TASSEL1 | TACLR);
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// When TxCCR[0]=0 in up mode, then counter stops.
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write_timer(dev, TxCCTL(0), 0);
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write_timer(dev, TxCCR(0), 0);
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assert(read_timer(dev, TxR) == 0);
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step_smclk(dev, 10);
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assert(read_timer(dev, TxR) == 0);
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}
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static void test_timer_updown_stop()
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{
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dev = create_timer("");
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/* Up/Down mode, SMCLK, clear */
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write_timer(dev, TxCTL, MC1 | MC0 | TASSEL1 | TACLR);
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// When TxCCR[0]=0 in up/down mode, then counter stops.
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write_timer(dev, TxCCTL(0), 0);
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write_timer(dev, TxCCR(0), 0);
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assert(read_timer(dev, TxR) == 0);
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step_smclk(dev, 10);
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assert(read_timer(dev, TxR) == 0);
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}
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static void test_timer_a_up()
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{
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dev = create_timer("");
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/* Up mode, SMCLK, enable interrupt, clear */
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write_timer(dev, TxCTL, MC0 | TASSEL1 | TACLR | TAIE);
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/* Enable compare interrupt */
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write_timer(dev, TxCCTL(0), CCIE);
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write_timer(dev, TxCCR(0), 10);
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step_smclk(dev, 10);
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assert(read_timer(dev, TxR) == 10);
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// Compare interrupt and TAIFG interrupt both will happen.
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step_smclk(dev, 1);
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assert(read_timer(dev, TxR) == 0);
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assert(read_timer(dev, TxCCTL(0)) & CCIFG);
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assert(read_timer(dev, TxCTL) & TAIFG);
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// Compare interrupt has priority.
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assert(check_irq0(dev));
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ack_irq0(dev);
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assert_not(read_timer(dev, TxCCTL(0)) & CCIFG);
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assert(read_timer(dev, TxCTL) & TAIFG);
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// Then TAIFG interrupt should happen.
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assert(check_irq1(dev));
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assert(read_iv(dev) == TAIV_TAIFG);
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assert_not(read_timer(dev, TxCTL) & TAIFG);
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assert(check_noirq(dev));
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}
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static void test_timer_a_up_change_period()
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{
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dev = create_timer("");
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/* Up mode, SMCLK, enable interrupt, clear */
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write_timer(dev, TxCTL, MC0 | TASSEL1 | TACLR | TAIE);
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write_timer(dev, TxCCTL(0), CCIE);
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write_timer(dev, TxCCR(0), 10);
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step_smclk(dev, 8);
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// Changing period to less than current count will roll down
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// counter to 0.
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assert(read_timer(dev, TxR) == 8);
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write_timer(dev, TxCCR(0), 5);
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assert(check_noirq(dev));
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// TAIFG interrupt should happen.
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step_smclk(dev, 1);
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assert(read_timer(dev, TxR) == 0);
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assert(check_irq1(dev));
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assert(read_timer(dev, TxCTL) & TAIFG);
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assert(read_iv(dev) == TAIV_TAIFG);
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assert(check_noirq(dev));
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assert_not(read_timer(dev, TxCTL) & TAIFG);
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step_smclk(dev, 4);
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assert(read_timer(dev, TxR) == 4);
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// Changing period to greater that current count will continue
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// counting to the new period.
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write_timer(dev, TxCCR(0), 8);
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step_smclk(dev, 4);
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assert(check_noirq(dev));
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assert(read_timer(dev, TxR) == 8);
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// Compare interrupt should happen at new period TAR=8
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step_smclk(dev, 1);
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assert(read_timer(dev, TxR) == 0);
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assert(check_irq0(dev));
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assert(read_timer(dev, TxCCTL(0)) & CCIFG);
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ack_irq0(dev);
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assert_not(read_timer(dev, TxCCTL(0)) & CCIFG);
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assert(read_timer(dev, TxCTL) & TAIFG);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TAIV_TAIFG);
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assert(check_noirq(dev));
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assert_not(read_timer(dev, TxCTL) & TAIFG);
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}
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static void test_timer_a_updown_change_period()
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{
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dev = create_timer("");
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/* Up/Down mode, SMCLK, enable interrupt, clear */
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write_timer(dev, TxCTL, MC1 | MC0 | TASSEL1 | TACLR | TAIE);
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write_timer(dev, TxCCTL(0), CCIE);
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write_timer(dev, TxCCR(0), 10);
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step_smclk(dev, 8);
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// While counting up, changing period to less than current
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// count will change the counting direction to down.
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assert(read_timer(dev, TxR) == 8);
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write_timer(dev, TxCCR(0), 5);
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assert(read_timer(dev, TxR) == 8);
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step_smclk(dev, 2);
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assert(read_timer(dev, TxR) == 6);
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assert(check_noirq(dev));
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// While counting down, Changing period to greater that
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// current count will continue counting to 0.
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write_timer(dev, TxCCR(0), 8);
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step_smclk(dev, 6);
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assert(check_irq1(dev));
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assert(read_iv(dev) == TAIV_TAIFG);
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assert(check_noirq(dev));
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assert(read_timer(dev, TxR) == 0);
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// Then count up to TACCR[0] and compare interrupt should happen.
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step_smclk(dev, 8);
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assert(check_noirq(dev));
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assert(read_timer(dev, TxR) == 8);
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step_smclk(dev, 1);
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assert(check_irq0(dev));
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assert(read_timer(dev, TxCCTL(0)) & CCIFG);
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ack_irq0(dev);
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assert(check_noirq(dev));
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assert(read_timer(dev, TxR) == 7);
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}
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static void test_timer_divider()
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{
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dev = create_timer("");
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/* Continuous mode, SMCLK/1, clear */
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write_timer(dev, TxCTL, MC1 | TASSEL1 | TACLR);
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assert(read_timer(dev, TxR) == 0);
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step_smclk(dev, 80);
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assert(read_timer(dev, TxR) == 80);
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step_aclk(dev, 100);
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assert(read_timer(dev, TxR) == 80);
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/* Continuous mode, SMCLK/2, clear */
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write_timer(dev, TxCTL, MC1 | TASSEL1 | ID0 | TACLR);
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assert(read_timer(dev, TxR) == 0);
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step_smclk(dev, 80);
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assert(read_timer(dev, TxR) == 40);
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step_aclk(dev, 100);
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assert(read_timer(dev, TxR) == 40);
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/* Continuous mode, SMCLK/4, clear */
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write_timer(dev, TxCTL, MC1 | TASSEL1 | ID1 | TACLR);
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assert(read_timer(dev, TxR) == 0);
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step_smclk(dev, 80);
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assert(read_timer(dev, TxR) == 20);
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step_aclk(dev, 100);
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assert(read_timer(dev, TxR) == 20);
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/* Continuous mode, SMCLK/2, clear */
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write_timer(dev, TxCTL, MC1 | TASSEL1 | ID1 | ID0 | TACLR);
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assert(read_timer(dev, TxR) == 0);
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step_smclk(dev, 80);
|
|
assert(read_timer(dev, TxR) == 10);
|
|
step_aclk(dev, 100);
|
|
assert(read_timer(dev, TxR) == 10);
|
|
|
|
/* Continuous mode, ACLK/1, clear */
|
|
write_timer(dev, TxCTL, MC1 | TASSEL0 | TACLR);
|
|
assert(read_timer(dev, TxR) == 0);
|
|
step_aclk(dev, 80);
|
|
assert(read_timer(dev, TxR) == 80);
|
|
step_smclk(dev, 100);
|
|
assert(read_timer(dev, TxR) == 80);
|
|
|
|
/* Continuous mode, ACLK/2, clear */
|
|
write_timer(dev, TxCTL, MC1 | TASSEL0 | ID0 | TACLR);
|
|
assert(read_timer(dev, TxR) == 0);
|
|
step_aclk(dev, 80);
|
|
assert(read_timer(dev, TxR) == 40);
|
|
step_smclk(dev, 100);
|
|
assert(read_timer(dev, TxR) == 40);
|
|
|
|
/* Continuous mode, ACLK/4, clear */
|
|
write_timer(dev, TxCTL, MC1 | TASSEL0 | ID1 | TACLR);
|
|
assert(read_timer(dev, TxR) == 0);
|
|
step_aclk(dev, 80);
|
|
assert(read_timer(dev, TxR) == 20);
|
|
step_smclk(dev, 100);
|
|
assert(read_timer(dev, TxR) == 20);
|
|
|
|
/* Continuous mode, ACLK/2, clear */
|
|
write_timer(dev, TxCTL, MC1 | TASSEL0 | ID1 | ID0 | TACLR);
|
|
assert(read_timer(dev, TxR) == 0);
|
|
step_aclk(dev, 80);
|
|
assert(read_timer(dev, TxR) == 10);
|
|
step_smclk(dev, 100);
|
|
assert(read_timer(dev, TxR) == 10);
|
|
}
|
|
|
|
static void test_timer_capture_by_software()
|
|
{
|
|
dev = create_timer("");
|
|
|
|
/* Continuous mode, ACLK, clear */
|
|
write_timer(dev, TxCTL, MC1 | TASSEL0 | TACLR);
|
|
|
|
/* Capture mode, input GND, both edge */
|
|
write_timer(dev, TxCCTL(0), CAP | CCIS1 | CM1 | CM0);
|
|
step_aclk(dev, 10);
|
|
// Rising edge.
|
|
write_timer(dev, TxCCTL(0), read_timer(dev, TxCCTL(0)) | CCIS0);
|
|
assert(read_timer(dev, TxCCTL(0)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(0)) & COV);
|
|
assert(read_timer(dev, TxCCTL(0)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(0)) == 10);
|
|
|
|
write_timer(dev, TxCCTL(0), read_timer(dev, TxCCTL(0)) & ~CCIFG);
|
|
step_aclk(dev, 10);
|
|
// Falling edge.
|
|
write_timer(dev, TxCCTL(0), read_timer(dev, TxCCTL(0)) & ~CCIS0);
|
|
assert_not(read_timer(dev, TxCCTL(0)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(0)) & COV);
|
|
assert(read_timer(dev, TxCCTL(0)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(0)) == 20);
|
|
|
|
// Keep CCIFG on and capture causes COV */
|
|
step_aclk(dev, 10);
|
|
// Rising edge.
|
|
write_timer(dev, TxCCTL(0), read_timer(dev, TxCCTL(0)) | CCIS0);
|
|
assert(read_timer(dev, TxCCTL(0)) & CCI);
|
|
assert(read_timer(dev, TxCCTL(0)) & COV);
|
|
assert(read_timer(dev, TxCCTL(0)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(0)) == 20);
|
|
|
|
/* Capture mode, input GND, rising edge */
|
|
write_timer(dev, TxCCTL(1), CAP | CCIS1 | CM0);
|
|
// Rising edge.
|
|
write_timer(dev, TxCCTL(1), read_timer(dev, TxCCTL(1)) | CCIS0);
|
|
assert(read_timer(dev, TxCCTL(1)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(1)) & COV);
|
|
assert(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(1)) == 30);
|
|
|
|
write_timer(dev, TxCCTL(1), read_timer(dev, TxCCTL(1)) & ~CCIFG);
|
|
step_aclk(dev, 10);
|
|
// Falling edge.
|
|
write_timer(dev, TxCCTL(1), read_timer(dev, TxCCTL(1)) & ~CCIS0);
|
|
assert_not(read_timer(dev, TxCCTL(1)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(1)) & COV);
|
|
assert_not(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(1)) == 30);
|
|
|
|
/* Capture mode, input GND, falling edge */
|
|
write_timer(dev, TxCCTL(2), CAP | CCIS1 | CM1);
|
|
// Rising edge.
|
|
write_timer(dev, TxCCTL(2), read_timer(dev, TxCCTL(2)) | CCIS0);
|
|
assert(read_timer(dev, TxCCTL(2)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(2)) & COV);
|
|
assert_not(read_timer(dev, TxCCTL(2)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(2)) == 0);
|
|
|
|
step_aclk(dev, 10);
|
|
// Falling edge.
|
|
write_timer(dev, TxCCTL(2), read_timer(dev, TxCCTL(2)) & ~CCIS0);
|
|
assert_not(read_timer(dev, TxCCTL(2)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(2)) & COV);
|
|
assert(read_timer(dev, TxCCTL(2)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(2)) == 50);
|
|
}
|
|
|
|
|
|
static void test_timer_capture_by_signal()
|
|
{
|
|
dev = create_timer("");
|
|
|
|
/* Continuous mode, ACLK, clear */
|
|
write_timer(dev, TxCTL, MC1 | TASSEL0 | TACLR);
|
|
|
|
/* Capture mode, input CCIxA, both edge */
|
|
write_timer(dev, TxCCTL(0), CAP | CM1 | CM0);
|
|
step_aclk(dev, 10);
|
|
// Rising edge.
|
|
config_timer(dev, "set", "0 1");
|
|
assert(read_timer(dev, TxCCTL(0)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(0)) & COV);
|
|
assert(read_timer(dev, TxCCTL(0)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(0)) == 10);
|
|
|
|
write_timer(dev, TxCCTL(0), read_timer(dev, TxCCTL(0)) & ~CCIFG);
|
|
step_aclk(dev, 10);
|
|
// Falling edge.
|
|
config_timer(dev, "set", "0 0");
|
|
assert_not(read_timer(dev, TxCCTL(0)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(0)) & COV);
|
|
assert(read_timer(dev, TxCCTL(0)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(0)) == 20);
|
|
|
|
// Keep CCIFG on and capture causes COV */
|
|
step_aclk(dev, 10);
|
|
// Rising edge.
|
|
config_timer(dev, "set", "0 1");
|
|
assert(read_timer(dev, TxCCTL(0)) & CCI);
|
|
assert(read_timer(dev, TxCCTL(0)) & COV);
|
|
assert(read_timer(dev, TxCCTL(0)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(0)) == 20);
|
|
|
|
/* Capture mode, input CCIxB, rising edge, enable interrupt */
|
|
write_timer(dev, TxCCTL(1), CAP | CCIS0 | CM0 | CCIE);
|
|
// Rising edge.
|
|
config_timer(dev, "set", "1 1");
|
|
assert(check_irq1(dev));
|
|
assert(read_timer(dev, TxCCTL(1)) & CCI);
|
|
assert(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert_not(read_timer(dev, TxCCTL(1)) & COV);
|
|
assert(read_iv(dev) == TxIV_TxIFG(1));
|
|
assert(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(1)) == 30);
|
|
|
|
write_timer(dev, TxCCTL(1), read_timer(dev, TxCCTL(1)) & ~CCIFG);
|
|
step_aclk(dev, 10);
|
|
// Falling edge.
|
|
config_timer(dev, "set", "1 0");
|
|
assert(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(1)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(1)) & COV);
|
|
assert_not(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(1)) == 30);
|
|
|
|
/* Capture mode, input CCIxB falling edge, enable interrupt */
|
|
write_timer(dev, TxCCTL(2), CAP | CCIS0 | CM1 | CCIE);
|
|
// Rising edge.
|
|
config_timer(dev, "set", "2 1");
|
|
assert(check_noirq(dev));
|
|
assert(read_timer(dev, TxCCTL(2)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(2)) & COV);
|
|
assert_not(read_timer(dev, TxCCTL(2)) & CCIFG);
|
|
assert(read_timer(dev, TxCCR(2)) == 0);
|
|
|
|
step_aclk(dev, 10);
|
|
// Falling edge.
|
|
config_timer(dev, "set", "2 0");
|
|
assert(check_irq1(dev));
|
|
assert_not(read_timer(dev, TxCCTL(2)) & CCI);
|
|
assert_not(read_timer(dev, TxCCTL(2)) & COV);
|
|
assert(read_timer(dev, TxCCTL(2)) & CCIFG);
|
|
assert(read_iv(dev) == TxIV_TxIFG(2));
|
|
assert(check_noirq(dev));
|
|
assert(read_timer(dev, TxCCR(2)) == 50);
|
|
}
|
|
|
|
static void test_timer_a_compare()
|
|
{
|
|
dev = create_timer("");
|
|
|
|
/* Continuous mode, ACLK, interrupt enable, clear */
|
|
write_timer(dev, TxCTL, MC1 | TASSEL0 | TACLR | TAIE);
|
|
write_timer(dev, TxR, 0xffff);
|
|
/* Compare mode, enable interrupts */
|
|
write_timer(dev, TxCCTL(0), CCIE);
|
|
write_timer(dev, TxCCR(0), 200);
|
|
write_timer(dev, TxCCTL(1), CCIE);
|
|
write_timer(dev, TxCCR(1), 100);
|
|
write_timer(dev, TxCCTL(2), CCIE);
|
|
write_timer(dev, TxCCR(2), 200);
|
|
|
|
// Timer_A overflow interrupt should happen.
|
|
step_aclk(dev, 1);
|
|
assert(check_irq1(dev));
|
|
// Timer_A overflow vector is 0x0a.
|
|
assert(TAIV_TAIFG == 0x0a);
|
|
assert(read_iv(dev) == TAIV_TAIFG);
|
|
assert(check_noirq(dev));
|
|
assert(read_timer(dev, TxR) == 0);
|
|
|
|
step_aclk(dev, 100);
|
|
assert(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(1)) & SCCI);
|
|
// Set CCI of CCTL[1] to 1.
|
|
config_timer(dev, "set", "1 1");
|
|
// Timer_A comparator interrupt should happen.
|
|
step_aclk(dev, 1);
|
|
assert(check_irq1(dev));
|
|
assert(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert(read_iv(dev) == TxIV_TxIFG(1));
|
|
assert(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert(read_timer(dev, TxCCTL(1)) & SCCI);
|
|
|
|
// Timer_A comparator interrupts should happen.
|
|
step_aclk(dev, 100);
|
|
assert(check_irq0(dev));
|
|
assert(read_timer(dev, TxCCTL(0)) & CCIFG);
|
|
ack_irq0(dev);
|
|
assert_not(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(0)) & CCIFG);
|
|
// Lower priority interrupt.
|
|
assert(check_irq1(dev));
|
|
assert(read_timer(dev, TxCCTL(2)) & CCIFG);
|
|
assert(read_iv(dev) == TxIV_TxIFG(2));
|
|
assert(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(2)) & CCIFG);
|
|
|
|
// Set CCI of CCTL[1] to 0.
|
|
config_timer(dev, "set", "1 0");
|
|
write_timer(dev, TxCCR(1), 300);
|
|
step_aclk(dev, 100);
|
|
// Timer_A comparator interrupt should happen.
|
|
assert(check_irq1(dev));
|
|
assert(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert(read_iv(dev) == TxIV_TxIFG(1));
|
|
assert(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert_not(read_timer(dev, TxCCTL(1)) & SCCI);
|
|
}
|
|
|
|
static void test_timer_b_compare()
|
|
{
|
|
dev = create_timer("");
|
|
config_timer(dev, "type", "B");
|
|
|
|
/* Continuous mode, ACLK, interrupt enable, clear */
|
|
write_timer(dev, TxCTL, MC1 | TASSEL0 | TACLR | TAIE);
|
|
write_timer(dev, TxR, 0xffff);
|
|
/* Compare mode, enable interrupts */
|
|
write_timer(dev, TxCCTL(0), CCIE);
|
|
write_timer(dev, TxCCR(0), 200);
|
|
write_timer(dev, TxCCTL(1), CCIE);
|
|
write_timer(dev, TxCCR(1), 100);
|
|
write_timer(dev, TxCCTL(2), CCIE);
|
|
write_timer(dev, TxCCR(2), 200);
|
|
|
|
// Timer_B overflow interrupt should happen.
|
|
step_aclk(dev, 1);
|
|
assert(check_irq1(dev));
|
|
// Timer_B overflow vector is 0x0e.
|
|
assert(TBIV_TBIFG == 0x0e);
|
|
assert(read_iv(dev) == TBIV_TBIFG);
|
|
assert(check_noirq(dev));
|
|
assert(read_timer(dev, TxR) == 0);
|
|
|
|
step_aclk(dev, 100);
|
|
assert(check_noirq(dev));
|
|
// Set CCI of CCTL[1] to 1.
|
|
config_timer(dev, "set", "1 1");
|
|
// Timer_B comparator interrupt should happen.
|
|
step_aclk(dev, 1);
|
|
assert(check_irq1(dev));
|
|
assert(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert(read_iv(dev) == TxIV_TxIFG(1));
|
|
assert(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
|
|
// Timer_B comparator interrupts should happen.
|
|
step_aclk(dev, 100);
|
|
assert(check_irq0(dev));
|
|
assert(read_timer(dev, TxCCTL(0)) & CCIFG);
|
|
ack_irq0(dev);
|
|
assert_not(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(0)) & CCIFG);
|
|
// Lower priority interrupt.
|
|
assert(check_irq1(dev));
|
|
assert(read_timer(dev, TxCCTL(2)) & CCIFG);
|
|
assert(read_iv(dev) == TxIV_TxIFG(2));
|
|
assert(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(2)) & CCIFG);
|
|
|
|
// Set CCI of CCTL[1] to 0.
|
|
config_timer(dev, "set", "1 0");
|
|
write_timer(dev, TxCCR(1), 300);
|
|
step_aclk(dev, 100);
|
|
// Timer_B comparator interrupt should happen.
|
|
assert(check_irq1(dev));
|
|
assert(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
assert(read_iv(dev) == TxIV_TxIFG(1));
|
|
assert(check_noirq(dev));
|
|
assert_not(read_timer(dev, TxCCTL(1)) & CCIFG);
|
|
}
|
|
|
|
static void test_timer_capture()
|
|
{
|
|
dev = create_timer("");
|
|
|
|
/* Continuous mode, ACLK, clear */
|
|
write_timer(dev, TxCTL, MC1 | TASSEL0 | TACLR);
|
|
/* Capture mode, enable interrupts */
|
|
}
|
|
|
|
static void test_timer_b_length_8()
|
|
{
|
|
dev = create_timer("");
|
|
config_timer(dev, "type", "B");
|
|
|
|
/* Continuous 8 bit, SMCLK, interrupt enable, clear */
|
|
write_timer(dev, TxCTL, MC1 | CNTL1 | CNTL0 | TACLR | TAIE | TASSEL1);
|
|
write_timer(dev, TxR, 0x00ff);
|
|
step_smclk(dev, 2);
|
|
|
|
// Timer B can configured as 8 bit length.
|
|
assert(check_irq1(dev));
|
|
assert(read_iv(dev) == TBIV_TBIFG);
|
|
assert(read_timer(dev, TxR) == 1);
|
|
}
|
|
|
|
static void test_timer_b_length_10()
|
|
{
|
|
dev = create_timer("");
|
|
config_timer(dev, "type", "B");
|
|
|
|
/* Continuous 10 bit, ACLK, interrupt enable, clear */
|
|
write_timer(dev, TxCTL, MC1 | CNTL1 | TACLR | TAIE | TASSEL0);
|
|
write_timer(dev, TxR, 0x03ff);
|
|
step_aclk(dev, 3);
|
|
|
|
// Timer B can configured as 10 bit length.
|
|
assert(check_irq1(dev));
|
|
assert(read_iv(dev) == TBIV_TBIFG);
|
|
assert(read_timer(dev, TxR) == 2);
|
|
}
|
|
|
|
static void test_timer_b_length_12()
|
|
{
|
|
dev = create_timer("");
|
|
config_timer(dev, "type", "B");
|
|
|
|
/* Continuous 12 bit, SMCLK, interrupt enable, clear */
|
|
write_timer(dev, TxCTL, MC1 | CNTL0 | TACLR | TAIE | TASSEL1);
|
|
write_timer(dev, TxR, 0x0fff);
|
|
step_smclk(dev, 4);
|
|
|
|
// Timer B can configured as 12 bit length.
|
|
assert(check_irq1(dev));
|
|
assert(read_iv(dev) == TBIV_TBIFG);
|
|
assert(read_timer(dev, TxR) == 3);
|
|
}
|
|
|
|
static void test_timer_b_length_16()
|
|
{
|
|
dev = create_timer("");
|
|
config_timer(dev, "type", "B");
|
|
|
|
/* Continuous 16 bit, SMCLK, interrupt enable, clear */
|
|
write_timer(dev, TxCTL, MC1 | TACLR | TAIE | TASSEL1);
|
|
write_timer(dev, TxR, 0xffff);
|
|
step_smclk(dev, 5);
|
|
|
|
// Timer B can configured as 16 bit length.
|
|
assert(check_irq1(dev));
|
|
assert(read_iv(dev) == TBIV_TBIFG);
|
|
assert(read_timer(dev, TxR) == 4);
|
|
}
|
|
|
|
|
|
/*
|
|
* Test runner.
|
|
*/
|
|
|
|
static void run_test(void (*test)(), const char *test_name)
|
|
{
|
|
set_up();
|
|
|
|
test();
|
|
printf(" PASS %s\n", test_name);
|
|
|
|
tear_down();
|
|
}
|
|
|
|
#define RUN_TEST(test) run_test(test, #test)
|
|
|
|
int main(int argc, char **argv)
|
|
{
|
|
set_up_globals();
|
|
|
|
RUN_TEST(test_create_no_option);
|
|
RUN_TEST(test_create_with_size_7);
|
|
RUN_TEST(test_create_with_size_2);
|
|
RUN_TEST(test_create_with_size_8);
|
|
RUN_TEST(test_create_with_size_1);
|
|
RUN_TEST(test_config_type_default);
|
|
RUN_TEST(test_config_type_A);
|
|
RUN_TEST(test_config_type_B);
|
|
RUN_TEST(test_config_type_bad);
|
|
RUN_TEST(test_config_type_empty);
|
|
RUN_TEST(test_address_space);
|
|
RUN_TEST(test_timer_continuous);
|
|
RUN_TEST(test_timer_stop);
|
|
RUN_TEST(test_timer_up_stop);
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RUN_TEST(test_timer_updown_stop);
|
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RUN_TEST(test_timer_a_up);
|
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RUN_TEST(test_timer_a_up_change_period);
|
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RUN_TEST(test_timer_a_updown_change_period);
|
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RUN_TEST(test_timer_divider);
|
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RUN_TEST(test_timer_capture_by_software);
|
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RUN_TEST(test_timer_capture_by_signal);
|
|
RUN_TEST(test_timer_a_compare);
|
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RUN_TEST(test_timer_b_compare);
|
|
RUN_TEST(test_timer_b_length_8);
|
|
RUN_TEST(test_timer_b_length_10);
|
|
RUN_TEST(test_timer_b_length_12);
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RUN_TEST(test_timer_b_length_16);
|
|
}
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