we can read from memory now!
This commit is contained in:
parent
377733b191
commit
f0ba450435
36
src/main.c
36
src/main.c
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@ -49,12 +49,36 @@ int main() {
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sbw_tclk_burst(16);
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printf("done.\n");*/
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// sbw_tap_reset();
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// sbw_check_fuse();
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//
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// uint8_t id = sbw_tap_shift_ir(0xff/*IR_BYPASS*/);
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//
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// printf("JTAG ID=%02x\n", id);
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/*sbw_tap_reset();
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sbw_check_fuse();
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uint8_t id = sbw_tap_shift_ir(msp430_ir_bypass);
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printf("JTAG ID=%02x\n", id);
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit);
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uint16_t dr = sbw_tap_read_dr();
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printf("dr.0 = %04x\n", dr);
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sbw_clr_tclk(); // FIXME: looks very bad
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sbw_set_tclk(); // FIXME: looks very bad
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dr = sbw_tap_read_dr();
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printf("dr.1 = %04x\n", dr);
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sbw_clr_tclk(); // FIXME: looks very bad
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sbw_set_tclk(); // FIXME: looks very bad
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dr = sbw_tap_read_dr();
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printf("dr.2 = %04x\n", dr);
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sbw_clr_tclk(); // FIXME: looks very bad
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sbw_set_tclk(); // FIXME: looks very bad
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sbw_tap_shift_ir(msp430_ir_data_16bit);
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dr = sbw_tap_shift_dr(0x3fff); // "jmp ."
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printf("dr.10 = %04x\n", dr);
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sbw_clr_tclk(); // looks ok here?
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit); // FIXME: a
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dr = sbw_tap_shift_dr(0x2409); // JTAG halt // FIXME: a
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printf("dr.11 = %04x\n", dr);
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sbw_set_tclk(); // looks ok here?
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printf("test done\n");*/
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uint32_t initv = msp430_device_get(200e3);
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printf("init -> %08lx\n", initv);
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@ -0,0 +1,186 @@
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#include <stddef.h>
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#include <stdio.h>
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#include "pio_sbw.h"
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#include "tap.h"
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#include "msp430dbg.h"
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bool msp430_check_fuse_blown(void) {
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for (size_t i = 0; i < 3; ++i) {
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_capture);
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uint16_t dr = sbw_tap_shift_dr(0xaaaa);
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//printf("fuse dr=%04x\n", dr);
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if (dr == 0x5555) return true;
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}
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return false;
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}
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bool msp430_insn_fetch(void) {
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_capture);
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// shouldn't it set the insn fetch bit here?
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for (size_t i = 0; i < 50; ++i) {
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uint16_t dr = sbw_tap_read_dr();
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//printf("[%zu] wait fetch dr=%04x\n", i, dr);
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if (dr & 0x0080) return true;
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sbw_clr_tclk();
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sbw_set_tclk();
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}
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return false;
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}
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void msp430_cpu_halt(void) {
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if (!msp430_insn_fetch()) ;//printf("aaa no fetch\n");
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sbw_tap_shift_ir(msp430_ir_data_16bit);
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sbw_tap_shift_dr(0x3fff); // "jmp ."
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sbw_clr_tclk();
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit);
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sbw_tap_shift_dr(0x2409); // JTAG halt
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sbw_set_tclk();
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}
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void msp430_cpu_release(void) {
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sbw_clr_tclk();
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit);
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sbw_tap_shift_dr(0x2401);
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sbw_tap_shift_ir(msp430_ir_addr_capture);
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sbw_set_tclk();
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}
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bool msp430_cpu_reset(void) {
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit);
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sbw_tap_shift_dr(0x2C01);
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sbw_tap_shift_dr(0x2401);
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sbw_clr_tclk();
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sbw_set_tclk();
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sbw_clr_tclk();
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sbw_set_tclk();
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sbw_clr_tclk();
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uint8_t jtagid = sbw_tap_shift_ir(msp430_ir_addr_capture);
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sbw_set_tclk();
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//printf("reset: watchdog disable\n");
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msp430_memory_write(16, 0x0120, 0x5A80); // disable watchdog
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return jtagid == MSP430_JTAG_TAP_ID;
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}
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uint16_t msp430_memory_read16(uint16_t addr) {
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msp430_cpu_halt();
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sbw_clr_tclk();
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit);
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sbw_tap_shift_dr(0x2409); // 2419 for 8bit
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sbw_tap_shift_ir(msp430_ir_addr_16bit);
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sbw_tap_shift_dr(addr);
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sbw_tap_shift_ir(msp430_ir_data_to_addr);
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sbw_set_tclk();
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sbw_clr_tclk();
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uint16_t r = sbw_tap_read_dr();
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//printf("read16 result=%04x\n", r);
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msp430_cpu_release();
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return r;
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}
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uint8_t msp430_memory_read8 (uint16_t addr) {
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msp430_cpu_halt();
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sbw_clr_tclk();
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit);
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sbw_tap_shift_dr(0x2419); // 2409 for 16bit
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sbw_tap_shift_ir(msp430_ir_addr_16bit);
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sbw_tap_shift_dr(addr);
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sbw_tap_shift_ir(msp430_ir_data_to_addr);
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sbw_set_tclk();
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sbw_clr_tclk();
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uint16_t r = sbw_tap_read_dr();
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msp430_cpu_release();
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return r;
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}
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void msp430_memory_write16(uint16_t addr, uint16_t value) {
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msp430_cpu_halt();
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sbw_clr_tclk();
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit);
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sbw_tap_shift_dr(0x2408); // 2418 for 8bit
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sbw_tap_shift_ir(msp430_ir_addr_16bit);
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sbw_tap_shift_dr(addr);
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sbw_tap_shift_ir(msp430_ir_data_to_addr);
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sbw_tap_shift_dr(value);
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sbw_set_tclk();
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msp430_cpu_release();
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}
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void msp430_memory_write8 (uint16_t addr, uint8_t value) {
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msp430_cpu_halt();
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sbw_clr_tclk();
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit);
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sbw_tap_shift_dr(0x2418);
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sbw_tap_shift_ir(msp430_ir_addr_16bit);
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sbw_tap_shift_dr(addr);
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sbw_tap_shift_ir(msp430_ir_data_to_addr);
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sbw_tap_shift_dr(value);
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sbw_set_tclk();
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msp430_cpu_release();
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}
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uint32_t msp430_device_get(float freq) {
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uint8_t jtagid = 0;
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for (size_t i = 0; i < 7; ++i) {
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sbw_preinit();
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bool s = sbw_init();
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if (!s) return 0xff<<24;
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sbw_tap_reset();
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sbw_check_fuse();
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jtagid = sbw_tap_shift_ir(msp430_ir_bypass);
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//printf("[%zu] get jtag id= %02x\n", i, jtagid);
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if (jtagid == MSP430_JTAG_TAP_ID) break;
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sbw_deinit();
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}
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if (jtagid != MSP430_JTAG_TAP_ID) return 0<<24;
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if (msp430_check_fuse_blown()) return 1<<24;
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// TODO: set frequency here
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sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit);
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uint16_t dr = sbw_tap_shift_dr(0x2401); // JTAG mode, read
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//printf("olddr=%04x\n", dr);
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if (sbw_tap_shift_ir(msp430_ir_ctrl_sig_16bit) != jtagid) {
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return 2<<24;
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}
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uint16_t devid = 0;
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for (size_t i = 0; i < 50; ++i) {
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dr = sbw_tap_read_dr();
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//printf("[%zu] wait jtag sync: dr=%04x\n", i, dr);
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if (dr & 0x0200) {
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devid = msp430_memory_read(16, 0x0FF0);
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break;
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}
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}
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if (devid == 0) return 3<<24;
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if (!msp430_cpu_reset()) return 4<<24;
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return ((uint32_t)jtagid << 24) | devid;
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}
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@ -0,0 +1,73 @@
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#ifndef MSP430DBG_H_
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#define MSP430DBG_H_
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#include <stdint.h>
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#include <stdbool.h>
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#define MSP430_JTAG_TAP_ID 0x89
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enum msp430_ir {
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// lsb-first transfer
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// DR: msb-first transfer...
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msp430_ir_addr_16bit = 0x83,
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msp430_ir_addr_capture = 0x84,
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msp430_ir_data_to_addr = 0x85,
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msp430_ir_data_16bit = 0x41,
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msp430_ir_data_quick = 0x43,
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msp430_ir_ctrl_sig_16bit = 0x13,
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msp430_ir_ctrl_sig_capture = 0x14, // 0010 1000 <=> 0x28
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msp430_ir_ctrl_sig_release = 0x15,
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msp430_ir_data_psa = 0x44,
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msp430_ir_shift_out_psa = 0x46,
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msp430_ir_fuse_prepare_blow = 0x22,
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msp430_ir_fuse_ex_blow = 0x24,
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msp430_ir_jmb_exchange = 0x61,
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msp430_ir_bypass = 0xff
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};
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enum msp430_ctrl {
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msp430_ctrl_RnW = 1<< 0,
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msp430_ctrl_halt_jtag = 1<< 3,
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msp430_ctrl_instr_load = 1<< 7,
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msp430_ctrl_tce0 = 1<< 9,
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msp430_ctrl_tce1 = 1<<10,
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msp430_ctrl_por = 1<<11,
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msp430_release_lbyte0 = 1<<12,
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msp430_tagfuncsat = 1<<13,
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msp430_switch = 1<<14,
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};
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bool msp430_check_fuse_blown(void);
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void msp430_jtag_ctrl(void);
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bool msp430_insn_fetch(void);//
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void msp430_pc_set(uint16_t pc);
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void msp430_cpu_halt(void);
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void msp430_cpu_release(void);
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bool msp430_cpu_reset(void); // POR
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void msp430_device_release(void);
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uint16_t msp430_memory_read16(uint16_t addr);
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uint8_t msp430_memory_read8 (uint16_t addr);
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void msp430_memory_write16(uint16_t addr, uint16_t value);
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void msp430_memory_write8 (uint16_t addr, uint8_t value);
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void msp430_memory_read_block(uint16_t srcaddr, uint16_t num, uint16_t* dest);
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void msp430_memory_write_block(uint16_t dstaddr, uint16_t num, const uint16_t* src);
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#define msp430_memory_read(bits, addr) (msp430_memory_read##bits (addr))
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#define msp430_memory_write(bit, a, v) (msp430_memory_write##bit (a, v))
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void msp430_flash_write(uint16_t startaddr, uint16_t num, const uint16_t* src);
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void msp430_flash_erase_seg(uint16_t startaddr, bool is_infosegA);
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void msp430_flash_erase_mass(bool withinfomem); // false: only main flash
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bool msp430_flash_verify(uint16_t startaddr, uint16_t length, const uint16_t* copy);
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uint32_t msp430_device_get(float freq);
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#endif
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@ -1,4 +1,6 @@
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#include <stdio.h>
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#include <hardware/clocks.h>
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#include <hardware/dma.h>
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#include <hardware/gpio.h>
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@ -67,7 +69,7 @@ void sbw_preinit(void) {
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int sbw_piosm = -1, sbw_offset = -1;
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static uint last_tclk = 1;
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static bool last_tclk = true;
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static uint8_t last_tdi = 0xff, last_tms = 0xff;
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bool sbw_init(void) {
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@ -92,7 +94,7 @@ bool sbw_init(void) {
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PINOUT_SBW_TCK, PINOUT_SBW_TDIO);
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last_tdi = last_tms = 0xff;
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last_tclk = 1;
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last_tclk = true;
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return true;
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}
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@ -180,7 +182,7 @@ void sbw_sequence(uint32_t ncyc, bool tms, const uint8_t* tdi, uint8_t* tdo) {
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}
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}
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while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm)) tight_loop_contents();
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//while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();
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if (tdi) last_tdi = (tdi[nbytes - 1] & (1 << (ncyc & 7))) ? 0xff : 0;
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last_tms = tms ? 0xff : 0;
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@ -214,18 +216,18 @@ void sbw_tms_sequence(uint32_t ncyc, bool tdi, const uint8_t* tms) {
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}
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}
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while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm)) tight_loop_contents();
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//while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();
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last_tdi = tdi ? 0xff : 0;
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last_tms = (tms[nbytes - 1] & (1 << (ncyc & 7))) ? 0xff : 0;
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}
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void sbw_clrset_tclk(bool value) {
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sbw_pio_loadbearing_set_setpins(PINOUT_SBW_PIO, value ? 1 : 0); // new value
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//sbw_pio_loadbearing_set_setpins(PINOUT_SBW_PIO, value ? 1 : 0); // new value
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// pre-TCLK value
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piosm_txf_wait();
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piosm_txf(16) = sbw_pio_gen_sety(last_tclk);
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piosm_txf(16) = sbw_pio_gen_sety(last_tclk ? 1 : 0);
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// only one TCLK
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piosm_txf_wait();
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@ -235,14 +237,19 @@ void sbw_clrset_tclk(bool value) {
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piosm_txf_wait();
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piosm_txf(16) = sbw_pio_gen_jmp(sbw_offset_sbw_tclk_burst + sbw_offset);
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// wait until done
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while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm)) tight_loop_contents();
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// always use out pins, 1
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piosm_txf_wait();
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piosm_txf(8) = value ? 0xff : 0;
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last_tclk = value ? 1 : 0;
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// wait until done
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/*while ( sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();
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while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();*/
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last_tclk = value;
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}
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void sbw_tclk_burst(uint32_t ncyc) {
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sbw_pio_loadbearing_set_outpins(PINOUT_SBW_PIO);
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//sbw_pio_loadbearing_set_outpins(PINOUT_SBW_PIO);
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uint32_t txremain = ((ncyc + 7) >> 3) * 2;
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@ -251,7 +258,7 @@ void sbw_tclk_burst(uint32_t ncyc) {
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// pre-TCLK value
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piosm_txf_wait();
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piosm_txf(16) = sbw_pio_gen_sety(last_tclk);
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piosm_txf(16) = sbw_pio_gen_sety(last_tclk ? 1 : 0);
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// number of TCLK half-cycles in x
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piosm_txf_wait();
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@ -271,7 +278,8 @@ void sbw_tclk_burst(uint32_t ncyc) {
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}
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// wait until done
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while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm)) tight_loop_contents();
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/*while ( sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();
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while (!sbw_pio_is_idle(PINOUT_SBW_PIO, sbw_piosm, sbw_offset)) tight_loop_contents();*/
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// last_tclk doesn't change - always an even number of TCLK half-cycles
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}
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19
src/sbw.pio
19
src/sbw.pio
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@ -80,8 +80,8 @@ PUBLIC sbw_tms_seq:
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;
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; a full cycle takes 13 cycles, a single slot 4
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; the SM divider should be sysclk/(4*baudrate)
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; baudrate shouldn't exceed 20 MHz (typical value is 1.8 MHz?)
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; SBWTCK LOW phases shouldn't exceed 7us, so the baudrate should be at least 72 kHz
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; baudrate shouldn't exceed 20 MHz (typical value is 18 MHz?)
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; SBWTCK LOW phases shouldn't exceed 7us, so the baudrate should be at least 40 kHz
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; y: initial/previous TCLK value
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; x: number of TCLK *half*-cycles minus one!
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@ -99,7 +99,7 @@ PUBLIC sbw_tclk_burst:
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; tdi slot:
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nop side 1 [12] ; wait a bit
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burst_loop:
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PUBLIC sbw_tclk_burst_loadbearing_insn:
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;PUBLIC sbw_tclk_burst_loadbearing_insn:
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out pins, 1 side 1 [12] ; in the middle of TDI hiphase: do TCLK
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jmp x--, burst_loop side 1 [12]
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nop side 0 [1] ; need a low clock edge for TDO
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|
@ -186,7 +186,8 @@ static inline uint16_t sbw_pio_gen_outx(uint bits) {
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static inline uint16_t sbw_pio_gen_jmp(uint subroutine) {
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||||
return pio_encode_jmp(subroutine) | pio_encode_sideset(1, 1) | (1<<12);
|
||||
}
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static inline uint16_t sbw_pio_loadbearing_gen_outpins(void) {
|
||||
|
||||
/*static inline uint16_t sbw_pio_loadbearing_gen_outpins(void) {
|
||||
return pio_encode_out(pio_pins, 1) | pio_encode_sideset(1, 1) | pio_encode_delay(12) | (1<<12);
|
||||
}
|
||||
static inline uint16_t sbw_pio_loadbearing_gen_setpins(uint value) {
|
||||
|
|
@ -194,19 +195,17 @@ static inline uint16_t sbw_pio_loadbearing_gen_setpins(uint value) {
|
|||
}
|
||||
|
||||
static inline void sbw_pio_loadbearing_set_outpins(PIO pio) {
|
||||
// FIXME: writes 32 bits!!!
|
||||
pio->instr_mem[sbw_offset_sbw_tclk_burst_loadbearing_insn] =
|
||||
sbw_pio_loadbearing_gen_outpins();
|
||||
}
|
||||
static inline void sbw_pio_loadbearing_set_setpins(PIO pio, uint value) {
|
||||
// FIXME: writes 32 bits!!!
|
||||
pio->instr_mem[sbw_offset_sbw_tclk_burst_loadbearing_insn] =
|
||||
sbw_pio_loadbearing_gen_setpins(value);
|
||||
}
|
||||
}*/
|
||||
|
||||
static inline bool sbw_pio_is_idle(PIO pio, uint value) {
|
||||
return pio_sm_get_pc(pio, value) < sbw_offset_sbw_seq;
|
||||
}
|
||||
/*static inline bool sbw_pio_is_idle(PIO pio, uint sm, uint offset) {
|
||||
return pio_sm_get_pc(pio, sm) < sbw_offset_sbw_seq + offset;
|
||||
}*/
|
||||
|
||||
%}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue