fix a few bugs, make a very rudimentary assembler
This commit is contained in:
parent
008bbb95ab
commit
87d240ffa9
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@ -2,3 +2,5 @@
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*.html
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*.zip
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*.tar.gz
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orig-le.*
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reasm.*
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@ -41,7 +41,9 @@ instruction set (as of now):
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wait wait for interrupt???
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input abs, reg read from I/O space (absolute address)
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input (reg), reg read from I/O space (register indirect)
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output reg, abs write to I/O space
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output reg, (reg) write to I/O space
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outclr abs set I/O reg to 0?
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outset abs set I/O reg to 0xffff??
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outbclr imm, abs clear bit <imm> of I/O reg <abs>
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@ -93,7 +95,7 @@ instruction set encoding maybe:
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0110 1100 0000 dddd jmp (d=reg)
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^^^^ other ops?
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? 0110 1101 ssss dddd ?? input (s=srcreg), d=dst hypothetical
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0110 1110 ssss dddd output s=src, (d=dstreg)
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0110 1110 dddd ssss output s=src, (d=dstreg)
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0110 1111 ssss dddd lmd (s=srcreg), d=dst no store?
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0111 0000 0000 0000 rts
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@ -129,7 +129,7 @@ def decode(insn):
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elif typ == 1: # input
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return "input (%s), %s" % (REGS[src], REGS[dreg])
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elif typ == 2: # output
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return "output %s, (%s)" % (REGS[src], REGS[dreg])
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return "output %s, (%s)" % (REGS[dreg], REGS[src])
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elif typ == 3: # lmd
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return "lmd (%s), %s" % (REGS[src], REGS[dreg])
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else: assert False
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@ -0,0 +1,244 @@
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; vim: set ft=nasm:
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r0 equ 0
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r1 equ 1
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r2 equ 2
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r3 equ 3
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r4 equ 4
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r5 equ 5
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r6 equ 6
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r7 equ 7
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r8 equ 8
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r9 equ 9
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r10 equ 10
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r11 equ 11
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r12 equ 12
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r13 equ 13
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r14 equ 14
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r15 equ 15
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pc equ 16
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;;;;; alu ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro or 2
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%ifid %1
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dw 0x0000 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%else
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dw 0x0200 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%endif
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%endmacro
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%macro and 2
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%ifid %1
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dw 0x0400 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%else
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dw 0x0600 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%endif
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%endmacro
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%macro xor 2
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%ifid %1
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dw 0x0800 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%else
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dw 0x0a00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%endif
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%endmacro
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%macro tst 2
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%ifid %1
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dw 0x0c00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%else
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dw 0x0e00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%endif
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%endmacro
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%macro mov 2
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%ifid %1
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dw 0x1000 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%else
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dw 0x1200 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%endif
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%endmacro
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%macro add 2
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%ifid %1
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dw 0x1400 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%else
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dw 0x1600 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%endif
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%endmacro
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%macro sub 2
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%ifid %1
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dw 0x1800 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%else
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dw 0x1a00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%endif
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%endmacro
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%macro cmp 2
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%ifid %1
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dw 0x1c00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%else
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dw 0x1e00 | (((%2)&0xf) << 0) | (((%1)&0x1f) << 4)
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%endif
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%endmacro
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;;;;; bit ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro btst 2
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dw 0x2200 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4)
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%endmacro
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%macro bclr 2
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dw 0x2a00 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4)
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%endmacro
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;;;;; shift ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro sl0 2
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%ifid %1
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dw 0x3000 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4)
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%else
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dw 0x3100 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4)
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%endif
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%endmacro
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%macro sr0 2
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%ifid %1
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dw 0x3800 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4)
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%else
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dw 0x3900 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4)
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%endif
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%endmacro
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%macro srx 2
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%ifid %1
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dw 0x3c00 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4)
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%else
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dw 0x3d00 | (((%2)&0xf) << 0) | (((%1)&0xf) << 4)
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%endif
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%endmacro
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;;;;; branch ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro beq 1
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dw 0x4000 | ((((%1)&0x7ff)<<0)>>1)
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%endmacro
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%macro bne 1
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dw 0x4400 | ((((%1)&0x7ff)<<0)>>1)
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%endmacro
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%macro bmi 1
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dw 0x4800 | ((((%1)&0x7ff)<<0)>>1)
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%endmacro
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%macro bpl 1
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dw 0x4c00 | ((((%1)&0x7ff)<<0)>>1)
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%endmacro
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;;;;; jump+regind ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro jmp 1
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%ifid %1
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; jmp abs
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dw 0x6000 | (((((%1)+0)&0x7ff)<<0)>>1)
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%else
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; jmp (reg)
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dw 0x6c00 | (((%1)&0xf)<<0)
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%endif
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%endmacro
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%macro jsr 1
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dw 0x6400 | (((((%1)+0)&0x7ff)<<0)>>1)
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%endmacro
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%macro loop 1
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dw 0x6800 | (((((%1)+0)&0x7ff)<<0)>>1)
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%endmacro
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%macro input 2
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%ifid %1
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; input abs, reg
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dw 0x8000 | (((%1)&0xff)<<4) | ((%2)&0xf)
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%elifnum %1
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; input abs, reg
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dw 0x8000 | (((%1)&0xff)<<4) | ((%2)&0xf)
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%else
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; input (reg), reg
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dw 0x6d00 | (((%2)&0xf)<<0) | (((%1)&0xf)<<4)
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%endif
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%endmacro
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%macro output 2
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%ifid %2
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; output reg, abs
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dw 0x9000 | (((%2)&0xff)<<4) | ((%1)&0xf)
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%elifnum %2
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; output reg, abs
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dw 0x9000 | (((%2)&0xff)<<4) | ((%1)&0xf)
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%else
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; output reg, (reg)
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dw 0x6e00 | (((%1)&0xf)<<0) | (((%2)&0xf)<<4)
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%endif
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%endmacro
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%macro lmd 2
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%ifid %1
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; lmd abs, reg
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dw 0x7800 | ((((%1)&0xff)<<4)>>1) | (((%2)&0xf)<<0)
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%elifnum %1
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; lmd abs, reg
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dw 0x7800 | ((((%1)&0xff)<<4)>>1) | (((%2)&0xf)<<0)
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%else
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; lmd (reg), reg
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dw 0x6f00 | (((%2)&0xf)<<0) | (((%1)&0xf)<<4)
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%endif
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%endmacro
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;;;;; I/O + misc ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro rts 0
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dw 0x7000
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%endmacro
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%macro wait 0
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dw 0x7100
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%endmacro
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%macro outclr 1
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dw 0x7200 | ((%1)&0xff)
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%endmacro
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%macro outset 1
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dw 0x7300 | ((%1)&0xff)
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%endmacro
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;;;;; I/O bit ops ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro outbclr 2
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dw 0xa000 | ((%1)&0xf) | (((%2)&0xff)<<4)
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%endmacro
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; this is a bug in the original source! this shouldn't happen!
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%macro outclr 2
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outclr %1
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;outbclr %1, %2
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%endmacro
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%macro outbset 2
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dw 0xb000 | ((%1)&0xf) | (((%2)&0xff)<<4)
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%endmacro
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;%macro outset 2
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; outbset %1, %2
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;%endmacro
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;;;;; lli ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%macro lli 2
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dw 0xc000 | (((%1)&0x3ff)<<4) | (((%2)&0xf)<<0)
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%endmacro
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%macro nop 0
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or r0, r0
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%endmacro
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@ -0,0 +1,7 @@
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#!/usr/bin/env bash
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set -e
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set -x
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yasm -fbin -i. -lreasm.lst -oreasm.bin text.asm
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hexdump -C reasm.bin > reasm.hd
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135
text.asm
135
text.asm
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@ -1,17 +1,20 @@
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; vim: set ft=nasm:
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.ORG 0
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%include 'isa.inc'
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%include 'defs.inc'
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org 0
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jmp START_PROCESS
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.ORG LMD_DATA_SPACE
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;org LMD_DATA_SPACE
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DEMENABLE0_RX_IQDUMP:
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.DATA 0x2FCF ; DEMENABLE0 settings (felp, frac,fidc,chfi,bdec,iqmc,mge2,codc,cmix)
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dw 0x2FCF ; DEMENABLE0 settings (felp, frac,fidc,chfi,bdec,iqmc,mge2,codc,cmix)
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DEMENABLE1_RX_IQDUMP:
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.DATA 0x3F9D ; DEMENABLE1
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dw 0x3F9D ; DEMENABLE1
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VITACCCTRL_REG_DEFAULT: ; Transp, downsample + IIR filter setting
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.DATA 0x0001 ; [7:0]=0: no filter
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dw 0x0001 ; [7:0]=0: no filter
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; [7:0]=1: k=1/2
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; [7:0]=2: k=1/4
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; [7:0]=3: k=1/8
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@ -22,65 +25,65 @@ VITACCCTRL_REG_DEFAULT: ; Transp, downsample + IIR filter setting
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; [15: 8]=4, transparent downsample by sixteen
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DEMC1BE0_MASKA_BITS: ; Various bit masks
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.DATA 0x003F
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dw 0x003F
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IQDUMP_MASK_BITS_15_8:
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.DATA 0xFF00
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dw 0xFF00
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IQDUMP_TEST_MAX_VAL:
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.DATA 0x0FFF
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dw 0x0FFF
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IQDUMP_MAX_POS_VAL:
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.DATA 0x07FF ; 2^11 - 1 = 2047
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dw 0x07FF ; 2^11 - 1 = 2047
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IQDUMP_MIN_NEG_VAL:
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.DATA 0xF800 ; -2048
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dw 0xF800 ; -2048
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TRANSPARENT_CAPT:
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.DATA 0x0300 ; Combined RDCAPT0_DEMPDIF0 and RDCAPT0_DEMFIFE2
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dw 0x0300 ; Combined RDCAPT0_DEMPDIF0 and RDCAPT0_DEMFIFE2
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CORR_DEFG_THR:
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.DATA 0x8080
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dw 0x8080
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TX_TONE_COUNT:
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.DATA 0x06 ; Default number of clock ticks for tone in front of preamble
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dw 0x06 ; Default number of clock ticks for tone in front of preamble
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.ORG MDMCONF_IQDUMP
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;org MDMCONF_IQDUMP
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.DATA 0x0003 ; ADCDIGCONF
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.DATA 0x0017 ; MODPRECTRL
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.DATA 0x3D1F ; MODSYMMAP0
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.DATA 0x0000 ; MODSYMMAP1
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.DATA 0x0000 ; MODSOFTTX
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.DATA 0x0800 ; MDMBAUD
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.DATA 0x000F ; MDMBAUDPRE
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.DATA 0x0000 ; MODMAIN
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.DATA 0x0387 ; DEMMISC0
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.DATA 0x0000 ; DEMMISC1
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.DATA 0x4074 ; DEMMISC2
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.DATA 0x0043 ; DEMMISC3
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.DATA 0x8000 ; DEMIQMC0
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.DATA 0x0082 ; DEMDSBU
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.DATA 0x0080 ; DEMDSBU2
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.DATA 0x06F0 ; DEMCODC0
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.DATA 0x0000 ; DEMFIDC0
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.DATA 0x091E ; DEMFEXB0
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.DATA 0x0510 ; DEMDSXB0
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.DATA 0x0054 ; DEMD2XB0
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.DATA 0x0007 ; DEMFIFE0
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.DATA 0x0000 ; DEMMAFI0
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.DATA 0x5014 ; DEMMAFI1
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.DATA 0x0050 ; DEMMAFI2
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.DATA 0x0000 ; DEMMAFI3
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.DATA 0xC02F ; DEMC1BE0
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.DATA 0x0C30 ; DEMC1BE1
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.DATA 0x017F ; DEMC1BE2
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.DATA 0x0000 ; DEMC1BE10
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.DATA 0x0000 ; DEMC1BE11
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.DATA 0x0000 ; DEMC1BE12
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.DATA 0x0000 ; MDMSYNC0
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.DATA 0x0000 ; MDMSYNC1
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.DATA 0x0000 ; MDMSYNC2
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.DATA 0xAA00 ; MDMSYNC3
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.DATA 0x0000 ; DEMSWQU0
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dw 0x0003 ; ADCDIGCONF
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dw 0x0017 ; MODPRECTRL
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dw 0x3D1F ; MODSYMMAP0
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dw 0x0000 ; MODSYMMAP1
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dw 0x0000 ; MODSOFTTX
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dw 0x0800 ; MDMBAUD
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dw 0x000F ; MDMBAUDPRE
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dw 0x0000 ; MODMAIN
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dw 0x0387 ; DEMMISC0
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dw 0x0000 ; DEMMISC1
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dw 0x4074 ; DEMMISC2
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dw 0x0043 ; DEMMISC3
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dw 0x8000 ; DEMIQMC0
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dw 0x0082 ; DEMDSBU
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dw 0x0080 ; DEMDSBU2
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dw 0x06F0 ; DEMCODC0
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dw 0x0000 ; DEMFIDC0
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dw 0x091E ; DEMFEXB0
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dw 0x0510 ; DEMDSXB0
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dw 0x0054 ; DEMD2XB0
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dw 0x0007 ; DEMFIFE0
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dw 0x0000 ; DEMMAFI0
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dw 0x5014 ; DEMMAFI1
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dw 0x0050 ; DEMMAFI2
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dw 0x0000 ; DEMMAFI3
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dw 0xC02F ; DEMC1BE0
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dw 0x0C30 ; DEMC1BE1
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dw 0x017F ; DEMC1BE2
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dw 0x0000 ; DEMC1BE10
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dw 0x0000 ; DEMC1BE11
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dw 0x0000 ; DEMC1BE12
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dw 0x0000 ; MDMSYNC0
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dw 0x0000 ; MDMSYNC1
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dw 0x0000 ; MDMSYNC2
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dw 0xAA00 ; MDMSYNC3
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dw 0x0000 ; DEMSWQU0
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MDMCONF_IQDUMP_END:
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.ORG MAIN
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;org MAIN
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START_PROCESS:
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;; Do hard initialization of all submodules of the modem
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@ -214,7 +217,7 @@ MDMCONF_IQDUMP_END:
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MCFG_Entry:
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; NOTE: = lli text, r0; jsr _DBG_PRINT
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DBG_PRINT0 "MCFG - IQ Dump Configuration"
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DBG_PRINT0 3;"MCFG - IQ Dump Configuration"
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lli MDMCONF_IQDUMP, r1 ; Points R1 to the WMBUS data
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lli MDMCONF_IQDUMP_FIRST_REG, r2 ; Points to the first IO address for configiration
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lli MDMCONF_IQDUMP_LAST_REG, r0 ; Points to the last of the IO address
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@ -414,7 +417,7 @@ MDMCONF_IQDUMP_END:
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outset MCEEVENTCLR1
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;; Normal mode (1bit per symbol) proceeds here
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DBG_PRINT0 "IQDump___ NoFEC, TX Started"
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DBG_PRINT0 4;"IQDump___ NoFEC, TX Started"
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lli 0x10, r0 ; MDMFIFORDCTRL, 1 bits reads, from modem
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output r0, MDMFIFORDCTRL
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jsr MTX_Iqdump_Common_Preamble ; Send Preamble
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@ -434,7 +437,7 @@ MDMCONF_IQDUMP_END:
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outset MCEEVENTCLR0
|
||||
outset MCEEVENTCLR1
|
||||
|
||||
DBG_PRINT0 "IQDump___ Multi-level FSK TX Mode"
|
||||
DBG_PRINT0 5;"IQDump___ Multi-level FSK TX Mode"
|
||||
lli 0x03, r0 ; 4 bit reads, from register
|
||||
output r0, MDMFIFORDCTRL
|
||||
;; Set modctrl to read from modsofftx:
|
||||
|
|
@ -467,7 +470,7 @@ MDMCONF_IQDUMP_END:
|
|||
cmp 2, r0
|
||||
bne MTX_MFSK_ToneLoop
|
||||
;; At this point, we can actually read data from the FIFO, 4 bits at a time
|
||||
DBG_PRINT0 "Starting MFSK Symbol Loop"
|
||||
DBG_PRINT0 6;"Starting MFSK Symbol Loop"
|
||||
MTX_MFSK_SymbolLoop:
|
||||
wait
|
||||
outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1 ; Clear CLKEN Baud
|
||||
|
|
@ -489,7 +492,7 @@ MDMCONF_IQDUMP_END:
|
|||
beq MTX_MFSK_SymbolLoop
|
||||
;;
|
||||
;; FIFO is now empty, so terminate
|
||||
DBG_PRINT0 "Stopping MFSK Symbol Loop"
|
||||
DBG_PRINT0 7;"Stopping MFSK Symbol Loop"
|
||||
outbclr MODCTRL_SOFTTXENABLE, MODCTRL
|
||||
jsr MTX_Iqdump_Termination
|
||||
jmp CMD_OK_END
|
||||
|
|
@ -507,7 +510,7 @@ MDMCONF_IQDUMP_END:
|
|||
outset MCEEVENTCLR1
|
||||
jsr MRX_SETUP
|
||||
|
||||
DBG_PRINT0 "########################### Blind REGISTER MODE -> IQ Dump starting at once ########################"
|
||||
DBG_PRINT0 8;"########################### Blind REGISTER MODE -> IQ Dump starting at once ########################"
|
||||
outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4f event
|
||||
lli 3, r5 ; to trigger capture of I and Q
|
||||
|
||||
|
|
@ -555,7 +558,7 @@ MDMCONF_IQDUMP_END:
|
|||
loop LOOP_SAMPLES_FIFO_BLIND_WAIT
|
||||
|
||||
|
||||
DBG_PRINT0 "########################### Blind RFC FIFO Mode -> IQ Dump starting at once (DataRate <= 12,5 kbps) ########################"
|
||||
DBG_PRINT0 9;"########################### Blind RFC FIFO Mode -> IQ Dump starting at once (DataRate <= 12,5 kbps) ########################"
|
||||
lli 3, r5 ; to trigger capture of I and Q
|
||||
|
||||
LOOP_SAMPLES_FIFO_BLIND:
|
||||
|
|
@ -629,7 +632,7 @@ MDMCONF_IQDUMP_END:
|
|||
wait
|
||||
loop LOOP_SAMPLES_TRANSPARENT_FIFO_WAIT
|
||||
|
||||
DBG_PRINT0 "########################### Transparent FIFO Mode -> PDIFF streaming starting at once ########################"
|
||||
DBG_PRINT0 10;"########################### Transparent FIFO Mode -> PDIFF streaming starting at once ########################"
|
||||
|
||||
lmd TRANSPARENT_CAPT, r13 ; Combined RDCAPT0_DEMPDIF0 and RDCAPT0_DEMFIFE2
|
||||
input VITACCCTRL, r14 ; Capture for later use, time optimization
|
||||
|
|
@ -644,7 +647,7 @@ MDMCONF_IQDUMP_END:
|
|||
btst 1, r0
|
||||
bne CAPT_FREQUENCY
|
||||
outbset 1, RFESEND ; Notify by bit 1 in RFESEND (i.e. Stop AGC)
|
||||
DBG_PRINT0 "########################### Transparent FIFO Mode Stop AGC ########################"
|
||||
DBG_PRINT0 11;"########################### Transparent FIFO Mode Stop AGC ########################"
|
||||
|
||||
|
||||
CAPT_FREQUENCY:
|
||||
|
|
@ -757,7 +760,7 @@ MDMCONF_IQDUMP_END:
|
|||
;;; IQ dump start after SFD detection
|
||||
;;;
|
||||
MRX_Entry_REG_SYNC:
|
||||
DBG_PRINT0 "########################### IQ Dump REGISTER MODE, RX started, Wait for Sync ########################"
|
||||
DBG_PRINT0 12;"########################### IQ Dump REGISTER MODE, RX started, Wait for Sync ########################"
|
||||
;;; Just to be sure those interrupts are disabled, there is no normal termination.
|
||||
outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; disable the clkenbaud_4f event
|
||||
outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event
|
||||
|
|
@ -782,7 +785,7 @@ MDMCONF_IQDUMP_END:
|
|||
DUMP_SAMPLES:
|
||||
outbset 1, RFESEND ; Notify by bit 1 in RFESEND (sync found)
|
||||
|
||||
DBG_PRINT0 "########################### Sync Found REGISTER MODE -> IQ Dump starting ########################"
|
||||
DBG_PRINT0 13;"########################### Sync Found REGISTER MODE -> IQ Dump starting ########################"
|
||||
outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 ; clear the event flag
|
||||
outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event
|
||||
outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4f event
|
||||
|
|
@ -803,7 +806,7 @@ MDMCONF_IQDUMP_END:
|
|||
;;; - IQ dump start after SFD detection
|
||||
;;;
|
||||
MRX_Entry_FIFO_SYNC:
|
||||
DBG_PRINT0 "########################### IQ Dump through RFC FIFO, RX started, Wait for Sync (DataRate <= 12.5 kbps) ########################"
|
||||
DBG_PRINT0 14;"########################### IQ Dump through RFC FIFO, RX started, Wait for Sync (DataRate <= 12.5 kbps) ########################"
|
||||
;;; Just to be sure those interrupts are disabled, there is no normal termination.
|
||||
outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; disable the clkenbaud_4f event
|
||||
outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event
|
||||
|
|
@ -840,7 +843,7 @@ MDMCONF_IQDUMP_END:
|
|||
outbset MCESTROBES0_EVENT0, MCESTROBES0 ; signal Sync Found
|
||||
outbset 1, RFESEND ; Notify by bit 1 in RFESEND (sync found)
|
||||
|
||||
DBG_PRINT0 "########################### Sync Found RFC FIFO MODE-> IQ samples through FIFO starting ########################"
|
||||
DBG_PRINT0 15;"########################### Sync Found RFC FIFO MODE-> IQ samples through FIFO starting ########################"
|
||||
outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2 ; clear the event flag
|
||||
outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2 ; disable correlation event
|
||||
outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0 ; enable the clkenbaud_4 event
|
||||
|
|
@ -915,7 +918,7 @@ MDMCONF_IQDUMP_END:
|
|||
jmp MRX_SETUP ; Go back to test received event
|
||||
|
||||
RFE_Started:
|
||||
DBG_PRINT0 "########################### RX Started ########################"
|
||||
DBG_PRINT0 16;"########################### RX Started ########################"
|
||||
outbset MCEEVENT0_CPEFWEVENT0, MCEEVENTCLR0 ; Clear any pending CPEFWEVENT0
|
||||
|
||||
|
||||
|
|
@ -1075,7 +1078,7 @@ MDMCONF_IQDUMP_END:
|
|||
sl0 8, r4
|
||||
or r0,r4
|
||||
output r4, MDMSTATUS ; Warning: CPE use MDMSTATUS[1:0] for CMD_DONE checking
|
||||
DBG_PRINT0 "All bits received, MCE Ending"
|
||||
DBG_PRINT0 17;"All bits received, MCE Ending"
|
||||
;; Hard init of all modules except FIFO
|
||||
outset TIMCTRL ;
|
||||
outclr TIMCTRL ;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,726 @@
|
|||
0000: 6030 jmp 0x0030 jmp START_PROCESS
|
||||
0001: 2fcf .DATA 0x2FCF
|
||||
0002: 3f9d .DATA 0x3F9D
|
||||
0003: 0001 .DATA 0x0001
|
||||
0004: 003f .DATA 0x003F
|
||||
0005: ff00 .DATA 0xFF00
|
||||
0006: 0fff .DATA 0x0FFF
|
||||
0007: 07ff .DATA 0x07FF
|
||||
0008: f800 .DATA 0xF800
|
||||
0009: 0300 .DATA 0x0300
|
||||
000a: 8080 .DATA 0x8080
|
||||
000b: 0006 .DATA 0x06
|
||||
000c: 0003 .DATA 0x0003
|
||||
000d: 0017 .DATA 0x0017
|
||||
000e: 3d1f .DATA 0x3D1F
|
||||
000f: 0000 .DATA 0x0000
|
||||
0010: 0000 .DATA 0x0000
|
||||
0011: 0800 .DATA 0x0800
|
||||
0012: 000f .DATA 0x000F
|
||||
0013: 0000 .DATA 0x0000
|
||||
0014: 0387 .DATA 0x0387
|
||||
0015: 0000 .DATA 0x0000
|
||||
0016: 4074 .DATA 0x4074
|
||||
0017: 0043 .DATA 0x0043
|
||||
0018: 8000 .DATA 0x8000
|
||||
0019: 0082 .DATA 0x0082
|
||||
001a: 0080 .DATA 0x0080
|
||||
001b: 06f0 .DATA 0x06F0
|
||||
001c: 0000 .DATA 0x0000
|
||||
001d: 091e .DATA 0x091E
|
||||
001e: 0510 .DATA 0x0510
|
||||
001f: 0054 .DATA 0x0054
|
||||
0020: 0007 .DATA 0x0007
|
||||
0021: 0000 .DATA 0x0000
|
||||
0022: 5014 .DATA 0x5014
|
||||
0023: 0050 .DATA 0x0050
|
||||
0024: 0000 .DATA 0x0000
|
||||
0025: c02f .DATA 0xC02F
|
||||
0026: 0c30 .DATA 0x0C30
|
||||
0027: 017f .DATA 0x017F
|
||||
0028: 0000 .DATA 0x0000
|
||||
0029: 0000 .DATA 0x0000
|
||||
002a: 0000 .DATA 0x0000
|
||||
002b: 0000 .DATA 0x0000
|
||||
002c: 0000 .DATA 0x0000
|
||||
002d: 0000 .DATA 0x0000
|
||||
002e: aa00 .DATA 0xAA00
|
||||
002f: 0000 .DATA 0x0000
|
||||
0030: 7223 outclr 0x23 outclr RFESEND
|
||||
0031: 66ca jsr 0x02ca jsr MODCTRL_CLR
|
||||
0032: a35d outbclr 13, 0x35 outbclr DEMMISC2_MLSERUN,DEMMISC2
|
||||
0033: a4e5 outbclr 5, 0x4e outbclr DEMSWQU0_RUN, DEMSWQU0
|
||||
0034: 7303 outset 0x03 outset DEMENABLE0
|
||||
0035: 7305 outset 0x05 outset DEMINIT0
|
||||
0036: 7203 outclr 0x03 outclr DEMENABLE0
|
||||
0037: 7304 outset 0x04 outset DEMENABLE1
|
||||
0038: 7306 outset 0x06 outset DEMINIT1
|
||||
0039: 7204 outclr 0x04 outclr DEMENABLE1
|
||||
003a: 7391 outset 0x91 outset TIMCTRL
|
||||
003b: 7291 outclr 0x91 outclr TIMCTRL
|
||||
003c: b008 outbset 8, 0x00 outbset MDMENABLE_FB2PLL, MDMENABLE
|
||||
003d: ffc0 lli 0x3fc, r0 lli 0x3FC, r0
|
||||
003e: 9010 output r0, 0x01 output r0, MDMINIT
|
||||
003f: a008 outbclr 8, 0x00 outbclr MDMENABLE_FB2PLL, MDMENABLE
|
||||
0040: 720d outclr 0x0d outclr MCEEVENTMSK0
|
||||
0041: 720e outclr 0x0e outclr MCEEVENTMSK1
|
||||
0042: 720f outclr 0x0f outclr MCEEVENTMSK2
|
||||
0043: 7210 outclr 0x10 outclr MCEEVENTMSK3
|
||||
0044: b0d0 outbset 0, 0x0d outbset MCEEVENT0_MDMAPI_WR, MCEEVENTMSK0
|
||||
0045: 7100 wait wait
|
||||
0046: b110 outbset 0, 0x11 outbset MCEEVENT0_MDMAPI_WR, MCEEVENTCLR0
|
||||
0047: a0d0 outbclr 0, 0x0d outbclr MCEEVENT0_MDMAPI_WR, MCEEVENTMSK0
|
||||
0048: 721b outclr 0x1b outclr MDMSTATUS
|
||||
0049: 8162 input 0x16, r2 input MDMAPI, r2
|
||||
004a: 1020 mov r2, r0 mov r2, r0
|
||||
004b: 3952 sr0 5, r2 sr0 5, r2
|
||||
004c: 0670 and 7, r0 and 7, r0
|
||||
004d: 0020 or r2, r0 or r2, r0
|
||||
004e: 1630 add 3, r0 add 3, r0
|
||||
004f: 1101 mov pc, r1 mov pc, r1
|
||||
0050: 1401 add r0, r1 add r0, r1
|
||||
0051: 6c01 jmp (r1) jmp (r1)
|
||||
0052: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0053: 6088 jmp 0x0088 jmp MCFG_Entry
|
||||
0054: 6104 jmp 0x0104 jmp MTX_Entry
|
||||
0055: 613e jmp 0x013e jmp MRX_Entry_REG_BLIND
|
||||
0056: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0057: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0058: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0059: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
005a: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
005b: 6088 jmp 0x0088 jmp MCFG_Entry
|
||||
005c: 6104 jmp 0x0104 jmp MTX_Entry
|
||||
005d: 61e4 jmp 0x01e4 jmp MRX_Entry_REG_SYNC
|
||||
005e: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
005f: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0060: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0061: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0062: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0063: 6088 jmp 0x0088 jmp MCFG_Entry
|
||||
0064: 6104 jmp 0x0104 jmp MTX_Entry
|
||||
0065: 614e jmp 0x014e jmp MRX_Entry_FIFO_BLIND
|
||||
0066: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0067: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0068: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0069: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
006a: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
006b: 6088 jmp 0x0088 jmp MCFG_Entry
|
||||
006c: 6104 jmp 0x0104 jmp MTX_Entry
|
||||
006d: 6200 jmp 0x0200 jmp MRX_Entry_FIFO_SYNC
|
||||
006e: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
006f: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0070: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0071: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0072: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0073: 6088 jmp 0x0088 jmp MCFG_Entry
|
||||
0074: 6104 jmp 0x0104 jmp MTX_Entry
|
||||
0075: 6186 jmp 0x0186 jmp MRX_Entry_TRANSPARENT_FIFO
|
||||
0076: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0077: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0078: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
0079: 6087 jmp 0x0087 jmp MNOP_Entry
|
||||
007a: 6088 jmp 0x0088 jmp MCFG_Entry
|
||||
007b: 6112 jmp 0x0112 jmp MTX_MFSK
|
||||
007c: 614e jmp 0x014e jmp MRX_Entry_FIFO_BLIND
|
||||
007d: 1210 mov 1, r0 mov CMD_OK, r0
|
||||
007e: 7223 outclr 0x23 outclr RFESEND
|
||||
007f: 7311 outset 0x11 outset MCEEVENTCLR0
|
||||
0080: 7312 outset 0x12 outset MCEEVENTCLR1
|
||||
0081: 7313 outset 0x13 outset MCEEVENTCLR2
|
||||
0082: 81b1 input 0x1b, r1 input MDMSTATUS, r1
|
||||
0083: 0010 or r1, r0 or r1, r0
|
||||
0084: 91b0 output r0, 0x1b output r0, MDMSTATUS
|
||||
0085: b070 outbset 0, 0x07 outbset 0, MCESTROBES0
|
||||
0086: 6044 jmp 0x0044 jmp CMD_PROC
|
||||
0087: 607d jmp 0x007d jmp CMD_OK_END
|
||||
0088: c030 lli 0x3, r0 lli "MCFG - IQ Dump Configuration"
|
||||
0088: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
008a: c0c1 lli 0xc, r1 lli MDMCONF_IQDUMP, r1
|
||||
008b: c2b2 lli 0x2b, r2 lli MDMCONF_IQDUMP_FIRST_REG, r2
|
||||
008c: c4e0 lli 0x4e, r0 lli MDMCONF_IQDUMP_LAST_REG, r0
|
||||
008d: 1820 sub r2, r0 sub r2,r0
|
||||
008e: 6f13 lmd (r1), r3 lmd (r1), r3
|
||||
008f: 6e23 output r3, (r2) output r3, (r2)
|
||||
0090: 1611 add 1, r1 add 1, r1
|
||||
0091: 1612 add 1, r2 add 1, r2
|
||||
0092: 688e loop 0x008e loop MCFG_Iqdump_Loop
|
||||
0093: 7830 lmd 0x3, r0 lmd VITACCCTRL_REG_DEFAULT,r0
|
||||
0094: 99c0 output r0, 0x9c output r0,VITACCCTRL
|
||||
0095: 78a0 lmd 0xa, r0 lmd CORR_DEFG_THR, r0
|
||||
0096: 9480 output r0, 0x48 output r0, DEMC1BE11
|
||||
0097: 9490 output r0, 0x49 output r0, DEMC1BE12
|
||||
0098: c4f2 lli 0x4f, r2 lli DEMFB2P0, r2
|
||||
0099: c750 lli 0x75, r0 lli VITCTRL, r0
|
||||
009a: 1820 sub r2, r0 sub r2,r0
|
||||
009b: 40a0 beq 0x00a0 beq ZERO_DONE
|
||||
009c: 1203 mov 0, r3 mov 0, r3
|
||||
009d: 6e23 output r3, (r2) output r3, (r2)
|
||||
009e: 1612 add 1, r2 add 1, r2
|
||||
009f: 689d loop 0x009d loop ZERO_LOOP
|
||||
00a0: 78b0 lmd 0xb, r0 lmd TX_TONE_COUNT, r0
|
||||
00a1: 9990 output r0, 0x99 output r0, BRMACC0
|
||||
00a2: 7263 outclr 0x63 outclr MODCTRL
|
||||
00a3: b63c outbset 12, 0x63 outbset MODCTRL_CDC_COL_RESTART, MODCTRL
|
||||
00a4: 607d jmp 0x007d jmp CMD_OK_END
|
||||
00a5: 8190 input 0x19, r0 input MDMCMDPAR2, r0
|
||||
00a6: 9640 output r0, 0x64 output r0, MODPREAMBLE
|
||||
00a7: 8170 input 0x17, r0 input MDMCMDPAR0, r0
|
||||
00a8: 3980 sr0 8, r0 sr0 8, r0
|
||||
00a9: 2a70 bclr 7, r0 bclr 7, r0
|
||||
00aa: 1001 mov r0, r1 mov r0, r1
|
||||
00ab: 1611 add 1, r1 add 1, r1
|
||||
00ac: 84a2 input 0x4a, r2 input MDMSYNC0, r2
|
||||
00ad: 84b4 input 0x4b, r4 input MDMSYNC1, r4
|
||||
00ae: c0f3 lli 0xf, r3 lli 15, r3
|
||||
00af: c0f5 lli 0xf, r5 lli 15, r5
|
||||
00b0: c200 lli 0x20, r0 lli 32, r0
|
||||
00b1: 1c01 cmp r0, r1 cmp r0, r1
|
||||
00b2: 40c9 beq 0x00c9 beq MTX_Iqdump_Common_Preamble_RFESEND
|
||||
00b3: c100 lli 0x10, r0 lli 16, r0
|
||||
00b4: 1c10 cmp r1, r0 cmp r1, r0
|
||||
00b5: 40bf beq 0x00bf beq MTX_Iqdump_Common_Preamble_16bitSyncWord
|
||||
00b6: 4cc1 bpl 0x00c1 bpl MTX_Iqdump_Common_Preamble_ShortSyncWord
|
||||
00b7: 1013 mov r1, r3 mov r1, r3
|
||||
00b8: 1803 sub r0, r3 sub r0, r3
|
||||
00b9: 1830 sub r3, r0 sub r3, r0
|
||||
00ba: 1a13 sub 1, r3 sub 1, r3
|
||||
00bb: 1a10 sub 1, r0 sub 1, r0
|
||||
00bc: 3912 sr0 1, r2 sr0 1, r2
|
||||
00bd: 68bc loop 0x00bc loop MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop1
|
||||
00be: 60c9 jmp 0x00c9 jmp MTX_Iqdump_Common_Preamble_RFESEND
|
||||
00bf: 13f3 mov 31, r3 mov 0x1F, r3
|
||||
00c0: 60c9 jmp 0x00c9 jmp MTX_Iqdump_Common_Preamble_RFESEND
|
||||
00c1: 13f3 mov 31, r3 mov 0x1F, r3
|
||||
00c2: 1015 mov r1, r5 mov r1, r5
|
||||
00c3: c100 lli 0x10, r0 lli 16, r0
|
||||
00c4: 1850 sub r5, r0 sub r5, r0
|
||||
00c5: 1a15 sub 1, r5 sub 1, r5
|
||||
00c6: 1a10 sub 1, r0 sub 1, r0
|
||||
00c7: 3914 sr0 1, r4 sr0 1, r4
|
||||
00c8: 68c7 loop 0x00c7 loop MTX_Iqdump_Common_Preamble_SyncWord_ShiftLoop2
|
||||
00c9: b0e8 outbset 8, 0x0e outbset MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
||||
00ca: 7100 wait wait
|
||||
00cb: b128 outbset 8, 0x12 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTCLR1
|
||||
00cc: a0e8 outbclr 8, 0x0e outbclr MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
||||
00cd: b230 outbset 0, 0x23 outbset 0,RFESEND
|
||||
00ce: b910 outbset 0, 0x91 outbset TIMCTRL_ENABLETIMER, TIMCTRL
|
||||
00cf: 8990 input 0x99, r0 input BRMACC0, r0
|
||||
00d0: 9930 output r0, 0x93 output r0, TIMPERIOD
|
||||
00d1: b111 outbset 1, 0x11 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
||||
00d2: b0d1 outbset 1, 0x0d outbset MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
||||
00d3: 7100 wait wait
|
||||
00d4: b002 outbset 2, 0x00 outbset MDMENABLE_TIMEBASE, MDMENABLE
|
||||
00d5: b012 outbset 2, 0x01 outbset MDMINIT_TIMEBASE, MDMINIT
|
||||
00d6: b111 outbset 1, 0x11 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
||||
00d7: a0d1 outbclr 1, 0x0d outbclr MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
||||
00d8: 7291 outclr 0x91 outclr TIMCTRL
|
||||
00d9: b630 outbset 0, 0x63 outbset MODCTRL_PREAMBLEINSERT, MODCTRL
|
||||
00da: b003 outbset 3, 0x00 outbset MDMENABLE_MODULATOR, MDMENABLE
|
||||
00db: b013 outbset 3, 0x01 outbset MDMINIT_MODULATOR, MDMINIT
|
||||
00dc: 722c outclr 0x2c outclr MODPRECTRL
|
||||
00dd: b0e0 outbset 0, 0x0e outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTMSK1
|
||||
00de: 7100 wait wait
|
||||
00df: b120 outbset 0, 0x12 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
||||
00e0: 8170 input 0x17, r0 input MDMCMDPAR0, r0
|
||||
00e1: 92c0 output r0, 0x2c output r0, MODPRECTRL
|
||||
00e2: 7100 wait wait
|
||||
00e3: b120 outbset 0, 0x12 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
||||
00e4: 8170 input 0x17, r0 input MDMCMDPAR0, r0
|
||||
00e5: 22f0 btst 15, r0 btst 15, r0
|
||||
00e6: 44e2 bne 0x00e2 bne MTX_Iqdump_Common_Preamble_Loop
|
||||
00e7: 13f0 mov 31, r0 mov 0x1F, r0
|
||||
00e8: 1c03 cmp r0, r3 cmp r0, r3
|
||||
00e9: 40ee beq 0x00ee beq MTX_Iqdump_Common_Preamble_Send_One_SW
|
||||
00ea: 92c3 output r3, 0x2c output r3, MODPRECTRL
|
||||
00eb: 9642 output r2, 0x64 output r2, MODPREAMBLE
|
||||
00ec: 7100 wait wait
|
||||
00ed: b120 outbset 0, 0x12 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
||||
00ee: 92c5 output r5, 0x2c output r5, MODPRECTRL
|
||||
00ef: 9644 output r4, 0x64 output r4, MODPREAMBLE
|
||||
00f0: 7100 wait wait
|
||||
00f1: b120 outbset 0, 0x12 outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTCLR1
|
||||
00f2: b0e0 outbset 0, 0x0e outbset MCEEVENT1_PREAMBLE_DONE, MCEEVENTMSK1
|
||||
00f3: a630 outbclr 0, 0x63 outbclr MODCTRL_PREAMBLEINSERT, MODCTRL
|
||||
00f4: 7000 rts rts
|
||||
00f5: a0e1 outbclr 1, 0x0e outbclr MCEEVENT1_CLKEN_BAUD, MCEEVENTMSK1
|
||||
00f6: c030 lli 0x3, r0 lli 0x03,r0
|
||||
00f7: 9910 output r0, 0x91 output r0, TIMCTRL
|
||||
00f8: c040 lli 0x4, r0 lli 0x04, r0
|
||||
00f9: 9930 output r0, 0x93 output r0, TIMPERIOD
|
||||
00fa: b111 outbset 1, 0x11 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
||||
00fb: b0d1 outbset 1, 0x0d outbset MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
||||
00fc: 7100 wait wait
|
||||
00fd: b111 outbset 1, 0x11 outbset MCEEVENT0_TIMER_IRQ, MCEEVENTCLR0
|
||||
00fe: a0d1 outbclr 1, 0x0d outbclr MCEEVENT0_TIMER_IRQ, MCEEVENTMSK0
|
||||
00ff: 7291 outclr 0x91 outclr TIMCTRL
|
||||
0100: a003 outbclr 3, 0x00 outbclr MDMENABLE_MODULATOR, MDMENABLE
|
||||
0101: a002 outbclr 2, 0x00 outbclr MDMENABLE_TIMEBASE, MDMENABLE
|
||||
0102: a230 outbclr 0, 0x23 outbclr 0, RFESEND
|
||||
0103: 7000 rts rts
|
||||
0104: 7311 outset 0x11 outset MCEEVENTCLR0
|
||||
0105: 7312 outset 0x12 outset MCEEVENTCLR1
|
||||
0106: c040 lli 0x4, r0 lli "IQDump___ NoFEC, TX Started"
|
||||
0106: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
0108: c100 lli 0x10, r0 lli 0x10, r0
|
||||
0109: 91f0 output r0, 0x1f output r0, MDMFIFORDCTRL
|
||||
010a: 64a5 jsr 0x00a5 jsr MTX_Iqdump_Common_Preamble
|
||||
010b: b633 outbset 3, 0x63 outbset MODCTRL_FECENABLE, MODCTRL
|
||||
010c: b113 outbset 3, 0x11 outbset MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTCLR0
|
||||
010d: b0d3 outbset 3, 0x0d outbset MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTMSK0
|
||||
010e: 7100 wait wait
|
||||
010f: a0d3 outbclr 3, 0x0d outbclr MCEEVENT0_FIFO_ERR_UNDERFLOW, MCEEVENTMSK0
|
||||
0110: 64f5 jsr 0x00f5 jsr MTX_Iqdump_Termination
|
||||
0111: 607d jmp 0x007d jmp CMD_OK_END
|
||||
0112: 7311 outset 0x11 outset MCEEVENTCLR0
|
||||
0113: 7312 outset 0x12 outset MCEEVENTCLR1
|
||||
0114: c050 lli 0x5, r0 lli "IQDump___ Multi-level FSK TX Mode"
|
||||
0114: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
0116: c030 lli 0x3, r0 lli 0x03, r0
|
||||
0117: 91f0 output r0, 0x1f output r0, MDMFIFORDCTRL
|
||||
0118: b634 outbset 4, 0x63 outbset MODCTRL_SOFTTXENABLE, MODCTRL
|
||||
0119: b0e8 outbset 8, 0x0e outbset MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
||||
011a: 7100 wait wait
|
||||
011b: b128 outbset 8, 0x12 outbset MCEEVENT1_RAT_EVENT0, MCEEVENTCLR1
|
||||
011c: a0e8 outbclr 8, 0x0e outbclr MCEEVENT1_RAT_EVENT0, MCEEVENTMSK1
|
||||
011d: b230 outbset 0, 0x23 outbset 0,RFESEND
|
||||
011e: b002 outbset 2, 0x00 outbset MDMENABLE_TIMEBASE, MDMENABLE
|
||||
011f: b012 outbset 2, 0x01 outbset MDMINIT_TIMEBASE, MDMINIT
|
||||
0120: b003 outbset 3, 0x00 outbset MDMENABLE_MODULATOR, MDMENABLE
|
||||
0121: b013 outbset 3, 0x01 outbset MDMINIT_MODULATOR, MDMINIT
|
||||
0122: 1200 mov 0, r0 mov 0, r0
|
||||
0123: 92f0 output r0, 0x2f output r0, MODSOFTTX
|
||||
0124: b121 outbset 1, 0x12 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1
|
||||
0125: b0e1 outbset 1, 0x0e outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTMSK1
|
||||
0126: 7100 wait wait
|
||||
0127: b121 outbset 1, 0x12 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1
|
||||
0128: 8210 input 0x21, r0 input MDMFIFOSTA, r0
|
||||
0129: 0620 and 2, r0 and 2, r0
|
||||
012a: 1e20 cmp 2, r0 cmp 2, r0
|
||||
012b: 4526 bne 0x0126 bne MTX_MFSK_ToneLoop
|
||||
012c: c060 lli 0x6, r0 lli "Starting MFSK Symbol Loop"
|
||||
012c: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
012e: 7100 wait wait
|
||||
012f: b121 outbset 1, 0x12 outbset MCEEVENT1_CLKEN_BAUD, MCEEVENTCLR1
|
||||
0130: 81d1 input 0x1d, r1 input MDMFIFORD, r1
|
||||
0131: 92f1 output r1, 0x2f output r1, MODSOFTTX
|
||||
0132: 0000 or r0, r0 nop
|
||||
0133: 0000 or r0, r0 nop
|
||||
0134: 0000 or r0, r0 nop
|
||||
0135: 8212 input 0x21, r2 input MDMFIFOSTA, r2
|
||||
0136: 0622 and 2, r2 and 2, r2
|
||||
0137: 1e22 cmp 2, r2 cmp 2, r2
|
||||
0138: 412e beq 0x012e beq MTX_MFSK_SymbolLoop
|
||||
0139: c070 lli 0x7, r0 lli "Stopping MFSK Symbol Loop"
|
||||
0139: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
013b: a634 outbclr 4, 0x63 outbclr MODCTRL_SOFTTXENABLE, MODCTRL
|
||||
013c: 64f5 jsr 0x00f5 jsr MTX_Iqdump_Termination
|
||||
013d: 607d jmp 0x007d jmp CMD_OK_END
|
||||
013e: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
013f: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
0140: a0f3 outbclr 3, 0x0f outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
||||
0141: 7311 outset 0x11 outset MCEEVENTCLR0
|
||||
0142: 7312 outset 0x12 outset MCEEVENTCLR1
|
||||
0143: 6644 jsr 0x0244 jsr MRX_SETUP
|
||||
0144: c080 lli 0x8, r0 lli "########################### Blind REGISTER MODE -> IQ Dump starting at once ########################"
|
||||
0144: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
0146: b0d2 outbset 2, 0x0d outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
0147: c035 lli 0x3, r5 lli 3, r5
|
||||
0148: 7100 wait wait
|
||||
0149: 9b75 output r5, 0xb7 output r5, RDCAPT1
|
||||
014a: ba38 outbset 8, 0xa3 outbset RDCAPT0_DEMPDIF0, RDCAPT0
|
||||
014b: b074 outbset 4, 0x07 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
||||
014c: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
014d: 6148 jmp 0x0148 jmp LOOP_SAMPLES_BLIND
|
||||
014e: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
014f: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
0150: a0f3 outbclr 3, 0x0f outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
||||
0151: 7311 outset 0x11 outset MCEEVENTCLR0
|
||||
0152: 7312 outset 0x12 outset MCEEVENTCLR1
|
||||
0153: 6644 jsr 0x0244 jsr MRX_SETUP
|
||||
0154: c18b lli 0x18, r11 lli 24, r11
|
||||
0155: c000 lli 0x0, r0 lli 0x0, r0
|
||||
0156: 91e0 output r0, 0x1e output r0, MDMFIFOWRCTRL
|
||||
0157: 120c mov 0, r12 mov 0, r12
|
||||
0158: 1218 mov 1, r8 mov 1, r8
|
||||
0159: 786a lmd 0x6, r10 lmd IQDUMP_TEST_MAX_VAL, r10
|
||||
015a: 787d lmd 0x7, r13 lmd IQDUMP_MAX_POS_VAL, r13
|
||||
015b: 788e lmd 0x8, r14 lmd IQDUMP_MIN_NEG_VAL, r14
|
||||
015c: 10a9 mov r10, r9 mov r10, r9
|
||||
015d: b074 outbset 4, 0x07 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
||||
015e: b0d2 outbset 2, 0x0d outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
015f: c050 lli 0x5, r0 lli 5, r0
|
||||
0160: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
0161: 7100 wait wait
|
||||
0162: 6960 loop 0x0160 loop LOOP_SAMPLES_FIFO_BLIND_WAIT
|
||||
0163: c090 lli 0x9, r0 lli "########################### Blind RFC FIFO Mode -> IQ Dump starting at once (DataRate <= 12,5 kbps) ########################"
|
||||
0163: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
0165: c035 lli 0x3, r5 lli 3, r5
|
||||
0166: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
0167: 7100 wait wait
|
||||
0168: 9b75 output r5, 0xb7 output r5, RDCAPT1
|
||||
0169: 8bf0 input 0xbf, r0 input DEMFRAC4, r0
|
||||
016a: 65d9 jsr 0x01d9 jsr SignExt_and_Saturate
|
||||
016b: 8ca1 input 0xca, r1 input MDMSPAR2, r1
|
||||
016c: 2201 btst 0, r1 btst 0, r1
|
||||
016d: 4173 beq 0x0173 beq LOOP_SAMPLES_FIFO_BLIND_DEMFRAC4WR
|
||||
016e: 1080 mov r8, r0 mov r8, r0
|
||||
016f: 1ca8 cmp r10, r8 cmp r10, r8
|
||||
0170: 4572 bne 0x0172 bne TEST_PATTERN_ADD_BLIND
|
||||
0171: 1208 mov 0, r8 mov 0, r8
|
||||
0172: 1618 add 1, r8 add 1, r8
|
||||
0173: 65d0 jsr 0x01d0 jsr MDMFIFOWR_AND_WAIT10
|
||||
0174: 8c00 input 0xc0, r0 input DEMFRAC5, r0
|
||||
0175: 65d9 jsr 0x01d9 jsr SignExt_and_Saturate
|
||||
0176: 8ca1 input 0xca, r1 input MDMSPAR2, r1
|
||||
0177: 2201 btst 0, r1 btst 0, r1
|
||||
0178: 417e beq 0x017e beq LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR
|
||||
0179: 1090 mov r9, r0 mov r9, r0
|
||||
017a: 1a19 sub 1, r9 sub 1, r9
|
||||
017b: 1e09 cmp 0, r9 cmp 0, r9
|
||||
017c: 457e bne 0x017e bne LOOP_SAMPLES_FIFO_BLIND_DEMFRAC5WR
|
||||
017d: 10a9 mov r10, r9 mov r10, r9
|
||||
017e: 65d0 jsr 0x01d0 jsr MDMFIFOWR_AND_WAIT10
|
||||
017f: 8184 input 0x18, r4 input MDMCMDPAR1, r4
|
||||
0180: 1e04 cmp 0, r4 cmp 0, r4
|
||||
0181: 4166 beq 0x0166 beq LOOP_SAMPLES_FIFO_BLIND
|
||||
0182: 14bc add r11, r12 add r11, r12
|
||||
0183: 1c4c cmp r4, r12 cmp r4, r12
|
||||
0184: 4eb3 bpl 0x02b3 bpl MRX_GenFSK_CommonEnd
|
||||
0185: 6166 jmp 0x0166 jmp LOOP_SAMPLES_FIFO_BLIND
|
||||
0186: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
0187: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
0188: a0f3 outbclr 3, 0x0f outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
||||
0189: 7311 outset 0x11 outset MCEEVENTCLR0
|
||||
018a: 7312 outset 0x12 outset MCEEVENTCLR1
|
||||
018b: 6644 jsr 0x0244 jsr MRX_SETUP
|
||||
018c: 721e outclr 0x1e outclr MDMFIFOWRCTRL
|
||||
018d: 120c mov 0, r12 mov 0, r12
|
||||
018e: 1205 mov 0, r5 mov 0, r5
|
||||
018f: b074 outbset 4, 0x07 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
||||
0190: b0d2 outbset 2, 0x0d outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
0191: c050 lli 0x5, r0 lli 5, r0
|
||||
0192: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
0193: 7100 wait wait
|
||||
0194: 6992 loop 0x0192 loop LOOP_SAMPLES_TRANSPARENT_FIFO_WAIT
|
||||
0195: c0a0 lli 0xa, r0 lli "########################### Transparent FIFO Mode -> PDIFF streaming starting at once ########################"
|
||||
0195: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
0197: 789d lmd 0x9, r13 lmd TRANSPARENT_CAPT, r13
|
||||
0198: 89ce input 0x9c, r14 input VITACCCTRL, r14
|
||||
0199: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
019a: 7100 wait wait
|
||||
019b: 8c90 input 0xc9, r0 input MDMSPAR1, r0
|
||||
019c: 2200 btst 0, r0 btst 0, r0
|
||||
019d: 41a4 beq 0x01a4 beq CAPT_FREQUENCY
|
||||
019e: 8230 input 0x23, r0 input RFESEND, r0
|
||||
019f: 2210 btst 1, r0 btst 1, r0
|
||||
01a0: 45a4 bne 0x01a4 bne CAPT_FREQUENCY
|
||||
01a1: b231 outbset 1, 0x23 outbset 1, RFESEND
|
||||
01a2: c0b0 lli 0xb, r0 lli "########################### Transparent FIFO Mode Stop AGC ########################"
|
||||
01a2: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
01a4: 9a3d output r13, 0xa3 output r13, RDCAPT0
|
||||
01a5: 8ab2 input 0xab, r2 input DEMPDIF0, r2
|
||||
01a6: 3182 sl0 8, r2 sl0 8, r2
|
||||
01a7: 3d82 srx 8, r2 srx 8, r2
|
||||
01a8: 8af0 input 0xaf, r0 input DEMFIFE2,r0
|
||||
01a9: 3180 sl0 8, r0 sl0 8, r0
|
||||
01aa: 3d80 srx 8, r0 srx 8, r0
|
||||
01ab: 1802 sub r0, r2 sub r0, r2
|
||||
01ac: 063e and 3, r14 and 3, r14
|
||||
01ad: 1e0e cmp 0, r14 cmp 0, r14
|
||||
01ae: 41c6 beq 0x01c6 beq NO_IIR_FILTER
|
||||
01af: 1e2e cmp 2, r14 cmp 2, r14
|
||||
01b0: 41b8 beq 0x01b8 beq IIR_K4
|
||||
01b1: 1e3e cmp 3, r14 cmp 3, r14
|
||||
01b2: 41bf beq 0x01bf beq IIR_K8
|
||||
01b3: 1056 mov r5, r6 mov r5, r6
|
||||
01b4: 1426 add r2, r6 add r2, r6
|
||||
01b5: 3d16 srx 1, r6 srx 1, r6
|
||||
01b6: 1065 mov r6, r5 mov r6, r5
|
||||
01b7: 61c7 jmp 0x01c7 jmp HARD_DECISION
|
||||
01b8: 1056 mov r5, r6 mov r5, r6
|
||||
01b9: 3126 sl0 2, r6 sl0 2, r6
|
||||
01ba: 1856 sub r5, r6 sub r5,r6
|
||||
01bb: 1426 add r2, r6 add r2, r6
|
||||
01bc: 3d26 srx 2, r6 srx 2, r6
|
||||
01bd: 1065 mov r6, r5 mov r6, r5
|
||||
01be: 61c7 jmp 0x01c7 jmp HARD_DECISION
|
||||
01bf: 1056 mov r5, r6 mov r5, r6
|
||||
01c0: 3136 sl0 3, r6 sl0 3, r6
|
||||
01c1: 1856 sub r5, r6 sub r5,r6
|
||||
01c2: 1426 add r2, r6 add r2, r6
|
||||
01c3: 3d36 srx 3, r6 srx 3, r6
|
||||
01c4: 1065 mov r6, r5 mov r6, r5
|
||||
01c5: 61c7 jmp 0x01c7 jmp HARD_DECISION
|
||||
01c6: 1026 mov r2, r6 mov r2, r6
|
||||
01c7: 3976 sr0 7, r6 sr0 7, r6
|
||||
01c8: 91c6 output r6, 0x1c output r6, MDMFIFOWR
|
||||
01c9: 8184 input 0x18, r4 input MDMCMDPAR1, r4
|
||||
01ca: 1e04 cmp 0, r4 cmp 0, r4
|
||||
01cb: 4199 beq 0x0199 beq LOOP_SAMPLES_TRANSPARENT_FIFO
|
||||
01cc: 161c add 1, r12 add 1, r12
|
||||
01cd: 1c4c cmp r4, r12 cmp r4, r12
|
||||
01ce: 4eb3 bpl 0x02b3 bpl MRX_GenFSK_CommonEnd
|
||||
01cf: 6199 jmp 0x0199 jmp LOOP_SAMPLES_TRANSPARENT_FIFO
|
||||
01d0: 1001 mov r0, r1 mov r0, r1
|
||||
01d1: c0b0 lli 0xb, r0 lli 11, r0
|
||||
01d2: 91c1 output r1, 0x1c output r1, MDMFIFOWR
|
||||
01d3: 3911 sr0 1, r1 sr0 1, r1
|
||||
01d4: 1000 mov r0, r0 mov r0, r0
|
||||
01d5: 1000 mov r0, r0 mov r0, r0
|
||||
01d6: 1000 mov r0, r0 mov r0, r0
|
||||
01d7: 69d2 loop 0x01d2 loop LOOP_MDMFIFOWR
|
||||
01d8: 7000 rts rts
|
||||
01d9: 3130 sl0 3, r0 sl0 3, r0
|
||||
01da: 3d30 srx 3, r0 srx 3, r0
|
||||
01db: 1cd0 cmp r13, r0 cmp r13, r0
|
||||
01dc: 4de0 bpl 0x01e0 bpl Pos_Sat
|
||||
01dd: 1ce0 cmp r14, r0 cmp r14, r0
|
||||
01de: 49e2 bmi 0x01e2 bmi Neg_Sat
|
||||
01df: 7000 rts rts
|
||||
01e0: 10d0 mov r13, r0 mov r13, r0
|
||||
01e1: 7000 rts rts
|
||||
01e2: 10e0 mov r14, r0 mov r14, r0
|
||||
01e3: 7000 rts rts
|
||||
01e4: c0c0 lli 0xc, r0 lli "########################### IQ Dump REGISTER MODE, RX started, Wait for Sync ########################"
|
||||
01e4: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
01e6: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
01e7: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
01e8: a0f3 outbclr 3, 0x0f outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
||||
01e9: 7311 outset 0x11 outset MCEEVENTCLR0
|
||||
01ea: 7312 outset 0x12 outset MCEEVENTCLR1
|
||||
01eb: 6644 jsr 0x0244 jsr MRX_SETUP
|
||||
01ec: b130 outbset 0, 0x13 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
||||
01ed: b0f0 outbset 0, 0x0f outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
01ee: 7100 wait wait
|
||||
01ef: 80b0 input 0x0b, r0 input MCEEVENT2, r0
|
||||
01f0: 2200 btst 0, r0 btst MCEEVENT2_C1BE_A_POS_PEAK, r0
|
||||
01f1: 45f3 bne 0x01f3 bne DUMP_SAMPLES
|
||||
01f2: 61ee jmp 0x01ee jmp SYNC_SEARCH
|
||||
01f3: b231 outbset 1, 0x23 outbset 1, RFESEND
|
||||
01f4: c0d0 lli 0xd, r0 lli "########################### Sync Found REGISTER MODE -> IQ Dump starting ########################"
|
||||
01f4: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
01f6: b130 outbset 0, 0x13 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
||||
01f7: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
01f8: b0d2 outbset 2, 0x0d outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
01f9: c035 lli 0x3, r5 lli 3, r5
|
||||
01fa: 7100 wait wait
|
||||
01fb: 9b75 output r5, 0xb7 output r5, RDCAPT1
|
||||
01fc: ba38 outbset 8, 0xa3 outbset RDCAPT0_DEMPDIF0, RDCAPT0
|
||||
01fd: b074 outbset 4, 0x07 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
||||
01fe: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
01ff: 61fa jmp 0x01fa jmp LOOP_SAMPLES
|
||||
0200: c0e0 lli 0xe, r0 lli "########################### IQ Dump through RFC FIFO, RX started, Wait for Sync (DataRate <= 12.5 kbps) ########################"
|
||||
0200: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
0202: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
0203: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
0204: a0f3 outbclr 3, 0x0f outbclr MCEEVENT2_C1BE_B_POS_PEAK, MCEEVENTMSK2
|
||||
0205: 7311 outset 0x11 outset MCEEVENTCLR0
|
||||
0206: 7312 outset 0x12 outset MCEEVENTCLR1
|
||||
0207: 6644 jsr 0x0244 jsr MRX_SETUP
|
||||
0208: c18b lli 0x18, r11 lli 24, r11
|
||||
0209: c000 lli 0x0, r0 lli 0x0, r0
|
||||
020a: 91e0 output r0, 0x1e output r0, MDMFIFOWRCTRL
|
||||
020b: 120c mov 0, r12 mov 0, r12
|
||||
020c: 1218 mov 1, r8 mov 1, r8
|
||||
020d: 786a lmd 0x6, r10 lmd IQDUMP_TEST_MAX_VAL, r10
|
||||
020e: 787d lmd 0x7, r13 lmd IQDUMP_MAX_POS_VAL, r13
|
||||
020f: 788e lmd 0x8, r14 lmd IQDUMP_MIN_NEG_VAL, r14
|
||||
0210: 10a9 mov r10, r9 mov r10, r9
|
||||
0211: b130 outbset 0, 0x13 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
||||
0212: b0f0 outbset 0, 0x0f outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
0213: 7100 wait wait
|
||||
0214: 80b0 input 0x0b, r0 input MCEEVENT2, r0
|
||||
0215: 2200 btst 0, r0 btst MCEEVENT2_C1BE_A_POS_PEAK, r0
|
||||
0216: 4618 bne 0x0218 bne DUMP_SAMPLES_FIFO
|
||||
0217: 6213 jmp 0x0213 jmp SYNC_SEARCH_FIFO
|
||||
0218: b074 outbset 4, 0x07 outbset MCESTROBES0_EVENT0, MCESTROBES0
|
||||
0219: b231 outbset 1, 0x23 outbset 1, RFESEND
|
||||
021a: c0f0 lli 0xf, r0 lli "########################### Sync Found RFC FIFO MODE-> IQ samples through FIFO starting ########################"
|
||||
021a: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
021c: b130 outbset 0, 0x13 outbset MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTCLR2
|
||||
021d: a0f0 outbclr 0, 0x0f outbclr MCEEVENT2_C1BE_A_POS_PEAK, MCEEVENTMSK2
|
||||
021e: b0d2 outbset 2, 0x0d outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
021f: c020 lli 0x2, r0 lli 2, r0
|
||||
0220: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
0221: 7100 wait wait
|
||||
0222: 6a20 loop 0x0220 loop LOOP_SAMPLES_FIFO_SYNC_WAIT
|
||||
0223: c035 lli 0x3, r5 lli 3, r5
|
||||
0224: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
0225: 7100 wait wait
|
||||
0226: 9b75 output r5, 0xb7 output r5, RDCAPT1
|
||||
0227: 8bf0 input 0xbf, r0 input DEMFRAC4, r0
|
||||
0228: 65d9 jsr 0x01d9 jsr SignExt_and_Saturate
|
||||
0229: 8ca1 input 0xca, r1 input MDMSPAR2, r1
|
||||
022a: 2201 btst 0, r1 btst 0, r1
|
||||
022b: 4231 beq 0x0231 beq LOOP_SAMPLES_FIFO_SYNC_DEMFRAC4WR
|
||||
022c: 1080 mov r8, r0 mov r8, r0
|
||||
022d: 1ca8 cmp r10, r8 cmp r10, r8
|
||||
022e: 4630 bne 0x0230 bne TEST_PATTERN_ADD_SYNC
|
||||
022f: 1208 mov 0, r8 mov 0, r8
|
||||
0230: 1618 add 1, r8 add 1, r8
|
||||
0231: 65d0 jsr 0x01d0 jsr MDMFIFOWR_AND_WAIT10
|
||||
0232: 8c00 input 0xc0, r0 input DEMFRAC5, r0
|
||||
0233: 65d9 jsr 0x01d9 jsr SignExt_and_Saturate
|
||||
0234: 8ca1 input 0xca, r1 input MDMSPAR2, r1
|
||||
0235: 2201 btst 0, r1 btst 0, r1
|
||||
0236: 423c beq 0x023c beq LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR
|
||||
0237: 1090 mov r9, r0 mov r9, r0
|
||||
0238: 1a19 sub 1, r9 sub 1, r9
|
||||
0239: 1e09 cmp 0, r9 cmp 0, r9
|
||||
023a: 463c bne 0x023c bne LOOP_SAMPLES_FIFO_SYNC_DEMFRAC5WR
|
||||
023b: 10a9 mov r10, r9 mov r10, r9
|
||||
023c: 65d0 jsr 0x01d0 jsr MDMFIFOWR_AND_WAIT10
|
||||
023d: 8184 input 0x18, r4 input MDMCMDPAR1, r4
|
||||
023e: 1e04 cmp 0, r4 cmp 0, r4
|
||||
023f: 4224 beq 0x0224 beq LOOP_SAMPLES_FIFO_SYNC
|
||||
0240: 14bc add r11, r12 add r11, r12
|
||||
0241: 1c4c cmp r4, r12 cmp r4, r12
|
||||
0242: 4eb3 bpl 0x02b3 bpl MRX_GenFSK_CommonEnd
|
||||
0243: 6224 jmp 0x0224 jmp LOOP_SAMPLES_FIFO_SYNC
|
||||
0244: 8240 input 0x24, r0 input RFERCEV, r0
|
||||
0245: 2230 btst 3, r0 btst 3, r0
|
||||
0246: 464c bne 0x024c bne RFE_Started
|
||||
0247: b0d5 outbset 5, 0x0d outbset MCEEVENT0_RFECMD_IRQ, MCEEVENTMSK0
|
||||
0248: 7100 wait wait
|
||||
0249: b115 outbset 5, 0x11 outbset MCEEVENT0_RFECMD_IRQ, MCEEVENTCLR0
|
||||
024a: a0d5 outbclr 5, 0x0d outbclr MCEEVENT0_RFECMD_IRQ, MCEEVENTMSK0
|
||||
024b: 6244 jmp 0x0244 jmp MRX_SETUP
|
||||
024c: c100 lli 0x10, r0 lli "########################### RX Started ########################"
|
||||
024c: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
024e: b118 outbset 8, 0x11 outbset MCEEVENT0_CPEFWEVENT0, MCEEVENTCLR0
|
||||
024f: b006 outbset 6, 0x00 outbset MDMENABLE_ADCDIG, MDMENABLE
|
||||
0250: b016 outbset 6, 0x01 outbset MDMINIT_ADCDIG, MDMINIT
|
||||
0251: b004 outbset 4, 0x00 outbset MDMENABLE_DEMODULATOR, MDMENABLE
|
||||
0252: b014 outbset 4, 0x01 outbset MDMINIT_DEMODULATOR, MDMINIT
|
||||
0253: b002 outbset 2, 0x00 outbset MDMENABLE_TIMEBASE, MDMENABLE
|
||||
0254: b012 outbset 2, 0x01 outbset MDMINIT_TIMEBASE, MDMINIT
|
||||
0255: 8440 input 0x44, r0 input DEMC1BE0, r0
|
||||
0256: 7842 lmd 0x4, r2 lmd DEMC1BE0_MASKA_BITS, r2
|
||||
0257: 0420 and r2, r0 and r2, r0
|
||||
0258: 8173 input 0x17, r3 input MDMCMDPAR0, r3
|
||||
0259: 3983 sr0 8, r3 sr0 8, r3
|
||||
025a: 2a73 bclr 7, r3 bclr 7, r3
|
||||
025b: 94e3 output r3, 0x4e output r3, DEMSWQU0
|
||||
025c: c1f2 lli 0x1f, r2 lli 31, r2
|
||||
025d: 1832 sub r3, r2 sub r3, r2
|
||||
025e: 3162 sl0 6, r2 sl0 DEMC1BE0_MASKA, r2
|
||||
025f: 1021 mov r2, r1 mov r2, r1
|
||||
0260: 3151 sl0 5, r1 sl0 5, r1
|
||||
0261: 0012 or r1, r2 or r1, r2
|
||||
0262: 0020 or r2, r0 or r2, r0
|
||||
0263: 9440 output r0, 0x44 output r0, DEMC1BE0
|
||||
0264: 1030 mov r3, r0 mov r3, r0
|
||||
0265: 1610 add 1, r0 add 1,r0
|
||||
0266: 3930 sr0 3, r0 sr0 3,r0
|
||||
0267: 2210 btst 1, r0 btst 1, r0
|
||||
0268: 426a beq 0x026a beq GEN_FSK_AVG_LEN_CORRECT
|
||||
0269: 1220 mov 2, r0 mov 2, r0
|
||||
026a: 3150 sl0 5, r0 sl0 5,r0
|
||||
026b: 1003 mov r0, r3 mov r0, r3
|
||||
026c: 3180 sl0 8, r0 sl0 8, r0
|
||||
026d: 1630 add 3, r0 add 3,r0
|
||||
026e: 9380 output r0, 0x38 output r0, DEMDSBU
|
||||
026f: 1202 mov 0, r2 mov 0, r2
|
||||
0270: 1204 mov 0, r4 mov 0, r4
|
||||
0271: 2273 btst 7, r3 btst 7, r3
|
||||
0272: 427c beq 0x027c beq GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS_CHECK
|
||||
0273: 84a0 input 0x4a, r0 input MDMSYNC0, r0
|
||||
0274: 9970 output r0, 0x97 output r0, COUNT1IN
|
||||
0275: 8982 input 0x98, r2 input COUNT1RES, r2
|
||||
0276: 1a82 sub 8, r2 sub 8, r2
|
||||
0277: 84c0 input 0x4c, r0 input MDMSYNC2, r0
|
||||
0278: 9970 output r0, 0x97 output r0, COUNT1IN
|
||||
0279: 8984 input 0x98, r4 input COUNT1RES, r4
|
||||
027a: 1a84 sub 8, r4 sub 8, r4
|
||||
027b: 627e jmp 0x027e jmp GEN_FSK_DSBU_AVG_LEN_16_SYMBOLS
|
||||
027c: 2263 btst 6, r3 btst 6, r3
|
||||
027d: 4289 beq 0x0289 beq GEN_FSK_DSBU_AVG_LEN_8_SYMBOLS
|
||||
027e: 84b0 input 0x4b, r0 input MDMSYNC1, r0
|
||||
027f: 9970 output r0, 0x97 output r0, COUNT1IN
|
||||
0280: 8980 input 0x98, r0 input COUNT1RES, r0
|
||||
0281: 1a80 sub 8, r0 sub 8, r0
|
||||
0282: 1402 add r0, r2 add r0, r2
|
||||
0283: 84d0 input 0x4d, r0 input MDMSYNC3, r0
|
||||
0284: 9970 output r0, 0x97 output r0, COUNT1IN
|
||||
0285: 8980 input 0x98, r0 input COUNT1RES, r0
|
||||
0286: 1a80 sub 8, r0 sub 8, r0
|
||||
0287: 1404 add r0, r4 add r0, r4
|
||||
0288: 6295 jmp 0x0295 jmp GEN_FSK_CALC_DEMSWIMBAL
|
||||
0289: 84b0 input 0x4b, r0 input MDMSYNC1, r0
|
||||
028a: 7851 lmd 0x5, r1 lmd IQDUMP_MASK_BITS_15_8, r1
|
||||
028b: 0410 and r1, r0 and r1,r0
|
||||
028c: 9970 output r0, 0x97 output r0, COUNT1IN
|
||||
028d: 8982 input 0x98, r2 input COUNT1RES, r2
|
||||
028e: 1a42 sub 4, r2 sub 4, r2
|
||||
028f: 84d0 input 0x4d, r0 input MDMSYNC3, r0
|
||||
0290: 7851 lmd 0x5, r1 lmd IQDUMP_MASK_BITS_15_8, r1
|
||||
0291: 0410 and r1, r0 and r1,r0
|
||||
0292: 9970 output r0, 0x97 output r0, COUNT1IN
|
||||
0293: 8984 input 0x98, r4 input COUNT1RES, r4
|
||||
0294: 1a44 sub 4, r4 sub 4, r4
|
||||
0295: 3152 sl0 5, r2 sl0 5, r2
|
||||
0296: 3154 sl0 5, r4 sl0 5, r4
|
||||
0297: 3963 sr0 6, r3 sr0 6, r3
|
||||
0298: 0633 and 3, r3 and 3, r3
|
||||
0299: 1613 add 1, r3 add 1, r3
|
||||
029a: 3832 sr0 r3, r2 sr0 r3, r2
|
||||
029b: 3834 sr0 r3, r4 sr0 r3, r4
|
||||
029c: 3182 sl0 8, r2 sl0 8, r2
|
||||
029d: 3982 sr0 8, r2 sr0 8, r2
|
||||
029e: 3184 sl0 8, r4 sl0 8, r4
|
||||
029f: 0042 or r4, r2 or r4, r2
|
||||
02a0: 9722 output r2, 0x72 output r2, DEMSWIMBAL
|
||||
02a1: 84a0 input 0x4a, r0 input MDMSYNC0, r0
|
||||
02a2: 9590 output r0, 0x59 output r0, DEMC1BEREF0
|
||||
02a3: 84b0 input 0x4b, r0 input MDMSYNC1, r0
|
||||
02a4: 95a0 output r0, 0x5a output r0, DEMC1BEREF1
|
||||
02a5: 84c0 input 0x4c, r0 input MDMSYNC2, r0
|
||||
02a6: 95b0 output r0, 0x5b output r0, DEMC1BEREF2
|
||||
02a7: 84d0 input 0x4d, r0 input MDMSYNC3, r0
|
||||
02a8: 95c0 output r0, 0x5c output r0, DEMC1BEREF3
|
||||
02a9: 7810 lmd 0x1, r0 lmd DEMENABLE0_RX_IQDUMP, r0
|
||||
02aa: 9030 output r0, 0x03 output r0, DEMENABLE0
|
||||
02ab: 9050 output r0, 0x05 output r0, DEMINIT0
|
||||
02ac: 7820 lmd 0x2, r0 lmd DEMENABLE1_RX_IQDUMP, r0
|
||||
02ad: 9040 output r0, 0x04 output r0, DEMENABLE1
|
||||
02ae: 9060 output r0, 0x06 output r0, DEMINIT1
|
||||
02af: b235 outbset 5, 0x23 outbset 5, RFESEND
|
||||
02b0: cd90 lli 0xd9, r0 lli 0xD9, r0
|
||||
02b1: 9170 output r0, 0x17 output r0, MDMCMDPAR0
|
||||
02b2: 7000 rts rts
|
||||
02b3: a235 outbclr 5, 0x23 outbclr 5, RFESEND
|
||||
02b4: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
02b5: 7100 wait wait
|
||||
02b6: a0d2 outbclr 2, 0x0d outbclr MCEEVENT0_CLKEN_4BAUD, MCEEVENTMSK0
|
||||
02b7: b112 outbset 2, 0x11 outbset MCEEVENT0_CLKEN_4BAUD, MCEEVENTCLR0
|
||||
02b8: ba3c outbset 12, 0xa3 outbset RDCAPT0_DEMLQIE0, RDCAPT0
|
||||
02b9: 81b0 input 0x1b, r0 input MDMSTATUS, r0
|
||||
02ba: 8b54 input 0xb5, r4 input DEMLQIE0, r4
|
||||
02bb: 3924 sr0 2, r4 sr0 2, r4
|
||||
02bc: 3184 sl0 8, r4 sl0 8, r4
|
||||
02bd: 0004 or r0, r4 or r0,r4
|
||||
02be: 91b4 output r4, 0x1b output r4, MDMSTATUS
|
||||
02bf: c110 lli 0x11, r0 lli "All bits received, MCE Ending"
|
||||
02bf: 66d0 jsr 0x02d0 jsr _DBG_PRINT
|
||||
02c1: 7391 outset 0x91 outset TIMCTRL
|
||||
02c2: 7291 outclr 0x91 outclr TIMCTRL
|
||||
02c3: 66ca jsr 0x02ca jsr MODCTRL_CLR
|
||||
02c4: 7206 outclr 0x06 outclr MDMENABLE_ADCDIG, MDMENABLE
|
||||
02c5: 7202 outclr 0x02 outclr MDMENABLE_TIMEBASE, MDMENABLE
|
||||
02c6: 7204 outclr 0x04 outclr MDMENABLE_DEMODULATOR, MDMENABLE
|
||||
02c7: 7305 outset 0x05 outset DEMINIT0
|
||||
02c8: 7306 outset 0x06 outset DEMINIT1
|
||||
02c9: 607d jmp 0x007d jmp CMD_OK_END
|
||||
02ca: 8630 input 0x63, r0 input MODCTRL, r0
|
||||
02cb: c801 lli 0x80, r1 lli 0x80, r1
|
||||
02cc: 3151 sl0 5, r1 sl0 5, r1
|
||||
02cd: 0410 and r1, r0 and r1, r0
|
||||
02ce: 9630 output r0, 0x63 output r0, MODCTRL
|
||||
02cf: 7000 rts rts
|
||||
02d0: 9a00 output r0, 0xa0 output r0, MCETRCCMD
|
||||
02d0: 89f0 input 0x9f, r0 input MCETRCBUSY, r0
|
||||
02d0: 2200 btst 0, r0 btst 0, r0
|
||||
02d0: 46d1 bne 0x02d1 bne _DBG_PRINT_WAIT
|
||||
02d0: b9e0 outbset 0, 0x9e outbset MCETRCSEND_SEND, MCETRCSEND
|
||||
02d0: 7000 rts rts
|
||||
Loading…
Reference in New Issue