ols: Fix endianness problems in protocol.
This commit is contained in:
Bert Vermeulen
parent
e6e54bd253
commit
016e72f30e
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@ -415,17 +415,52 @@ static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
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return SR_OK;
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}
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static int set_trigger(const struct sr_dev_inst *sdi, int stage)
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{
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struct dev_context *devc;
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struct sr_serial_dev_inst *serial;
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uint8_t cmd, arg[4];
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devc = sdi->priv;
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serial = sdi->conn;
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cmd = CMD_SET_TRIGGER_MASK + stage * 4;
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arg[0] = devc->trigger_mask[stage] & 0xff;
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arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
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arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
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arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
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if (send_longcommand(serial, cmd, arg) != SR_OK)
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return SR_ERR;
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cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
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arg[0] = devc->trigger_value[stage] & 0xff;
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arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
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arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
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arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
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if (send_longcommand(serial, cmd, arg) != SR_OK)
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return SR_ERR;
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cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
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arg[0] = arg[1] = arg[3] = 0x00;
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arg[2] = stage;
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if (stage == devc->num_stages)
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/* Last stage, fire when this one matches. */
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arg[3] |= TRIGGER_START;
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if (send_longcommand(serial, cmd, arg) != SR_OK)
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return SR_ERR;
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return SR_OK;
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}
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static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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void *cb_data)
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{
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struct dev_context *devc;
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struct sr_serial_dev_inst *serial;
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uint32_t trigger_config[4];
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uint32_t data;
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uint16_t samplecount, readcount, delaycount;
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uint8_t changrp_mask;
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uint8_t changrp_mask, arg[4];
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int num_channels;
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int i;
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int ret, i;
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if (sdi->status != SR_ST_ACTIVE)
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return SR_ERR_DEV_CLOSED;
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@ -458,92 +493,61 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi,
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*/
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samplecount = MIN(devc->max_samples / num_channels, devc->limit_samples);
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readcount = samplecount / 4;
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if (samplecount % 4)
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/* Rather read too many samples than too few. */
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if (samplecount % 4 != 0)
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readcount++;
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memset(trigger_config, 0, 16);
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trigger_config[devc->num_stages] |= 0x08;
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if (devc->trigger_mask[0]) {
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/* Basic triggers. */
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if (devc->trigger_mask[0] != 0x00000000) {
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/* At least one probe has a trigger on it. */
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delaycount = readcount * (1 - devc->capture_ratio / 100.0);
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devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
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if (send_longcommand(serial, CMD_SET_TRIGGER_MASK_0,
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reverse32(devc->trigger_mask[0])) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_VALUE_0,
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reverse32(devc->trigger_value[0])) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_CONFIG_0,
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trigger_config[0]) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_MASK_1,
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reverse32(devc->trigger_mask[1])) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_VALUE_1,
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reverse32(devc->trigger_value[1])) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_CONFIG_1,
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trigger_config[1]) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_MASK_2,
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reverse32(devc->trigger_mask[2])) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_VALUE_2,
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reverse32(devc->trigger_value[2])) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_CONFIG_2,
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trigger_config[2]) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_MASK_3,
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reverse32(devc->trigger_mask[3])) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_VALUE_3,
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reverse32(devc->trigger_value[3])) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_CONFIG_3,
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trigger_config[3]) != SR_OK)
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return SR_ERR;
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for (i = 0; i <= devc->num_stages; i++) {
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sr_dbg("Setting stage %d trigger.", i);
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if ((ret = set_trigger(sdi, i)) != SR_OK)
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return ret;
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}
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} else {
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if (send_longcommand(serial, CMD_SET_TRIGGER_MASK_0,
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devc->trigger_mask[0]) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_VALUE_0,
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devc->trigger_value[0]) != SR_OK)
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return SR_ERR;
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if (send_longcommand(serial, CMD_SET_TRIGGER_CONFIG_0,
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0x00000008) != SR_OK)
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return SR_ERR;
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/* No triggers configured, force trigger on first stage. */
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sr_dbg("Forcing trigger at stage 0.");
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if ((ret = set_trigger(sdi, 0)) != SR_OK)
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return ret;
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delaycount = readcount;
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}
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/* Samplerate. */
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sr_info("Setting samplerate to %" PRIu64 "Hz (divider %u)",
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sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
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devc->cur_samplerate, devc->cur_samplerate_divider);
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if (send_longcommand(serial, CMD_SET_DIVIDER,
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reverse32(devc->cur_samplerate_divider)) != SR_OK)
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arg[0] = devc->cur_samplerate_divider & 0xff;
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arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
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arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
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arg[3] = 0x00;
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if (send_longcommand(serial, CMD_SET_DIVIDER, arg) != SR_OK)
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return SR_ERR;
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/* Send sample limit and pre/post-trigger capture ratio. */
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sr_info("Setting sample limit %d, trigger point at %d",
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sr_dbg("Setting sample limit %d, trigger point at %d",
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(readcount - 1) * 4, (delaycount - 1) * 4);
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data = ((readcount - 1) & 0xffff) << 16;
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data |= (delaycount - 1) & 0xffff;
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if (send_longcommand(serial, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
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arg[0] = ((readcount - 1) & 0xff);
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arg[1] = ((readcount - 1) & 0xff00) >> 8;
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arg[2] = ((delaycount - 1) & 0xff);
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arg[3] = ((delaycount - 1) & 0xff00) >> 8;
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if (send_longcommand(serial, CMD_CAPTURE_SIZE, arg) != SR_OK)
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return SR_ERR;
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/* Flag register. */
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sr_info("Setting demux %s, noise_filter %s, extpat %s, intpat %s",
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sr_dbg("Setting demux %s, noise_filter %s, extpat %s, intpat %s",
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devc->flag_reg & FLAG_DEMUX ? "on" : "off",
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devc->flag_reg & FLAG_FILTER ? "on": "off",
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devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
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devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off");
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/* 1 means "disable channel". */
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devc->flag_reg |= ~(changrp_mask << 2) & 0x3c;
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data = (devc->flag_reg << 24) | ((devc->flag_reg << 8) & 0xff0000);
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if (send_longcommand(serial, CMD_SET_FLAGS, data) != SR_OK)
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arg[0] = devc->flag_reg & 0xff;
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arg[1] = devc->flag_reg >> 8;
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arg[2] = arg[3] = 0x00;
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if (send_longcommand(serial, CMD_SET_FLAGS, arg) != SR_OK)
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return SR_ERR;
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/* Start acquisition on the device. */
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@ -37,16 +37,17 @@ SR_PRIV int send_shortcommand(struct sr_serial_dev_inst *serial,
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}
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SR_PRIV int send_longcommand(struct sr_serial_dev_inst *serial,
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uint8_t command, uint32_t data)
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uint8_t command, uint8_t *data)
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{
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char buf[5];
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sr_dbg("Sending cmd 0x%.2x data 0x%.8x.", command, data);
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sr_dbg("Sending cmd 0x%.2x data 0x%.2x%.2x%.2x%.2x.", command,
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data[0], data[1], data[2], data[3]);
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buf[0] = command;
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buf[1] = (data & 0xff000000) >> 24;
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buf[2] = (data & 0xff0000) >> 16;
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buf[3] = (data & 0xff00) >> 8;
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buf[4] = data & 0xff;
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buf[1] = data[0];
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buf[2] = data[1];
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buf[3] = data[2];
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buf[4] = data[3];
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if (serial_write_blocking(serial, buf, 5) != 5)
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return SR_ERR;
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@ -97,11 +98,8 @@ SR_PRIV int ols_configure_probes(const struct sr_dev_inst *sdi)
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if (*tc == '1')
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devc->trigger_value[stage] |= probe_bit;
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stage++;
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if (stage > 3)
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/*
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* TODO: Only supporting parallel mode, with
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* up to 4 stages.
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*/
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/* Only supporting parallel mode, with up to 4 stages. */
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if (stage > 4)
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return SR_ERR;
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}
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if (stage > devc->num_stages)
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@ -111,30 +109,6 @@ SR_PRIV int ols_configure_probes(const struct sr_dev_inst *sdi)
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return SR_OK;
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}
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SR_PRIV uint32_t reverse16(uint32_t in)
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{
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uint32_t out;
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out = (in & 0xff) << 8;
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out |= (in & 0xff00) >> 8;
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out |= (in & 0xff0000) << 8;
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out |= (in & 0xff000000) >> 8;
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return out;
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}
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SR_PRIV uint32_t reverse32(uint32_t in)
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{
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uint32_t out;
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out = (in & 0xff) << 24;
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out |= (in & 0xff00) << 8;
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out |= (in & 0xff0000) >> 8;
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out |= (in & 0xff000000) >> 24;
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return out;
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}
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SR_PRIV struct dev_context *ols_dev_new(void)
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{
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struct dev_context *devc;
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@ -218,7 +192,7 @@ SR_PRIV struct sr_dev_inst *get_metadata(struct sr_serial_dev_inst *serial)
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/* 32-bit unsigned integer */
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if (serial_read_blocking(serial, &tmp_int, 4) != 4)
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break;
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tmp_int = reverse32(tmp_int);
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tmp_int = RB32(&tmp_int);
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sr_dbg("Got metadata key 0x%.2x value 0x%.8x.",
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key, tmp_int);
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switch (token) {
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@ -45,32 +45,27 @@
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#define CMD_SET_FLAGS 0x82
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#define CMD_SET_DIVIDER 0x80
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#define CMD_CAPTURE_SIZE 0x81
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#define CMD_SET_TRIGGER_MASK_0 0xc0
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#define CMD_SET_TRIGGER_MASK_1 0xc4
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#define CMD_SET_TRIGGER_MASK_2 0xc8
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#define CMD_SET_TRIGGER_MASK_3 0xcc
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#define CMD_SET_TRIGGER_VALUE_0 0xc1
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#define CMD_SET_TRIGGER_VALUE_1 0xc5
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#define CMD_SET_TRIGGER_VALUE_2 0xc9
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#define CMD_SET_TRIGGER_VALUE_3 0xcd
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#define CMD_SET_TRIGGER_CONFIG_0 0xc2
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#define CMD_SET_TRIGGER_CONFIG_1 0xc6
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#define CMD_SET_TRIGGER_CONFIG_2 0xca
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#define CMD_SET_TRIGGER_CONFIG_3 0xce
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#define CMD_SET_TRIGGER_MASK 0xc0
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#define CMD_SET_TRIGGER_VALUE 0xc1
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#define CMD_SET_TRIGGER_CONFIG 0xc2
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/* Trigger config */
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#define TRIGGER_START (1 << 3)
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/* Bitmasks for CMD_FLAGS */
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#define FLAG_DEMUX 0x01
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#define FLAG_FILTER 0x02
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#define FLAG_CHANNELGROUP_1 0x04
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#define FLAG_CHANNELGROUP_2 0x08
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#define FLAG_CHANNELGROUP_3 0x10
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#define FLAG_CHANNELGROUP_4 0x20
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#define FLAG_CLOCK_EXTERNAL 0x40
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#define FLAG_CLOCK_INVERTED 0x80
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#define FLAG_RLE 0x0100
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#define FLAG_SWAP_PROBES 0x0200
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#define FLAG_EXTERNAL_TEST_MODE 0x0400
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#define FLAG_INTERNAL_TEST_MODE 0x0800
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/* 12-13 unused, 14-15 RLE mode (we hardcode mode 0). */
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#define FLAG_INTERNAL_TEST_MODE (1 << 11)
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#define FLAG_EXTERNAL_TEST_MODE (1 << 10)
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#define FLAG_SWAP_PROBES (1 << 9)
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#define FLAG_RLE (1 << 8)
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#define FLAG_SLOPE_FALLING (1 << 7)
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#define FLAG_CLOCK_EXTERNAL (1 << 6)
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#define FLAG_CHANNELGROUP_4 (1 << 5)
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#define FLAG_CHANNELGROUP_3 (1 << 4)
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#define FLAG_CHANNELGROUP_2 (1 << 3)
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#define FLAG_CHANNELGROUP_1 (1 << 2)
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#define FLAG_FILTER (1 << 1)
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#define FLAG_DEMUX (1 << 0)
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/* Private, per-device-instance driver context. */
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struct dev_context {
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@ -90,7 +85,7 @@ struct dev_context {
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uint32_t trigger_mask[4];
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uint32_t trigger_value[4];
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int num_stages;
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uint32_t flag_reg;
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uint16_t flag_reg;
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/* Operational states */
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unsigned int num_transfers;
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@ -110,10 +105,8 @@ SR_PRIV extern const char *ols_probe_names[NUM_PROBES + 1];
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SR_PRIV int send_shortcommand(struct sr_serial_dev_inst *serial,
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uint8_t command);
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SR_PRIV int send_longcommand(struct sr_serial_dev_inst *serial,
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uint8_t command, uint32_t data);
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uint8_t command, uint8_t *data);
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SR_PRIV int ols_configure_probes(const struct sr_dev_inst *sdi);
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SR_PRIV uint32_t reverse16(uint32_t in);
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SR_PRIV uint32_t reverse32(uint32_t in);
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SR_PRIV struct dev_context *ols_dev_new(void);
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SR_PRIV struct sr_dev_inst *get_metadata(struct sr_serial_dev_inst *serial);
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SR_PRIV int ols_set_samplerate(const struct sr_dev_inst *sdi,
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