BLAHAJ
/
libsigrok
10
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

dslogic: Added half and quater-mode flags

This commit is contained in:
Joel Holdsworth 2017-06-12 16:46:31 -06:00 committed by Uwe Hermann
parent 6c317a8d75
commit 780c5e2466
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/hardware/dslogic/dslogic.c
View File

@ -345,6 +345,12 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
v16 = DS_MODE_EXT_TEST;
else if (devc->mode == DS_OP_LOOPBACK_TEST)
v16 = DS_MODE_LPB_TEST;
if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
v16 |= DS_MODE_HALF_MODE;
else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
v16 |= DS_MODE_QUAR_MODE;
if (devc->continuous_mode)
v16 |= DS_MODE_STREAM_MODE;
if (devc->external_clock) {