dslogic: Added half and quater-mode flags

This commit is contained in:
Joel Holdsworth 2017-06-12 16:46:31 -06:00 提交者 Uwe Hermann
父節點 6c317a8d75
當前提交 780c5e2466
共有 1 個檔案被更改,包括 6 行新增0 行删除

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@ -345,6 +345,12 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
v16 = DS_MODE_EXT_TEST;
else if (devc->mode == DS_OP_LOOPBACK_TEST)
v16 = DS_MODE_LPB_TEST;
if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
v16 |= DS_MODE_HALF_MODE;
else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
v16 |= DS_MODE_QUAR_MODE;
if (devc->continuous_mode)
v16 |= DS_MODE_STREAM_MODE;
if (devc->external_clock) {