BLAHAJ
/
libsigrok
10
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

fx2lafw/dslogic: Various cosmetics and whitespace fixes.

This commit is contained in:
Uwe Hermann 2016-05-16 15:34:21 +02:00
parent a04b28ce2c
commit 9803346fe2
4 changed files with 91 additions and 79 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
src/hardware/fx2lafw/api.c
View File

@ -143,7 +143,7 @@ static const uint32_t dslogic_devopts[] = {
SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST
SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
};
static const int32_t soft_trigger_matches[] = {
@ -154,8 +154,7 @@ static const int32_t soft_trigger_matches[] = {
SR_TRIGGER_EDGE,
};
/* Names assigned to available edge slope choices.
*/
/* Names assigned to available edge slope choices. */
static const char *const signal_edge_names[] = {
[DS_EDGE_RISING] = "rising",
[DS_EDGE_FALLING] = "falling",
@ -166,8 +165,8 @@ static const struct {
gdouble low;
gdouble high;
} volt_thresholds[] = {
{ DS_VOLTAGE_RANGE_18_33_V, 0.7, 1.4 },
{ DS_VOLTAGE_RANGE_5_V, 1.4, 3.6 },
{ DS_VOLTAGE_RANGE_18_33_V, 0.7, 1.4 },
{ DS_VOLTAGE_RANGE_5_V, 1.4, 3.6 },
};
static const uint64_t samplerates[] = {
@ -516,6 +515,7 @@ static int dev_close(struct sr_dev_inst *sdi)
struct sr_usb_dev_inst *usb;
usb = sdi->conn;
if (!usb->devhdl)
return SR_ERR;
@ -529,8 +529,8 @@ static int dev_close(struct sr_dev_inst *sdi)
return SR_OK;
}
static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
const struct sr_channel_group *cg)
static int config_get(uint32_t key, GVariant **data,
const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
@ -586,7 +586,7 @@ static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *s
i = devc->dslogic_clock_edge;
if (i >= ARRAY_SIZE(signal_edge_names))
return SR_ERR_BUG;
*data = g_variant_new_string(signal_edge_names[0]);//idx]);
*data = g_variant_new_string(signal_edge_names[0]);
break;
default:
return SR_ERR_NA;
@ -595,8 +595,8 @@ static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *s
return SR_OK;
}
/* Helper for mapping a string-typed configuration value to an index
/*
* Helper for mapping a string-typed configuration value to an index
* within a table of possible values.
*/
static int lookup_index(GVariant *value, const char *const *table, int len)
@ -617,8 +617,8 @@ static int lookup_index(GVariant *value, const char *const *table, int len)
return -1;
}
static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
const struct sr_channel_group *cg)
static int config_set(uint32_t key, GVariant *data,
const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
struct dev_context *devc;
uint64_t arg;
@ -671,7 +671,7 @@ static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sd
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_5V);
else
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_3V3);
}else if (!strcmp(devc->profile->model, "DSLogic Pro")){
} else if (!strcmp(devc->profile->model, "DSLogic Pro")) {
ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PRO_FPGA_FIRMWARE);
}
break;
@ -695,8 +695,8 @@ static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sd
return ret;
}
static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
const struct sr_channel_group *cg)
static int config_list(uint32_t key, GVariant **data,
const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
struct dev_context *devc;
GVariant *gvar, *range[2];
@ -711,10 +711,10 @@ static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *
scanopts, ARRAY_SIZE(scanopts), sizeof(uint32_t));
break;
case SR_CONF_DEVICE_OPTIONS:
if (!sdi)
if (!sdi) {
*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
else{
drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
} else {
devc = sdi->priv;
if (!devc->dslogic)
*data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
@ -725,9 +725,11 @@ static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *
}
break;
case SR_CONF_VOLTAGE_THRESHOLD:
if (!sdi->priv) return SR_ERR_ARG;
if (!sdi->priv)
return SR_ERR_ARG;
devc = sdi->priv;
if (!devc->dslogic) return SR_ERR_NA;
if (!devc->dslogic)
return SR_ERR_NA;
g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
for (i = 0; i < ARRAY_SIZE(volt_thresholds); i++) {
range[0] = g_variant_new_double(volt_thresholds[i].low);
@ -813,8 +815,8 @@ static int start_transfers(const struct sr_dev_inst *sdi)
//if (devc->dslogic)
// num_transfers = dslogic_get_number_of_transfers(devc);
if ( devc->dslogic){
if(devc->cur_samplerate == SR_MHZ(100))
if (devc->dslogic) {
if (devc->cur_samplerate == SR_MHZ(100))
num_transfers = 16;
else if (devc->cur_samplerate == SR_MHZ(200))
num_transfers = 8;
@ -888,8 +890,9 @@ static void LIBUSB_CALL dslogic_trigger_receive(struct libusb_transfer *transfer
} else if (transfer->status == LIBUSB_TRANSFER_COMPLETED
&& transfer->actual_length == sizeof(struct dslogic_trigger_pos)) {
tpos = (struct dslogic_trigger_pos *)transfer->buffer;
sr_info("tpos real_pos %d ram_saddr %d cnt %d", tpos->real_pos, tpos->ram_saddr, tpos->remain_cnt);
devc->trigger_pos = tpos->real_pos;
sr_info("tpos real_pos %d ram_saddr %d cnt %d", tpos->real_pos,
tpos->ram_saddr, tpos->remain_cnt);
devc->trigger_pos = tpos->real_pos;
g_free(tpos);
start_transfers(sdi);
}
@ -913,11 +916,11 @@ static int dslogic_trigger_request(const struct sr_dev_inst *sdi)
if ((ret = dslogic_fpga_configure(sdi)) != SR_OK)
return ret;
/* if this is a dslogic pro, set the voltage threshold */
/* If this is a DSLogic Pro, set the voltage threshold. */
if (!strcmp(devc->profile->model, "DSLogic Pro")){
if(devc->dslogic_voltage_threshold == DS_VOLTAGE_RANGE_18_33_V){
if (devc->dslogic_voltage_threshold == DS_VOLTAGE_RANGE_18_33_V) {
dslogic_set_vth(sdi, 1.4);
}else{
} else {
dslogic_set_vth(sdi, 3.3);
}
}

79
src/hardware/fx2lafw/dslogic.c
View File

@ -39,15 +39,17 @@
SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
{
struct sr_usb_dev_inst *usb;
usb = sdi->conn;
int ret;
uint8_t cmd;
cmd = vth/5.0 * 255;
usb = sdi->conn;
cmd = (vth / 5.0) * 255;
/* Send the control command. */
ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
LIBUSB_ENDPOINT_OUT, DS_CMD_VTH, 0x0000, 0x0000,
(unsigned char *)&cmd, sizeof(cmd), 3000);
LIBUSB_ENDPOINT_OUT, DS_CMD_VTH, 0x0000, 0x0000,
(unsigned char *)&cmd, sizeof(cmd), 3000);
if (ret < 0) {
sr_err("Unable to send VTH command: %s.",
libusb_error_name(ret));
@ -186,13 +188,13 @@ static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
struct sr_trigger *trigger;
struct sr_trigger_stage *stage;
struct sr_trigger_match *match;
struct dev_context *devc;
devc = sdi->priv;
const GSList *l, *m;
int channelbit, i = 0;
uint16_t v16;
devc = sdi->priv;
cfg->trig_mask0[0] = 0xffff;
cfg->trig_mask1[0] = 0xffff;
@ -231,7 +233,7 @@ static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
sr_dbg("configuring trigger");
if (!(trigger = sr_session_trigger_get(sdi->session))){
if (!(trigger = sr_session_trigger_get(sdi->session))) {
sr_dbg("No session trigger found");
return SR_OK;
}
@ -265,19 +267,20 @@ static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
cfg->trig_value1[0] |= channelbit;
cfg->trig_edge0[0] |= channelbit;
cfg->trig_edge1[0] |= channelbit;
} else if(match->match == SR_TRIGGER_EDGE){
} else if (match->match == SR_TRIGGER_EDGE) {
cfg->trig_edge0[0] |= channelbit;
cfg->trig_edge1[0] |= channelbit;
}
}
}
v16 = RL16(&cfg->mode);
v16 |= 1 << 0;
WL16(&cfg->mode, v16);
return SR_OK;
}
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
@ -289,6 +292,7 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
int transferred, len, ret;
sr_dbg("Configuring FPGA.");
usb = sdi->conn;
devc = sdi->priv;
@ -322,7 +326,8 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
c, 3, USB_TIMEOUT);
if (ret < 0) {
sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
sr_err("Failed to send FPGA configure command: %s.",
libusb_error_name(ret));
return SR_ERR;
}
@ -338,9 +343,9 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
* 5 1 = samplerate 200MHz or analog mode
* 4 0 = logic, 1 = dso or analog
* 3 1 = RLE encoding (enable for more than 16 Megasamples)
* 1-2 00 = internal clock,
* 01 = external clock rising,
* 11 = external clock falling
* 1-2 00 = internal clock,
* 01 = external clock rising,
* 11 = external clock falling
* 0 1 = trigger enabled
*/
v16 = 0x0000;
@ -352,17 +357,18 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
v16 = 1 << 13;
if (devc->dslogic_continuous_mode)
v16 |= 1 << 12;
if (devc->dslogic_external_clock){
if (devc->dslogic_external_clock) {
v16 |= 1 << 1;
if (devc->dslogic_clock_edge == DS_EDGE_FALLING){
if (devc->dslogic_clock_edge == DS_EDGE_FALLING)
v16 |= 1 << 2;
}
}
if (devc->limit_samples > DS_MAX_LOGIC_DEPTH * ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
&& !devc->dslogic_continuous_mode){
/* enable rle for long captures.
Without this, captured data present errors. */
v16 |= 1<< 3;
if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
&& !devc->dslogic_continuous_mode) {
/* Enable RLE for long captures.
* Without this, captured data present errors.
*/
v16 |= 1 << 3;
}
WL16(&cfg.mode, v16);
@ -383,30 +389,33 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
return SR_OK;
}
static int to_bytes_per_ms(struct dev_context* devc){
static int to_bytes_per_ms(struct dev_context *devc)
{
if (devc->cur_samplerate > SR_MHZ(100))
return SR_MHZ(100) / 1000 * (devc->sample_wide ? 2 : 1);
return devc->cur_samplerate / 1000 * (devc->sample_wide ? 2 : 1);
return SR_MHZ(100) / 1000 * (devc->sample_wide ? 2 : 1);
return devc->cur_samplerate / 1000 * (devc->sample_wide ? 2 : 1);
}
static size_t get_buffer_size(struct dev_context *devc)
{
size_t s;
size_t s;
/*
* The buffer should be large enough to hold 10ms of data and
* a multiple of 512.
*/
s = 10 * to_bytes_per_ms(devc);
//s = to_bytes_per_ms(devc->cur_samplerate);
return (s + 511) & ~511;
/*
* The buffer should be large enough to hold 10ms of data and
* a multiple of 512.
*/
s = 10 * to_bytes_per_ms(devc);
// s = to_bytes_per_ms(devc->cur_samplerate);
return (s + 511) & ~511;
}
SR_PRIV int dslogic_get_number_of_transfers(struct dev_context* devc){
SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
{
unsigned int n;
/* Total buffer size should be able to hold about 100ms of data. */
n = (100 * to_bytes_per_ms(devc) /
get_buffer_size(devc));
n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
sr_info("New calculation: %d", n);
if (n > NUM_SIMUL_TRANSFERS)

18
src/hardware/fx2lafw/dslogic.h
View File

@ -27,7 +27,7 @@
#define DS_CMD_START 0xb2
#define DS_CMD_FPGA_FW 0xb3
#define DS_CMD_CONFIG 0xb4
#define DS_CMD_VTH 0xb8
#define DS_CMD_VTH 0xb8
#define DS_NUM_TRIGGER_STAGES 16
#define DS_START_FLAGS_STOP (1 << 7)
@ -35,8 +35,8 @@
#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
#define DS_START_FLAGS_MODE_LA (1 << 4)
#define DS_MAX_LOGIC_DEPTH SR_MHZ(16)
#define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100)
#define DS_MAX_LOGIC_DEPTH SR_MHZ(16)
#define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100)
enum dslogic_operation_modes {
DS_OP_NORMAL,
@ -45,14 +45,14 @@ enum dslogic_operation_modes {
DS_OP_LOOPBACK_TEST,
};
enum {
DS_VOLTAGE_RANGE_18_33_V, /* 1.8V and 3.3V logic */
DS_VOLTAGE_RANGE_5_V, /* 5V logic */
enum {
DS_VOLTAGE_RANGE_18_33_V, /* 1.8V and 3.3V logic */
DS_VOLTAGE_RANGE_5_V, /* 5V logic */
};
enum{
enum {
DS_EDGE_RISING,
DS_EDGE_FALLING
DS_EDGE_FALLING,
};
struct dslogic_version {
@ -145,6 +145,6 @@ SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
SR_PRIV int dslogic_get_number_of_transfers(struct dev_context* devc);
SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);
#endif

16
src/hardware/fx2lafw/protocol.c
View File

@ -517,25 +517,25 @@ SR_PRIV void LIBUSB_CALL fx2lafw_receive_transfer(struct libusb_transfer *transf
else
num_samples = cur_sample_count;
if(devc->dslogic && devc->trigger_pos > devc->sent_samples
&& devc->trigger_pos <= devc->sent_samples + num_samples){
/* dslogic trigger in this block. Send trigger position */
if (devc->dslogic && devc->trigger_pos > devc->sent_samples
&& devc->trigger_pos <= devc->sent_samples + num_samples) {
/* DSLogic trigger in this block. Send trigger position. */
trigger_offset = devc->trigger_pos - devc->sent_samples;
/* pre-trigger samples */
/* Pre-trigger samples. */
devc->send_data_proc(sdi, (uint8_t *)transfer->buffer,
trigger_offset * unitsize, unitsize);
devc->sent_samples += trigger_offset;
/* trigger position */
/* Trigger position. */
devc->trigger_pos = 0;
packet.type = SR_DF_TRIGGER;
packet.payload = NULL;
sr_session_send(sdi, &packet);
/* post trigger samples */
/* Post trigger samples. */
num_samples -= trigger_offset;
devc->send_data_proc(sdi, (uint8_t *)transfer->buffer
+ trigger_offset * unitsize, num_samples * unitsize, unitsize);
+ trigger_offset * unitsize, num_samples * unitsize, unitsize);
devc->sent_samples += num_samples;
}else{
} else {
devc->send_data_proc(sdi, (uint8_t *)transfer->buffer,
num_samples * unitsize, unitsize);
devc->sent_samples += num_samples;