BLAHAJ
/
libsigrok
10
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

dslogic: Fix sampling for high samplerates. 

This patch fixes sampling at 100MHz, 200MHz and 400MHz.

Signed-off-by: Diego Asanza <f.asanza@gmail.com>
This commit is contained in:
Diego Asanza 2016-05-08 19:13:12 +02:00 committed by Uwe Hermann
parent a9a9bfaa6a
commit a04b28ce2c
3 changed files with 52 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/hardware/fx2lafw/api.c
View File

@ -809,6 +809,19 @@ static int start_transfers(const struct sr_dev_inst *sdi)
devc->trigger_fired = TRUE;
num_transfers = fx2lafw_get_number_of_transfers(devc);
//if (devc->dslogic)
// num_transfers = dslogic_get_number_of_transfers(devc);
if ( devc->dslogic){
if(devc->cur_samplerate == SR_MHZ(100))
num_transfers = 16;
else if (devc->cur_samplerate == SR_MHZ(200))
num_transfers = 8;
else if (devc->cur_samplerate == SR_MHZ(400))
num_transfers = 4;
}
size = fx2lafw_get_buffer_size(devc);
devc->submitted_transfers = 0;
@ -830,6 +843,7 @@ static int start_transfers(const struct sr_dev_inst *sdi)
libusb_fill_bulk_transfer(transfer, usb->devhdl,
endpoint | LIBUSB_ENDPOINT_IN, buf, size,
fx2lafw_receive_transfer, (void *)sdi, timeout);
sr_info("submitting transfer: %d", i);
if ((ret = libusb_submit_transfer(transfer)) != 0) {
sr_err("Failed to submit transfer: %s.",
libusb_error_name(ret));

37
src/hardware/fx2lafw/dslogic.c
View File

@ -358,14 +358,15 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
v16 |= 1 << 2;
}
}
if (devc->limit_samples > DS_MAX_LOGIC_DEPTH && !devc->dslogic_continuous_mode){
if (devc->limit_samples > DS_MAX_LOGIC_DEPTH * ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
&& !devc->dslogic_continuous_mode){
/* enable rle for long captures.
Without this, captured data present errors. */
v16 |= 1<< 3;
}
WL16(&cfg.mode, v16);
v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
WL32(&cfg.divider, v32);
WL32(&cfg.count, devc->limit_samples);
@ -381,3 +382,35 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
return SR_OK;
}
static int to_bytes_per_ms(struct dev_context* devc){
if (devc->cur_samplerate > SR_MHZ(100))
return SR_MHZ(100) / 1000 * (devc->sample_wide ? 2 : 1);
return devc->cur_samplerate / 1000 * (devc->sample_wide ? 2 : 1);
}
static size_t get_buffer_size(struct dev_context *devc)
{
size_t s;
/*
* The buffer should be large enough to hold 10ms of data and
* a multiple of 512.
*/
s = 10 * to_bytes_per_ms(devc);
//s = to_bytes_per_ms(devc->cur_samplerate);
return (s + 511) & ~511;
}
SR_PRIV int dslogic_get_number_of_transfers(struct dev_context* devc){
unsigned int n;
/* Total buffer size should be able to hold about 100ms of data. */
n = (100 * to_bytes_per_ms(devc) /
get_buffer_size(devc));
sr_info("New calculation: %d", n);
if (n > NUM_SIMUL_TRANSFERS)
return NUM_SIMUL_TRANSFERS;
return n;
}

5
src/hardware/fx2lafw/dslogic.h
View File

@ -35,8 +35,8 @@
#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
#define DS_START_FLAGS_MODE_LA (1 << 4)
/* enable rle to capture more samples than this limit */
#define DS_MAX_LOGIC_DEPTH 16000000
#define DS_MAX_LOGIC_DEPTH SR_MHZ(16)
#define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100)
enum dslogic_operation_modes {
DS_OP_NORMAL,
@ -145,5 +145,6 @@ SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
SR_PRIV int dslogic_get_number_of_transfers(struct dev_context* devc);
#endif