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fx2lafw/dslogic: Imported FPGA config mode flags

This commit is contained in:
Joel Holdsworth 2017-06-09 17:29:08 -06:00 committed by Uwe Hermann
parent cd189a44f8
commit cf398cc058
2 changed files with 23 additions and 24 deletions
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31
src/hardware/fx2lafw/dslogic.c
View File

@ -330,36 +330,19 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
return SR_ERR;
}
/*
* 15 1 = internal test mode
* 14 1 = external test mode
* 13 1 = loopback test mode
* 12 1 = stream mode
* 11 1 = serial trigger
* 8-10 unused
* 7 1 = analog mode
* 6 1 = samplerate 400MHz
* 5 1 = samplerate 200MHz or analog mode
* 4 0 = logic, 1 = dso or analog
* 3 1 = RLE encoding (enable for more than 16 Megasamples)
* 1-2 00 = internal clock,
* 01 = external clock rising,
* 11 = external clock falling
* 0 1 = trigger enabled
*/
v16 = 0x0000;
if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
v16 = 1 << 15;
v16 = DS_MODE_INT_TEST;
else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
v16 = 1 << 14;
v16 = DS_MODE_EXT_TEST;
else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
v16 = 1 << 13;
v16 = DS_MODE_LPB_TEST;
if (devc->dslogic_continuous_mode)
v16 |= 1 << 12;
v16 |= DS_MODE_STREAM_MODE;
if (devc->dslogic_external_clock) {
v16 |= 1 << 1;
v16 |= DS_MODE_CLK_TYPE;
if (devc->dslogic_clock_edge == DS_EDGE_FALLING)
v16 |= 1 << 2;
v16 |= DS_MODE_CLK_EDGE;
}
if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
@ -367,7 +350,7 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
/* Enable RLE for long captures.
* Without this, captured data present errors.
*/
v16 |= 1 << 3;
v16 |= DS_MODE_RLE_MODE;
}
WL16(&cfg.mode, v16);

16
src/hardware/fx2lafw/dslogic.h
View File

@ -49,6 +49,22 @@
#define DS_MAX_LOGIC_DEPTH SR_MHZ(16)
#define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100)
#define DS_MODE_TRIG_EN (1 << 0)
#define DS_MODE_CLK_TYPE (1 << 1)
#define DS_MODE_CLK_EDGE (1 << 2)
#define DS_MODE_RLE_MODE (1 << 3)
#define DS_MODE_DSO_MODE (1 << 4)
#define DS_MODE_HALF_MODE (1 << 5)
#define DS_MODE_QUAR_MODE (1 << 6)
#define DS_MODE_ANALOG_MODE (1 << 7)
#define DS_MODE_FILTER (1 << 8)
#define DS_MODE_INSTANT (1 << 9)
#define DS_MODE_STRIG_MODE (1 << 11)
#define DS_MODE_STREAM_MODE (1 << 12)
#define DS_MODE_LPB_TEST (1 << 13)
#define DS_MODE_EXT_TEST (1 << 14)
#define DS_MODE_INT_TEST (1 << 15)
enum dslogic_operation_modes {
DS_OP_NORMAL,
DS_OP_INTERNAL_TEST,