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fx2lafw/dslogic: Updated dslogic_fpga_config structure to reflect v0.97 firmware

This commit is contained in:
Joel Holdsworth 2017-06-09 17:33:46 -06:00 committed by Uwe Hermann
parent cf398cc058
commit e40ee26b45
2 changed files with 37 additions and 62 deletions
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42
src/hardware/fx2lafw/dslogic.c
View File

@ -194,6 +194,12 @@ static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
devc = sdi->priv; devc = sdi->priv;
cfg->ch_en = 0;
for (l = sdi->channels; l; l = l->next) {
const struct sr_channel *const probe = (struct sr_channel *)l->data;
cfg->ch_en |= probe->enabled << probe->index;
}
cfg->trig_mask0[0] = 0xffff; cfg->trig_mask0[0] = 0xffff;
cfg->trig_mask1[0] = 0xffff; cfg->trig_mask1[0] = 0xffff;
@ -206,25 +212,20 @@ static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
cfg->trig_logic0[0] = 0; cfg->trig_logic0[0] = 0;
cfg->trig_logic1[0] = 0; cfg->trig_logic1[0] = 0;
cfg->trig_count0[0] = 0; cfg->trig_count[0] = 0;
cfg->trig_count1[0] = 0;
cfg->trig_pos = 0;
cfg->trig_sda = 0;
cfg->trig_glb = 0; cfg->trig_glb = 0;
cfg->trig_adp = cfg->count - cfg->trig_pos - 1;
for (i = 1; i < 16; i++) { for (i = 1; i < DS_NUM_TRIGGER_STAGES; i++) {
cfg->trig_mask0[i] = 0xff; cfg->trig_mask0[i] = 0xff;
cfg->trig_mask1[i] = 0xff; cfg->trig_mask1[i] = 0xff;
cfg->trig_value0[i] = 0; cfg->trig_value0[i] = 0;
cfg->trig_value1[i] = 0; cfg->trig_value1[i] = 0;
cfg->trig_edge0[i] = 0; cfg->trig_edge0[i] = 0;
cfg->trig_edge1[i] = 0; cfg->trig_edge1[i] = 0;
cfg->trig_count0[i] = 0;
cfg->trig_count1[i] = 0;
cfg->trig_logic0[i] = 2; cfg->trig_logic0[i] = 2;
cfg->trig_logic1[i] = 2; cfg->trig_logic1[i] = 2;
cfg->trig_count[i] = 0;
} }
cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples); cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
@ -297,22 +298,12 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
WL32(&cfg.sync, DS_CFG_START); WL32(&cfg.sync, DS_CFG_START);
WL16(&cfg.mode_header, DS_CFG_MODE); WL16(&cfg.mode_header, DS_CFG_MODE);
WL32(&cfg.divider_header, DS_CFG_DIVIDER); WL16(&cfg.divider_header, DS_CFG_DIVIDER);
WL32(&cfg.count_header, DS_CFG_COUNT); WL16(&cfg.count_header, DS_CFG_COUNT);
WL32(&cfg.trig_pos_header, DS_CFG_TRIG_POS); WL16(&cfg.trig_pos_header, DS_CFG_TRIG_POS);
WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB); WL16(&cfg.trig_glb_header, DS_CFG_TRIG_GLB);
WL32(&cfg.trig_adp_header, DS_CFG_TRIG_ADP); WL16(&cfg.ch_en_header, DS_CFG_CH_EN);
WL32(&cfg.trig_sda_header, DS_CFG_TRIG_SDA); WL16(&cfg.trig_header, DS_CFG_TRIG);
WL32(&cfg.trig_mask0_header, DS_CFG_TRIG_MASK0);
WL32(&cfg.trig_mask1_header, DS_CFG_TRIG_MASK1);
WL32(&cfg.trig_value0_header, DS_CFG_TRIG_VALUE0);
WL32(&cfg.trig_value1_header, DS_CFG_TRIG_VALUE1);
WL32(&cfg.trig_edge0_header, DS_CFG_TRIG_EDGE0);
WL32(&cfg.trig_edge1_header, DS_CFG_TRIG_EDGE1);
WL32(&cfg.trig_count0_header, DS_CFG_TRIG_COUNT0);
WL32(&cfg.trig_count1_header, DS_CFG_TRIG_COUNT1);
WL32(&cfg.trig_logic0_header, DS_CFG_TRIG_LOGIC0);
WL32(&cfg.trig_logic1_header, DS_CFG_TRIG_LOGIC1);
WL32(&cfg.end_sync, DS_CFG_END); WL32(&cfg.end_sync, DS_CFG_END);
/* Pass in the length of a fixed-size struct. Really. */ /* Pass in the length of a fixed-size struct. Really. */
@ -322,8 +313,8 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
c[2] = (len >> 16) & 0xff; c[2] = (len >> 16) & 0xff;
ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000, LIBUSB_ENDPOINT_OUT, DS_CMD_SETTING, 0x0000, 0x0000,
c, 3, USB_TIMEOUT); c, sizeof(c), USB_TIMEOUT);
if (ret < 0) { if (ret < 0) {
sr_err("Failed to send FPGA configure command: %s.", sr_err("Failed to send FPGA configure command: %s.",
libusb_error_name(ret)); libusb_error_name(ret));
@ -331,6 +322,7 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
} }
v16 = 0x0000; v16 = 0x0000;
if (devc->dslogic_mode == DS_OP_INTERNAL_TEST) if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
v16 = DS_MODE_INT_TEST; v16 = DS_MODE_INT_TEST;
else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST) else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)

57
src/hardware/fx2lafw/dslogic.h
View File

@ -102,70 +102,53 @@ struct dslogic_trigger_pos {
/* /*
* The FPGA is configured with TLV tuples. Length is specified as the * The FPGA is configured with TLV tuples. Length is specified as the
* number of 16-bit words, and the (type, length) header is in some * number of 16-bit words.
* cases padded with 0xffff.
*/ */
#define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt) #define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
#define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff)
#define DS_CFG_START 0xf5a5f5a5 #define DS_CFG_START 0xf5a5f5a5
#define DS_CFG_MODE _DS_CFG(0, 1) #define DS_CFG_MODE _DS_CFG(0, 1)
#define DS_CFG_DIVIDER _DS_CFG_PAD(1, 2) #define DS_CFG_DIVIDER _DS_CFG(1, 2)
#define DS_CFG_COUNT _DS_CFG_PAD(3, 2) #define DS_CFG_COUNT _DS_CFG(3, 2)
#define DS_CFG_TRIG_POS _DS_CFG_PAD(5, 2) #define DS_CFG_TRIG_POS _DS_CFG(5, 2)
#define DS_CFG_TRIG_GLB _DS_CFG(7, 1) #define DS_CFG_TRIG_GLB _DS_CFG(7, 1)
#define DS_CFG_TRIG_ADP _DS_CFG_PAD(10, 2) #define DS_CFG_CH_EN _DS_CFG(8, 1)
#define DS_CFG_TRIG_SDA _DS_CFG_PAD(12, 2) #define DS_CFG_TRIG _DS_CFG(64, 160)
#define DS_CFG_TRIG_MASK0 _DS_CFG_PAD(16, 16)
#define DS_CFG_TRIG_MASK1 _DS_CFG_PAD(17, 16)
#define DS_CFG_TRIG_VALUE0 _DS_CFG_PAD(20, 16)
#define DS_CFG_TRIG_VALUE1 _DS_CFG_PAD(21, 16)
#define DS_CFG_TRIG_EDGE0 _DS_CFG_PAD(24, 16)
#define DS_CFG_TRIG_EDGE1 _DS_CFG_PAD(25, 16)
#define DS_CFG_TRIG_COUNT0 _DS_CFG_PAD(28, 16)
#define DS_CFG_TRIG_COUNT1 _DS_CFG_PAD(29, 16)
#define DS_CFG_TRIG_LOGIC0 _DS_CFG_PAD(32, 16)
#define DS_CFG_TRIG_LOGIC1 _DS_CFG_PAD(33, 16)
#define DS_CFG_END 0xfa5afa5a #define DS_CFG_END 0xfa5afa5a
#pragma pack(push, 1)
struct dslogic_fpga_config { struct dslogic_fpga_config {
uint32_t sync; uint32_t sync;
uint16_t mode_header; uint16_t mode_header;
uint16_t mode; uint16_t mode;
uint32_t divider_header; uint16_t divider_header;
uint32_t divider; uint32_t divider;
uint32_t count_header; uint16_t count_header;
uint32_t count; uint32_t count;
uint32_t trig_pos_header; uint16_t trig_pos_header;
uint32_t trig_pos; uint32_t trig_pos;
uint16_t trig_glb_header; uint16_t trig_glb_header;
uint16_t trig_glb; uint16_t trig_glb;
uint32_t trig_adp_header; uint16_t ch_en_header;
uint32_t trig_adp; uint16_t ch_en;
uint32_t trig_sda_header;
uint32_t trig_sda; uint16_t trig_header;
uint32_t trig_mask0_header;
uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES]; uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES];
uint32_t trig_mask1_header;
uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES]; uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES];
uint32_t trig_value0_header;
uint16_t trig_value0[DS_NUM_TRIGGER_STAGES]; uint16_t trig_value0[DS_NUM_TRIGGER_STAGES];
uint32_t trig_value1_header;
uint16_t trig_value1[DS_NUM_TRIGGER_STAGES]; uint16_t trig_value1[DS_NUM_TRIGGER_STAGES];
uint32_t trig_edge0_header;
uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES]; uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES];
uint32_t trig_edge1_header;
uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES]; uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES];
uint32_t trig_count0_header;
uint16_t trig_count0[DS_NUM_TRIGGER_STAGES];
uint32_t trig_count1_header;
uint16_t trig_count1[DS_NUM_TRIGGER_STAGES];
uint32_t trig_logic0_header;
uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES]; uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES];
uint32_t trig_logic1_header;
uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES]; uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES];
uint32_t trig_count[DS_NUM_TRIGGER_STAGES];
uint32_t end_sync; uint32_t end_sync;
}; };
#pragma pack(pop)
SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi, SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
const char *name); const char *name);
SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi); SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);