For demux mode we half the channels. Previous check method broke
the OLS randomly and but it in a bad state.
Signed-off-by: Matt Ranostay <mranostay@gmail.com>
demux mode allows DDR sampling which disables group 2 & 3
and thus samples group 0 & 1 to sample on rising and falling of
the clock.
Signed-off-by: Matt Ranostay <mranostay@gmail.com>
The high bit of the sample, denoting this is a count, was not getting
properly cleared. This resulted in an inevitably negative count, and
corruption of the sample buffer before it was transferred to the
frontend.
Stage count was always getting incremented one more than
actual stages, and this caused a extra stage with zero'ed data
probe lines to have the start bit field.
Signed-off-by: Matt Ranostay <mranostay@gmail.com>
Matt Ranostay
Bert Vermeulen
Uwe Hermann