2007-12-01 03:42:52 +00:00
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/*
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2011-09-30 18:15:37 +00:00
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* This program source code file is part of KiCad, a free EDA CAD application.
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2007-12-01 03:42:52 +00:00
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*
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2019-01-26 12:01:48 +00:00
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* Copyright (C) 2004-2019 Jean-Pierre Charras, jp.charras at wanadoo.fr
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2014-08-13 15:47:02 +00:00
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* Copyright (C) 2014 Dick Hollenbeck, dick@softplc.com
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2020-02-24 23:17:30 +00:00
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* Copyright (C) 2017-2020 KiCad Developers, see change_log.txt for contributors.
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2007-12-01 03:42:52 +00:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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2012-01-23 04:33:36 +00:00
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#include <fctsys.h>
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2018-01-29 20:58:58 +00:00
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#include <pcb_edit_frame.h>
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2012-01-23 04:33:36 +00:00
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#include <trigo.h>
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2018-02-02 20:57:12 +00:00
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#include <board_design_settings.h>
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2018-08-27 13:50:50 +00:00
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#include <class_edge_mod.h>
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#include <class_drawsegment.h>
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2012-01-23 04:33:36 +00:00
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#include <class_module.h>
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#include <class_track.h>
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#include <class_pad.h>
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#include <class_zone.h>
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2014-08-13 15:47:02 +00:00
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#include <class_pcb_text.h>
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#include <geometry/seg.h>
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2017-12-08 10:25:13 +00:00
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#include <math_for_graphics.h>
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2018-10-12 06:17:15 +00:00
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#include <connectivity/connectivity_algo.h>
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2019-06-03 13:49:17 +00:00
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#include <bitmaps.h>
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2016-01-20 14:22:09 +00:00
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#include <tool/tool_manager.h>
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2017-02-21 12:42:08 +00:00
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#include <tools/pcb_actions.h>
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2019-06-03 13:49:17 +00:00
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#include <tools/pcb_tool_base.h>
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2020-05-17 14:40:06 +00:00
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#include <tools/zone_filler_tool.h>
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2019-03-28 19:30:51 +00:00
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#include <kiface_i.h>
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2012-01-23 04:33:36 +00:00
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#include <pcbnew.h>
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2019-11-17 12:58:38 +00:00
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#include <netlist_reader/pcb_netlist.h>
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2020-01-07 17:12:59 +00:00
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#include <math/util.h> // for KiROUND
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2012-01-23 04:33:36 +00:00
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#include <dialog_drc.h>
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2013-03-20 14:50:12 +00:00
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#include <wx/progdlg.h>
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2017-03-03 15:04:58 +00:00
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#include <board_commit.h>
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2020-07-04 18:48:22 +00:00
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#include <geometry/shape_segment.h>
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2018-08-27 13:50:50 +00:00
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#include <geometry/shape_arc.h>
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2020-05-24 14:54:26 +00:00
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#include <drc/drc.h>
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2020-05-18 00:20:16 +00:00
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#include <drc/drc_rule_parser.h>
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2020-03-16 11:05:01 +00:00
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#include <drc/drc_item.h>
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2020-05-01 17:44:25 +00:00
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#include <drc/drc_courtyard_tester.h>
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2020-05-17 14:40:06 +00:00
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#include <drc/drc_drilled_hole_tester.h>
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2020-05-18 00:20:16 +00:00
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#include <drc/drc_keepout_tester.h>
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#include <drc/drc_textvar_tester.h>
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2020-05-29 20:23:08 +00:00
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#include <drc/footprint_tester.h>
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2020-05-24 14:54:26 +00:00
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#include <dialogs/panel_setup_rules.h>
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2020-07-30 11:24:29 +00:00
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#include <reporter.h>
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2020-07-04 18:48:22 +00:00
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2019-06-03 13:49:17 +00:00
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DRC::DRC() :
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2020-01-13 19:46:39 +00:00
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PCB_TOOL_BASE( "pcbnew.DRCTool" ),
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2020-05-24 14:54:26 +00:00
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m_editFrame( nullptr ),
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2020-01-13 19:46:39 +00:00
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m_pcb( nullptr ),
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2020-05-18 20:09:36 +00:00
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m_board_outline_valid( false ),
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2020-05-16 19:12:56 +00:00
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m_drcDialog( nullptr ),
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2020-05-18 16:11:57 +00:00
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m_largestClearance( 0 )
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2019-06-03 13:49:17 +00:00
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{
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// establish initial values for everything:
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m_doUnconnectedTest = true; // enable unconnected tests
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2020-05-29 20:23:08 +00:00
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m_testTracksAgainstZones = false; // disable zone to items clearance tests
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2019-06-03 13:49:17 +00:00
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m_doKeepoutTest = true; // enable keepout areas to items clearance tests
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m_refillZones = false; // Only fill zones if requested by user.
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m_reportAllTrackErrors = false;
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m_testFootprints = false;
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m_drcRun = false;
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m_footprintsTested = false;
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}
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DRC::~DRC()
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{
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for( DRC_ITEM* unconnectedItem : m_unconnected )
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delete unconnectedItem;
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for( DRC_ITEM* footprintItem : m_footprints )
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delete footprintItem;
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}
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void DRC::Reset( RESET_REASON aReason )
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{
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2020-05-24 14:54:26 +00:00
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m_editFrame = getEditFrame<PCB_EDIT_FRAME>();
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2019-06-03 13:49:17 +00:00
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2020-05-24 14:54:26 +00:00
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if( m_pcb != m_editFrame->GetBoard() )
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2019-06-03 13:49:17 +00:00
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{
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if( m_drcDialog )
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DestroyDRCDialog( wxID_OK );
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2020-05-24 14:54:26 +00:00
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m_pcb = m_editFrame->GetBoard();
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2019-06-03 13:49:17 +00:00
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}
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}
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2016-07-28 12:07:35 +00:00
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void DRC::ShowDRCDialog( wxWindow* aParent )
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2007-12-01 03:42:52 +00:00
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{
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2016-07-28 12:07:35 +00:00
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bool show_dlg_modal = true;
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// the dialog needs a parent frame. if it is not specified, this is
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// the PCB editor frame specified in DRC class.
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2019-06-03 13:49:17 +00:00
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if( !aParent )
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2016-07-28 12:07:35 +00:00
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{
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// if any parent is specified, the dialog is modal.
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// if this is the default PCB editor frame, it is not modal
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show_dlg_modal = false;
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2020-05-24 14:54:26 +00:00
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aParent = m_editFrame;
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2016-07-28 12:07:35 +00:00
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}
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2019-06-03 13:49:17 +00:00
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Activate();
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m_toolMgr->RunAction( PCB_ACTIONS::selectionClear, true );
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2018-03-15 23:01:17 +00:00
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2016-04-15 18:15:22 +00:00
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if( !m_drcDialog )
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2007-12-01 03:42:52 +00:00
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{
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2020-05-24 14:54:26 +00:00
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m_drcDialog = new DIALOG_DRC( this, m_editFrame, aParent );
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2007-12-04 18:23:38 +00:00
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updatePointers();
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2008-02-09 08:34:45 +00:00
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2016-07-28 12:07:35 +00:00
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if( show_dlg_modal )
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m_drcDialog->ShowModal();
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else
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m_drcDialog->Show( true );
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2007-12-04 18:23:38 +00:00
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}
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2016-07-28 12:07:35 +00:00
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else // The dialog is just not visible (because the user has double clicked on an error item)
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{
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2007-12-04 18:23:38 +00:00
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updatePointers();
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2016-07-28 12:07:35 +00:00
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m_drcDialog->Show( true );
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}
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2007-12-01 03:42:52 +00:00
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}
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2017-12-08 10:25:13 +00:00
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2019-06-03 13:49:17 +00:00
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int DRC::ShowDRCDialog( const TOOL_EVENT& aEvent )
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{
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ShowDRCDialog( nullptr );
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return 0;
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}
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2020-03-08 15:55:14 +00:00
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bool DRC::IsDRCDialogShown()
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{
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if( m_drcDialog )
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return m_drcDialog->IsShown();
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return false;
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}
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2020-05-18 00:20:16 +00:00
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void DRC::addMarkerToPcb( BOARD_COMMIT& aCommit, MARKER_PCB* aMarker )
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2017-03-03 15:04:58 +00:00
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{
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2020-05-04 19:08:42 +00:00
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if( m_pcb->GetDesignSettings().Ignore( aMarker->GetRCItem()->GetErrorCode() ) )
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{
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delete aMarker;
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return;
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}
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2020-05-18 00:20:16 +00:00
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aCommit.Add( aMarker );
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2017-03-03 15:04:58 +00:00
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}
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2007-12-01 03:42:52 +00:00
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2017-12-08 10:25:13 +00:00
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2016-07-28 12:07:35 +00:00
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void DRC::DestroyDRCDialog( int aReason )
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2007-12-01 03:42:52 +00:00
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{
|
2016-04-15 18:15:22 +00:00
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if( m_drcDialog )
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2007-12-01 03:42:52 +00:00
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{
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2016-04-15 18:15:22 +00:00
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m_drcDialog->Destroy();
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2019-06-03 13:49:17 +00:00
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m_drcDialog = nullptr;
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2007-12-01 03:42:52 +00:00
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}
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}
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2007-06-05 12:10:51 +00:00
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2007-11-27 01:34:35 +00:00
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2020-05-24 14:54:26 +00:00
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bool DRC::LoadRules()
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2020-05-15 23:25:33 +00:00
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{
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2020-05-24 14:54:26 +00:00
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wxString rulesFilepath = m_editFrame->Prj().AbsolutePath( "drc-rules" );
|
2020-05-16 19:12:56 +00:00
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wxFileName rulesFile( rulesFilepath );
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2020-05-15 23:25:33 +00:00
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2020-05-16 19:12:56 +00:00
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if( rulesFile.FileExists() )
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2020-05-15 23:25:33 +00:00
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{
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2020-05-18 16:11:57 +00:00
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m_rules.clear();
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2020-05-16 19:12:56 +00:00
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2020-05-18 16:11:57 +00:00
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FILE* fp = wxFopen( rulesFilepath, wxT( "rt" ) );
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2020-05-16 19:12:56 +00:00
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2020-05-18 16:11:57 +00:00
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if( fp )
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{
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try
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2020-05-16 19:12:56 +00:00
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{
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2020-05-18 16:11:57 +00:00
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DRC_RULES_PARSER parser( m_pcb, fp, rulesFilepath );
|
2020-07-30 11:24:29 +00:00
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parser.Parse( m_rules, &NULL_REPORTER::GetInstance() );
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2020-05-18 16:11:57 +00:00
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}
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catch( PARSE_ERROR& pe )
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{
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// Don't leave possibly malformed stuff around for us to trip over
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m_rules.clear();
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2020-05-16 19:12:56 +00:00
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2020-05-24 14:54:26 +00:00
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wxSafeYield( m_editFrame );
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m_editFrame->ShowBoardSetupDialog( _( "Rules" ), pe.What(), ID_RULES_EDITOR,
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pe.lineNumber, pe.byteIndex );
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return false;
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2020-05-16 19:12:56 +00:00
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}
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2020-05-15 23:25:33 +00:00
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}
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}
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2020-05-16 19:12:56 +00:00
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2020-07-19 21:22:49 +00:00
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std::reverse( std::begin( m_rules ), std::end( m_rules ) );
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2020-05-23 21:48:24 +00:00
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2020-05-16 19:12:56 +00:00
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BOARD_DESIGN_SETTINGS& bds = m_pcb->GetDesignSettings();
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bds.m_DRCRules = m_rules;
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2020-05-24 14:54:26 +00:00
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return true;
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2020-05-15 23:25:33 +00:00
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}
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2010-09-15 14:53:33 +00:00
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void DRC::RunTests( wxTextCtrl* aMessages )
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2007-12-01 03:42:52 +00:00
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{
|
2020-05-18 16:11:57 +00:00
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// Make absolutely sure these are up-to-date
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2020-05-24 14:54:26 +00:00
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if( !LoadRules() )
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return;
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2020-05-15 23:25:33 +00:00
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2020-05-24 14:54:26 +00:00
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wxASSERT( m_pcb == m_editFrame->GetBoard() );
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2016-04-15 18:15:22 +00:00
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2020-05-24 14:54:26 +00:00
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BOARD_COMMIT commit( m_editFrame );
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2020-05-18 00:20:16 +00:00
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BOARD_DESIGN_SETTINGS& bds = m_pcb->GetDesignSettings();
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m_largestClearance = bds.GetBiggestClearanceValue();
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2020-05-18 20:09:36 +00:00
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if( !bds.Ignore( DRCE_INVALID_OUTLINE )
|
2020-06-08 02:19:46 +00:00
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|| !bds.Ignore( DRCE_COPPER_EDGE_CLEARANCE ) )
|
2018-11-28 12:11:43 +00:00
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{
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2020-05-18 00:20:16 +00:00
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if( aMessages )
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{
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aMessages->AppendText( _( "Board Outline...\n" ) );
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wxSafeYield();
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}
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2018-11-28 12:11:43 +00:00
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2020-05-18 00:20:16 +00:00
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testOutline( commit );
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}
|
2008-02-09 08:34:45 +00:00
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2007-12-01 03:42:52 +00:00
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// test pad to pad clearances, nothing to do with tracks, vias or zones.
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2020-06-08 02:19:46 +00:00
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if( !bds.Ignore( DRCE_COPPER_EDGE_CLEARANCE ) )
|
2009-06-27 06:26:41 +00:00
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{
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2009-09-10 15:22:26 +00:00
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if( aMessages )
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{
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2010-09-15 14:53:33 +00:00
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aMessages->AppendText( _( "Pad clearances...\n" ) );
|
2009-09-10 15:22:26 +00:00
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wxSafeYield();
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}
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2020-05-18 20:09:36 +00:00
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testPadClearances( commit );
|
2009-06-27 06:26:41 +00:00
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}
|
2007-12-01 03:42:52 +00:00
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2020-05-18 00:20:16 +00:00
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// test drilled holes
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if( !bds.Ignore( DRCE_DRILLED_HOLES_TOO_CLOSE )
|
2020-06-08 02:19:46 +00:00
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|| !bds.Ignore( DRCE_TOO_SMALL_DRILL )
|
2020-05-18 00:20:16 +00:00
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|| !bds.Ignore( DRCE_TOO_SMALL_MICROVIA_DRILL ) )
|
2018-04-14 14:58:01 +00:00
|
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|
{
|
2020-05-18 00:20:16 +00:00
|
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|
if( aMessages )
|
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{
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aMessages->AppendText( _( "Drill sizes and clearances...\n" ) );
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wxSafeYield();
|
|
|
|
}
|
2018-04-14 14:58:01 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
DRC_DRILLED_HOLE_TESTER tester( [&]( MARKER_PCB* aMarker )
|
|
|
|
{
|
|
|
|
addMarkerToPcb( commit, aMarker );
|
|
|
|
} );
|
|
|
|
|
|
|
|
tester.RunDRC( userUnits(), *m_pcb );
|
|
|
|
}
|
2018-04-14 14:58:01 +00:00
|
|
|
|
2018-01-14 16:38:48 +00:00
|
|
|
// caller (a wxTopLevelFrame) is the wxDialog or the Pcb Editor frame that call DRC:
|
2020-05-24 14:54:26 +00:00
|
|
|
wxWindow* caller = aMessages ? aMessages->GetParent() : m_editFrame;
|
2018-02-10 20:17:11 +00:00
|
|
|
|
|
|
|
if( m_refillZones )
|
|
|
|
{
|
2018-05-04 12:01:26 +00:00
|
|
|
if( aMessages )
|
|
|
|
aMessages->AppendText( _( "Refilling all zones...\n" ) );
|
|
|
|
|
2019-07-08 19:44:40 +00:00
|
|
|
m_toolMgr->GetTool<ZONE_FILLER_TOOL>()->FillAllZones( caller );
|
2018-02-10 20:17:11 +00:00
|
|
|
}
|
2018-04-06 10:24:23 +00:00
|
|
|
else
|
|
|
|
{
|
2018-05-04 12:01:26 +00:00
|
|
|
if( aMessages )
|
|
|
|
aMessages->AppendText( _( "Checking zone fills...\n" ) );
|
|
|
|
|
2019-07-08 19:44:40 +00:00
|
|
|
m_toolMgr->GetTool<ZONE_FILLER_TOOL>()->CheckAllZones( caller );
|
2018-04-06 10:24:23 +00:00
|
|
|
}
|
2008-12-04 20:53:11 +00:00
|
|
|
|
2018-08-23 22:41:57 +00:00
|
|
|
// test track and via clearances to other tracks, pads, and vias
|
|
|
|
if( aMessages )
|
|
|
|
{
|
|
|
|
aMessages->AppendText( _( "Track clearances...\n" ) );
|
|
|
|
wxSafeYield();
|
|
|
|
}
|
|
|
|
|
2020-05-24 14:54:26 +00:00
|
|
|
testTracks( commit, aMessages ? aMessages->GetParent() : m_editFrame, true );
|
2018-08-23 22:41:57 +00:00
|
|
|
|
2011-11-10 08:21:11 +00:00
|
|
|
// test zone clearances to other zones
|
|
|
|
if( aMessages )
|
2009-09-10 15:22:26 +00:00
|
|
|
{
|
2018-04-06 10:24:23 +00:00
|
|
|
aMessages->AppendText( _( "Zone to zone clearances...\n" ) );
|
2009-09-10 15:22:26 +00:00
|
|
|
wxSafeYield();
|
|
|
|
}
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
testZones( commit );
|
2007-12-01 03:42:52 +00:00
|
|
|
|
2008-02-09 08:34:45 +00:00
|
|
|
// find and gather unconnected pads.
|
2020-05-18 00:20:16 +00:00
|
|
|
if( m_doUnconnectedTest
|
|
|
|
&& !bds.Ignore( DRCE_UNCONNECTED_ITEMS ) )
|
2009-06-27 06:26:41 +00:00
|
|
|
{
|
2009-09-10 15:22:26 +00:00
|
|
|
if( aMessages )
|
|
|
|
{
|
2010-09-15 14:53:33 +00:00
|
|
|
aMessages->AppendText( _( "Unconnected pads...\n" ) );
|
2011-10-31 20:29:46 +00:00
|
|
|
aMessages->Refresh();
|
2009-09-10 15:22:26 +00:00
|
|
|
}
|
|
|
|
|
2007-12-01 03:42:52 +00:00
|
|
|
testUnconnected();
|
2009-06-27 06:26:41 +00:00
|
|
|
}
|
2008-02-09 08:34:45 +00:00
|
|
|
|
2012-07-13 18:55:29 +00:00
|
|
|
// find and gather vias, tracks, pads inside keepout areas.
|
|
|
|
if( m_doKeepoutTest )
|
|
|
|
{
|
|
|
|
if( aMessages )
|
|
|
|
{
|
|
|
|
aMessages->AppendText( _( "Keepout areas ...\n" ) );
|
|
|
|
aMessages->Refresh();
|
|
|
|
}
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
DRC_KEEPOUT_TESTER tester( [&]( MARKER_PCB* aMarker )
|
|
|
|
{
|
|
|
|
addMarkerToPcb( commit, aMarker );
|
|
|
|
} );
|
|
|
|
|
|
|
|
tester.RunDRC( userUnits(), *m_pcb );
|
2012-07-13 18:55:29 +00:00
|
|
|
}
|
|
|
|
|
2014-08-13 15:47:02 +00:00
|
|
|
// find and gather vias, tracks, pads inside text boxes.
|
2020-06-08 02:19:46 +00:00
|
|
|
if( !bds.Ignore( DRCE_CLEARANCE ) )
|
2014-08-13 15:47:02 +00:00
|
|
|
{
|
2020-05-18 00:20:16 +00:00
|
|
|
if( aMessages )
|
|
|
|
{
|
|
|
|
aMessages->AppendText( _( "Text and graphic clearances...\n" ) );
|
|
|
|
wxSafeYield();
|
|
|
|
}
|
2014-08-13 15:47:02 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
testCopperTextAndGraphics( commit );
|
|
|
|
}
|
2014-08-13 15:47:02 +00:00
|
|
|
|
2020-05-01 17:44:25 +00:00
|
|
|
// test courtyards
|
2020-05-18 00:20:16 +00:00
|
|
|
if( !bds.Ignore( DRCE_OVERLAPPING_FOOTPRINTS )
|
|
|
|
|| !bds.Ignore( DRCE_MISSING_COURTYARD )
|
|
|
|
|| !bds.Ignore( DRCE_MALFORMED_COURTYARD )
|
|
|
|
|| !bds.Ignore( DRCE_PTH_IN_COURTYARD )
|
|
|
|
|| !bds.Ignore( DRCE_NPTH_IN_COURTYARD ) )
|
2017-03-16 17:09:33 +00:00
|
|
|
{
|
|
|
|
if( aMessages )
|
|
|
|
{
|
|
|
|
aMessages->AppendText( _( "Courtyard areas...\n" ) );
|
|
|
|
aMessages->Refresh();
|
|
|
|
}
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
DRC_COURTYARD_TESTER tester( [&]( MARKER_PCB* aMarker )
|
|
|
|
{
|
|
|
|
addMarkerToPcb( commit, aMarker );
|
|
|
|
} );
|
|
|
|
|
|
|
|
tester.RunDRC( userUnits(), *m_pcb );
|
2017-03-16 17:09:33 +00:00
|
|
|
}
|
|
|
|
|
2019-03-28 19:30:51 +00:00
|
|
|
for( DRC_ITEM* footprintItem : m_footprints )
|
|
|
|
delete footprintItem;
|
|
|
|
|
|
|
|
m_footprints.clear();
|
|
|
|
m_footprintsTested = false;
|
|
|
|
|
|
|
|
if( m_testFootprints && !Kiface().IsSingle() )
|
|
|
|
{
|
|
|
|
if( aMessages )
|
|
|
|
{
|
|
|
|
aMessages->AppendText( _( "Checking footprints against schematic...\n" ) );
|
|
|
|
aMessages->Refresh();
|
|
|
|
}
|
|
|
|
|
|
|
|
NETLIST netlist;
|
2020-05-24 14:54:26 +00:00
|
|
|
m_editFrame->FetchNetlistFromSchematic( netlist, PCB_EDIT_FRAME::ANNOTATION_DIALOG );
|
2019-03-28 19:30:51 +00:00
|
|
|
|
|
|
|
if( m_drcDialog )
|
|
|
|
m_drcDialog->Raise();
|
|
|
|
|
2020-05-29 20:23:08 +00:00
|
|
|
TestFootprints( netlist, m_pcb, m_footprints );
|
2019-03-28 19:30:51 +00:00
|
|
|
m_footprintsTested = true;
|
|
|
|
}
|
|
|
|
|
2018-07-04 08:23:40 +00:00
|
|
|
// Check if there are items on disabled layers
|
2020-05-18 00:20:16 +00:00
|
|
|
if( !bds.Ignore( DRCE_DISABLED_LAYER_ITEM ) )
|
2018-07-04 08:23:40 +00:00
|
|
|
{
|
2020-05-18 00:20:16 +00:00
|
|
|
if( aMessages )
|
|
|
|
{
|
|
|
|
aMessages->AppendText( _( "Items on disabled layers...\n" ) );
|
|
|
|
aMessages->Refresh();
|
|
|
|
}
|
|
|
|
|
|
|
|
testDisabledLayers( commit );
|
2018-07-04 08:23:40 +00:00
|
|
|
}
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
if( !bds.Ignore( DRCE_UNRESOLVED_VARIABLE ) )
|
|
|
|
{
|
|
|
|
if( aMessages )
|
|
|
|
{
|
|
|
|
aMessages->AppendText( _( "Unresolved text variables...\n" ) );
|
|
|
|
aMessages->Refresh();
|
|
|
|
}
|
|
|
|
|
|
|
|
DRC_TEXTVAR_TESTER tester( [&]( MARKER_PCB* aMarker )
|
|
|
|
{
|
|
|
|
addMarkerToPcb( commit, aMarker );
|
2020-05-28 13:36:54 +00:00
|
|
|
},
|
|
|
|
m_editFrame->GetCanvas()->GetWorksheet() );
|
2020-03-29 01:12:29 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
tester.RunDRC( userUnits(), *m_pcb );
|
|
|
|
}
|
|
|
|
|
|
|
|
commit.Push( wxEmptyString, false, false );
|
2019-03-28 19:30:51 +00:00
|
|
|
m_drcRun = true;
|
|
|
|
|
2016-04-15 18:15:22 +00:00
|
|
|
// update the m_drcDialog listboxes
|
2007-12-03 05:14:51 +00:00
|
|
|
updatePointers();
|
2009-09-10 15:22:26 +00:00
|
|
|
|
|
|
|
if( aMessages )
|
|
|
|
{
|
|
|
|
// no newline on this one because it is last, don't want the window
|
|
|
|
// to unnecessarily scroll.
|
2010-09-15 14:53:33 +00:00
|
|
|
aMessages->AppendText( _( "Finished" ) );
|
2009-09-10 15:22:26 +00:00
|
|
|
}
|
2007-12-03 05:14:51 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void DRC::updatePointers()
|
|
|
|
{
|
2020-05-24 14:54:26 +00:00
|
|
|
// update my pointers, m_editFrame is the only unchangeable one
|
|
|
|
m_pcb = m_editFrame->GetBoard();
|
2007-12-04 18:23:38 +00:00
|
|
|
|
2020-05-24 14:54:26 +00:00
|
|
|
m_editFrame->ResolveDRCExclusions();
|
2020-02-28 00:05:40 +00:00
|
|
|
|
2016-04-15 18:15:22 +00:00
|
|
|
if( m_drcDialog ) // Use diag list boxes only in DRC dialog
|
2008-02-09 08:34:45 +00:00
|
|
|
{
|
2020-02-24 23:17:30 +00:00
|
|
|
m_drcDialog->SetMarkersProvider( new BOARD_DRC_ITEMS_PROVIDER( m_pcb ) );
|
2020-05-24 14:54:26 +00:00
|
|
|
m_drcDialog->SetUnconnectedProvider( new RATSNEST_DRC_ITEMS_PROVIDER( m_editFrame,
|
2020-02-28 00:05:40 +00:00
|
|
|
&m_unconnected ) );
|
2020-05-24 14:54:26 +00:00
|
|
|
m_drcDialog->SetFootprintsProvider( new VECTOR_DRC_ITEMS_PROVIDER( m_editFrame,
|
2020-02-28 00:05:40 +00:00
|
|
|
&m_footprints ) );
|
2008-02-09 08:34:45 +00:00
|
|
|
}
|
2007-12-03 05:14:51 +00:00
|
|
|
}
|
2008-02-09 08:34:45 +00:00
|
|
|
|
2007-12-03 05:14:51 +00:00
|
|
|
|
2020-05-18 20:09:36 +00:00
|
|
|
void DRC::testPadClearances( BOARD_COMMIT& aCommit )
|
2007-12-01 03:42:52 +00:00
|
|
|
{
|
2020-05-18 20:09:36 +00:00
|
|
|
BOARD_DESIGN_SETTINGS& bds = m_pcb->GetDesignSettings();
|
|
|
|
std::vector<D_PAD*> sortedPads;
|
2008-03-18 04:04:17 +00:00
|
|
|
|
2011-10-31 13:44:13 +00:00
|
|
|
m_pcb->GetSortedPadListByXthenYCoord( sortedPads );
|
2007-12-01 03:42:52 +00:00
|
|
|
|
2019-06-04 10:45:43 +00:00
|
|
|
if( sortedPads.empty() )
|
2018-05-16 07:20:04 +00:00
|
|
|
return;
|
|
|
|
|
2020-05-18 20:09:36 +00:00
|
|
|
// find the max size of the pads (used to stop the pad-to-pad tests)
|
2009-03-23 19:54:15 +00:00
|
|
|
int max_size = 0;
|
2008-03-18 04:04:17 +00:00
|
|
|
|
2019-06-04 10:45:43 +00:00
|
|
|
for( D_PAD* pad : sortedPads )
|
2007-12-01 03:42:52 +00:00
|
|
|
{
|
2012-02-19 04:02:19 +00:00
|
|
|
// GetBoundingRadius() is the radius of the minimum sized circle fully containing the pad
|
|
|
|
int radius = pad->GetBoundingRadius();
|
2018-02-10 20:17:11 +00:00
|
|
|
|
2012-02-19 04:02:19 +00:00
|
|
|
if( radius > max_size )
|
|
|
|
max_size = radius;
|
2007-12-01 03:42:52 +00:00
|
|
|
}
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
// Better to be fast than accurate; this keeps us from having to look up / calculate the
|
|
|
|
// actual clearances
|
|
|
|
max_size += m_largestClearance;
|
|
|
|
|
2018-05-16 07:20:04 +00:00
|
|
|
// Upper limit of pad list (limit not included)
|
|
|
|
D_PAD** listEnd = &sortedPads[0] + sortedPads.size();
|
2008-03-18 04:04:17 +00:00
|
|
|
|
2018-05-16 07:20:04 +00:00
|
|
|
// Test the pads
|
2019-06-04 10:45:43 +00:00
|
|
|
for( auto& pad : sortedPads )
|
2007-12-01 03:42:52 +00:00
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
if( !bds.Ignore( DRCE_COPPER_EDGE_CLEARANCE ) && m_board_outline_valid )
|
2020-05-18 20:09:36 +00:00
|
|
|
{
|
2020-05-29 12:36:45 +00:00
|
|
|
int minClearance = bds.m_CopperEdgeClearance;
|
|
|
|
m_clearanceSource = _( "board edge" );
|
|
|
|
|
2020-05-18 20:09:36 +00:00
|
|
|
static DRAWSEGMENT dummyEdge;
|
|
|
|
dummyEdge.SetLayer( Edge_Cuts );
|
|
|
|
|
2020-08-07 20:18:33 +00:00
|
|
|
pad->GetRuleClearance( &dummyEdge, pad->GetLayer(), &minClearance, &m_clearanceSource );
|
2020-05-18 20:09:36 +00:00
|
|
|
|
|
|
|
for( auto it = m_board_outlines.IterateSegmentsWithHoles(); it; it++ )
|
|
|
|
{
|
2020-07-04 18:48:22 +00:00
|
|
|
SHAPE_SEGMENT edge( *it );
|
2020-05-18 20:09:36 +00:00
|
|
|
int actual;
|
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
if( pad->Collide( &edge, minClearance, &actual ) )
|
2020-05-18 20:09:36 +00:00
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_COPPER_EDGE_CLEARANCE );
|
2008-02-09 08:34:45 +00:00
|
|
|
|
2020-05-21 17:42:42 +00:00
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
|
2020-05-18 20:09:36 +00:00
|
|
|
m_clearanceSource,
|
|
|
|
MessageTextFromValue( userUnits(), minClearance, true ),
|
|
|
|
MessageTextFromValue( userUnits(), actual, true ) );
|
|
|
|
|
|
|
|
drcItem->SetErrorMessage( m_msg );
|
|
|
|
drcItem->SetItems( pad );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, pad->GetPosition() );
|
|
|
|
addMarkerToPcb( aCommit, marker );
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-06-08 02:19:46 +00:00
|
|
|
if( !bds.Ignore( DRCE_CLEARANCE ) )
|
2020-05-18 20:09:36 +00:00
|
|
|
{
|
|
|
|
int x_limit = pad->GetPosition().x + pad->GetBoundingRadius() + max_size;
|
|
|
|
|
|
|
|
doPadToPadsDrc( aCommit, pad, &pad, listEnd, x_limit );
|
|
|
|
}
|
2007-12-01 03:42:52 +00:00
|
|
|
}
|
|
|
|
}
|
2007-11-27 01:34:35 +00:00
|
|
|
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
void DRC::testTracks( BOARD_COMMIT& aCommit, wxWindow *aActiveWindow, bool aShowProgressBar )
|
2010-09-20 16:21:47 +00:00
|
|
|
{
|
2020-05-14 19:24:10 +00:00
|
|
|
wxProgressDialog* progressDialog = NULL;
|
|
|
|
const int delta = 500; // This is the number of tests between 2 calls to the
|
|
|
|
// progress bar
|
|
|
|
int count = m_pcb->Tracks().size();
|
|
|
|
int deltamax = count/delta;
|
2013-03-20 14:50:12 +00:00
|
|
|
|
2011-11-10 08:21:11 +00:00
|
|
|
if( aShowProgressBar && deltamax > 3 )
|
2010-09-20 16:21:47 +00:00
|
|
|
{
|
2018-01-15 16:57:03 +00:00
|
|
|
// Do not use wxPD_APP_MODAL style here: it is not necessary and create issues
|
|
|
|
// on OSX
|
2011-11-10 08:21:11 +00:00
|
|
|
progressDialog = new wxProgressDialog( _( "Track clearances" ), wxEmptyString,
|
2015-07-08 07:33:11 +00:00
|
|
|
deltamax, aActiveWindow,
|
2018-01-15 16:57:03 +00:00
|
|
|
wxPD_AUTO_HIDE | wxPD_CAN_ABORT | wxPD_ELAPSED_TIME );
|
2011-11-10 08:21:11 +00:00
|
|
|
progressDialog->Update( 0, wxEmptyString );
|
|
|
|
}
|
|
|
|
|
2020-05-14 19:24:10 +00:00
|
|
|
std::shared_ptr<CONNECTIVITY_DATA> connectivity = m_pcb->GetConnectivity();
|
|
|
|
BOARD_DESIGN_SETTINGS& settings = m_pcb->GetDesignSettings();
|
|
|
|
|
|
|
|
|
|
|
|
if( !m_pcb->GetDesignSettings().Ignore( DRCE_DANGLING_TRACK )
|
|
|
|
|| !m_pcb->GetDesignSettings().Ignore( DRCE_DANGLING_VIA ) )
|
|
|
|
{
|
|
|
|
connectivity->Clear();
|
|
|
|
connectivity->Build( m_pcb ); // just in case. This really needs to be reliable.
|
|
|
|
}
|
|
|
|
|
2011-11-10 08:21:11 +00:00
|
|
|
int ii = 0;
|
|
|
|
count = 0;
|
2013-03-20 14:50:12 +00:00
|
|
|
|
2019-05-31 02:30:28 +00:00
|
|
|
for( auto seg_it = m_pcb->Tracks().begin(); seg_it != m_pcb->Tracks().end(); seg_it++ )
|
2011-11-10 08:21:11 +00:00
|
|
|
{
|
2018-02-10 20:17:11 +00:00
|
|
|
if( ii++ > delta )
|
2011-11-10 08:21:11 +00:00
|
|
|
{
|
|
|
|
ii = 0;
|
|
|
|
count++;
|
2013-03-20 14:50:12 +00:00
|
|
|
|
2011-11-10 08:21:11 +00:00
|
|
|
if( progressDialog )
|
|
|
|
{
|
|
|
|
if( !progressDialog->Update( count, wxEmptyString ) )
|
|
|
|
break; // Aborted by user
|
2015-07-08 07:33:11 +00:00
|
|
|
#ifdef __WXMAC__
|
|
|
|
// Work around a dialog z-order issue on OS X
|
|
|
|
if( count == deltamax )
|
|
|
|
aActiveWindow->Raise();
|
|
|
|
#endif
|
2011-11-10 08:21:11 +00:00
|
|
|
}
|
|
|
|
}
|
2013-03-20 14:50:12 +00:00
|
|
|
|
2019-03-19 16:46:46 +00:00
|
|
|
// Test new segment against tracks and pads, optionally against copper zones
|
2020-05-29 20:23:08 +00:00
|
|
|
doTrackDrc( aCommit, *seg_it, seg_it + 1, m_pcb->Tracks().end(), m_testTracksAgainstZones );
|
2020-05-14 19:24:10 +00:00
|
|
|
|
|
|
|
// Test for dangling items
|
|
|
|
int code = (*seg_it)->Type() == PCB_VIA_T ? DRCE_DANGLING_VIA : DRCE_DANGLING_TRACK;
|
|
|
|
wxPoint pos;
|
|
|
|
|
|
|
|
if( !settings.Ignore( code ) && connectivity->TestTrackEndpointDangling( *seg_it, &pos ) )
|
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( code );
|
2020-05-14 19:24:10 +00:00
|
|
|
drcItem->SetItems( *seg_it );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, pos );
|
2020-05-18 00:20:16 +00:00
|
|
|
addMarkerToPcb( aCommit, marker );
|
2020-05-14 19:24:10 +00:00
|
|
|
}
|
2010-09-20 16:21:47 +00:00
|
|
|
}
|
2013-03-20 14:50:12 +00:00
|
|
|
|
2011-11-10 08:21:11 +00:00
|
|
|
if( progressDialog )
|
|
|
|
progressDialog->Destroy();
|
2010-09-20 16:21:47 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2007-12-01 03:42:52 +00:00
|
|
|
void DRC::testUnconnected()
|
|
|
|
{
|
2019-03-31 09:37:57 +00:00
|
|
|
for( DRC_ITEM* unconnectedItem : m_unconnected )
|
|
|
|
delete unconnectedItem;
|
|
|
|
|
|
|
|
m_unconnected.clear();
|
2017-03-22 13:43:10 +00:00
|
|
|
|
|
|
|
auto connectivity = m_pcb->GetConnectivity();
|
|
|
|
|
2017-03-22 15:47:15 +00:00
|
|
|
connectivity->Clear();
|
2018-02-10 20:17:11 +00:00
|
|
|
connectivity->Build( m_pcb ); // just in case. This really needs to be reliable.
|
2017-03-22 15:47:15 +00:00
|
|
|
connectivity->RecalculateRatsnest();
|
2007-11-27 01:34:35 +00:00
|
|
|
|
2017-03-22 15:47:15 +00:00
|
|
|
std::vector<CN_EDGE> edges;
|
|
|
|
connectivity->GetUnconnectedEdges( edges );
|
2013-03-20 14:50:12 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
for( const CN_EDGE& edge : edges )
|
2007-12-01 03:42:52 +00:00
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* item = DRC_ITEM::Create( DRCE_UNCONNECTED_ITEMS );
|
2020-04-24 13:36:10 +00:00
|
|
|
item->SetItems( edge.GetSourceNode()->Parent(), edge.GetTargetNode()->Parent() );
|
2020-03-16 11:05:01 +00:00
|
|
|
m_unconnected.push_back( item );
|
2017-03-22 15:47:15 +00:00
|
|
|
}
|
2007-12-01 03:42:52 +00:00
|
|
|
}
|
2007-11-27 01:34:35 +00:00
|
|
|
|
2009-03-23 19:54:15 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
void DRC::testZones( BOARD_COMMIT& aCommit )
|
2007-12-01 03:42:52 +00:00
|
|
|
{
|
2020-06-03 17:46:44 +00:00
|
|
|
BOARD_DESIGN_SETTINGS& bds = m_pcb->GetDesignSettings();
|
2020-05-29 20:23:08 +00:00
|
|
|
|
2011-09-17 01:22:26 +00:00
|
|
|
// Test copper areas for valid netcodes
|
2008-02-09 08:34:45 +00:00
|
|
|
// if a netcode is < 0 the netname was not found when reading a netlist
|
2009-01-24 19:30:39 +00:00
|
|
|
// if a netcode is == 0 the netname is void, and the zone is not connected.
|
|
|
|
// This is allowed, but i am not sure this is a good idea
|
2015-01-22 12:06:34 +00:00
|
|
|
//
|
|
|
|
// In recent Pcbnew versions, the netcode is always >= 0, but an internal net name
|
2018-02-10 20:17:11 +00:00
|
|
|
// is stored, and initialized from the file or the zone properties editor.
|
2015-01-22 12:06:34 +00:00
|
|
|
// if it differs from the net name from net code, there is a DRC issue
|
2011-09-07 19:41:04 +00:00
|
|
|
|
2020-05-29 20:23:08 +00:00
|
|
|
std::vector<SHAPE_POLY_SET> smoothed_polys;
|
2020-06-03 17:46:44 +00:00
|
|
|
smoothed_polys.resize( m_pcb->GetAreaCount() );
|
2011-09-07 19:41:04 +00:00
|
|
|
|
2020-05-29 20:23:08 +00:00
|
|
|
for( int ii = 0; ii < m_pcb->GetAreaCount(); ii++ )
|
|
|
|
{
|
|
|
|
ZONE_CONTAINER* zone = m_pcb->GetArea( ii );
|
|
|
|
|
|
|
|
if( !bds.Ignore( DRCE_ZONE_HAS_EMPTY_NET ) && zone->IsOnCopperLayer() )
|
|
|
|
{
|
2020-05-04 19:08:42 +00:00
|
|
|
int netcode = zone->GetNetCode();
|
2020-05-29 20:23:08 +00:00
|
|
|
// a netcode < 0 or > 0 and no pad in net is a error or strange
|
2020-05-04 19:08:42 +00:00
|
|
|
// perhaps a "dead" net, which happens when all pads in this net were removed
|
|
|
|
// Remark: a netcode < 0 should not happen (this is more a bug somewhere)
|
|
|
|
int pads_in_net = ( netcode > 0 ) ? m_pcb->GetConnectivity()->GetPadCount( netcode ) : 1;
|
2015-01-22 12:06:34 +00:00
|
|
|
|
2020-05-04 19:08:42 +00:00
|
|
|
if( ( netcode < 0 ) || pads_in_net == 0 )
|
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_ZONE_HAS_EMPTY_NET );
|
2020-05-04 19:08:42 +00:00
|
|
|
drcItem->SetItems( zone );
|
2020-04-24 13:36:10 +00:00
|
|
|
|
2020-05-04 19:08:42 +00:00
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, zone->GetPosition() );
|
2020-05-18 00:20:16 +00:00
|
|
|
addMarkerToPcb( aCommit, marker );
|
2020-05-04 19:08:42 +00:00
|
|
|
}
|
2008-02-09 08:34:45 +00:00
|
|
|
}
|
2020-05-29 20:23:08 +00:00
|
|
|
|
2020-06-03 17:46:44 +00:00
|
|
|
ZONE_CONTAINER* zoneRef = m_pcb->GetArea( ii );
|
2020-05-29 20:23:08 +00:00
|
|
|
std::set<VECTOR2I> colinearCorners;
|
2020-06-03 17:46:44 +00:00
|
|
|
zoneRef->GetColinearCorners( m_pcb, colinearCorners );
|
2020-05-29 20:23:08 +00:00
|
|
|
|
|
|
|
zoneRef->BuildSmoothedPoly( smoothed_polys[ii], &colinearCorners );
|
2008-02-09 08:34:45 +00:00
|
|
|
}
|
|
|
|
|
2020-05-29 20:23:08 +00:00
|
|
|
// iterate through all areas
|
2020-06-03 17:46:44 +00:00
|
|
|
for( int ia = 0; ia < m_pcb->GetAreaCount(); ia++ )
|
2020-05-29 20:23:08 +00:00
|
|
|
{
|
2020-06-03 17:46:44 +00:00
|
|
|
ZONE_CONTAINER* zoneRef = m_pcb->GetArea( ia );
|
2020-05-29 20:23:08 +00:00
|
|
|
|
|
|
|
if( !zoneRef->IsOnCopperLayer() )
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// If we are testing a single zone, then iterate through all other zones
|
|
|
|
// Otherwise, we have already tested the zone combination
|
2020-06-03 17:46:44 +00:00
|
|
|
for( int ia2 = ia + 1; ia2 < m_pcb->GetAreaCount(); ia2++ )
|
2020-05-29 20:23:08 +00:00
|
|
|
{
|
2020-06-03 17:46:44 +00:00
|
|
|
ZONE_CONTAINER* zoneToTest = m_pcb->GetArea( ia2 );
|
2020-05-29 20:23:08 +00:00
|
|
|
|
|
|
|
if( zoneRef == zoneToTest )
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// test for same layer
|
|
|
|
if( zoneRef->GetLayer() != zoneToTest->GetLayer() )
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Test for same net
|
|
|
|
if( zoneRef->GetNetCode() == zoneToTest->GetNetCode() && zoneRef->GetNetCode() >= 0 )
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// test for different priorities
|
|
|
|
if( zoneRef->GetPriority() != zoneToTest->GetPriority() )
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// test for different types
|
|
|
|
if( zoneRef->GetIsKeepout() != zoneToTest->GetIsKeepout() )
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Examine a candidate zone: compare zoneToTest to zoneRef
|
|
|
|
|
|
|
|
// Get clearance used in zone to zone test. The policy used to
|
|
|
|
// obtain that value is now part of the zone object itself by way of
|
|
|
|
// ZONE_CONTAINER::GetClearance().
|
2020-08-07 20:18:33 +00:00
|
|
|
int zone2zoneClearance = zoneRef->GetClearance( zoneRef->GetLayer(), zoneToTest,
|
|
|
|
&m_clearanceSource );
|
2020-05-29 20:23:08 +00:00
|
|
|
|
|
|
|
// Keepout areas have no clearance, so set zone2zoneClearance to 1
|
|
|
|
// ( zone2zoneClearance = 0 can create problems in test functions)
|
|
|
|
if( zoneRef->GetIsKeepout() )
|
|
|
|
zone2zoneClearance = 1;
|
|
|
|
|
|
|
|
// test for some corners of zoneRef inside zoneToTest
|
|
|
|
for( auto iterator = smoothed_polys[ia].IterateWithHoles(); iterator; iterator++ )
|
|
|
|
{
|
|
|
|
VECTOR2I currentVertex = *iterator;
|
|
|
|
wxPoint pt( currentVertex.x, currentVertex.y );
|
|
|
|
|
|
|
|
if( smoothed_polys[ia2].Contains( currentVertex ) )
|
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
|
2020-05-29 20:23:08 +00:00
|
|
|
drcItem->SetItems( zoneRef, zoneToTest );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, pt );
|
|
|
|
addMarkerToPcb( aCommit, marker );
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// test for some corners of zoneToTest inside zoneRef
|
|
|
|
for( auto iterator = smoothed_polys[ia2].IterateWithHoles(); iterator; iterator++ )
|
|
|
|
{
|
|
|
|
VECTOR2I currentVertex = *iterator;
|
|
|
|
wxPoint pt( currentVertex.x, currentVertex.y );
|
|
|
|
|
|
|
|
if( smoothed_polys[ia].Contains( currentVertex ) )
|
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
|
2020-05-29 20:23:08 +00:00
|
|
|
drcItem->SetItems( zoneToTest, zoneRef );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, pt );
|
|
|
|
addMarkerToPcb( aCommit, marker );
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Iterate through all the segments of refSmoothedPoly
|
|
|
|
std::map<wxPoint, int> conflictPoints;
|
|
|
|
|
|
|
|
for( auto refIt = smoothed_polys[ia].IterateSegmentsWithHoles(); refIt; refIt++ )
|
|
|
|
{
|
|
|
|
// Build ref segment
|
|
|
|
SEG refSegment = *refIt;
|
|
|
|
|
|
|
|
// Iterate through all the segments in smoothed_polys[ia2]
|
|
|
|
for( auto testIt = smoothed_polys[ia2].IterateSegmentsWithHoles(); testIt; testIt++ )
|
|
|
|
{
|
|
|
|
// Build test segment
|
|
|
|
SEG testSegment = *testIt;
|
|
|
|
wxPoint pt;
|
|
|
|
|
|
|
|
int ax1, ay1, ax2, ay2;
|
|
|
|
ax1 = refSegment.A.x;
|
|
|
|
ay1 = refSegment.A.y;
|
|
|
|
ax2 = refSegment.B.x;
|
|
|
|
ay2 = refSegment.B.y;
|
|
|
|
|
|
|
|
int bx1, by1, bx2, by2;
|
|
|
|
bx1 = testSegment.A.x;
|
|
|
|
by1 = testSegment.A.y;
|
|
|
|
bx2 = testSegment.B.x;
|
|
|
|
by2 = testSegment.B.y;
|
|
|
|
|
|
|
|
int d = GetClearanceBetweenSegments( bx1, by1, bx2, by2,
|
|
|
|
0,
|
|
|
|
ax1, ay1, ax2, ay2,
|
|
|
|
0,
|
|
|
|
zone2zoneClearance,
|
|
|
|
&pt.x, &pt.y );
|
|
|
|
|
|
|
|
if( d < zone2zoneClearance )
|
|
|
|
{
|
|
|
|
if( conflictPoints.count( pt ) )
|
|
|
|
conflictPoints[ pt ] = std::min( conflictPoints[ pt ], d );
|
|
|
|
else
|
|
|
|
conflictPoints[ pt ] = d;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for( const std::pair<const wxPoint, int>& conflict : conflictPoints )
|
|
|
|
{
|
|
|
|
int actual = conflict.second;
|
|
|
|
DRC_ITEM* drcItem;
|
|
|
|
|
|
|
|
if( actual <= 0 )
|
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
drcItem = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
|
2020-05-29 20:23:08 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
|
2020-05-29 20:23:08 +00:00
|
|
|
|
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
|
|
|
|
m_clearanceSource,
|
|
|
|
MessageTextFromValue( userUnits(), zone2zoneClearance, true ),
|
|
|
|
MessageTextFromValue( userUnits(), conflict.second, true ) );
|
|
|
|
|
|
|
|
drcItem->SetErrorMessage( m_msg );
|
|
|
|
}
|
|
|
|
|
|
|
|
drcItem->SetItems( zoneRef, zoneToTest );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, conflict.first );
|
|
|
|
addMarkerToPcb( aCommit, marker );
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2007-12-01 03:42:52 +00:00
|
|
|
}
|
2007-08-08 20:51:08 +00:00
|
|
|
|
2007-12-01 03:42:52 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
void DRC::testCopperTextAndGraphics( BOARD_COMMIT& aCommit )
|
2014-08-13 15:47:02 +00:00
|
|
|
{
|
2018-08-27 13:50:50 +00:00
|
|
|
// Test copper items for clearance violations with vias, tracks and pads
|
2014-08-13 15:47:02 +00:00
|
|
|
|
2018-08-23 22:41:57 +00:00
|
|
|
for( BOARD_ITEM* brdItem : m_pcb->Drawings() )
|
2014-08-13 15:47:02 +00:00
|
|
|
{
|
2018-08-27 13:50:50 +00:00
|
|
|
if( IsCopperLayer( brdItem->GetLayer() ) )
|
2020-05-18 00:20:16 +00:00
|
|
|
testCopperDrawItem( aCommit, brdItem );
|
2018-08-23 22:41:57 +00:00
|
|
|
}
|
2014-08-13 15:47:02 +00:00
|
|
|
|
2018-08-23 22:41:57 +00:00
|
|
|
for( MODULE* module : m_pcb->Modules() )
|
|
|
|
{
|
2018-12-15 22:29:36 +00:00
|
|
|
TEXTE_MODULE& ref = module->Reference();
|
|
|
|
TEXTE_MODULE& val = module->Value();
|
2018-08-23 22:41:57 +00:00
|
|
|
|
2018-12-15 22:29:36 +00:00
|
|
|
if( ref.IsVisible() && IsCopperLayer( ref.GetLayer() ) )
|
2020-05-18 00:20:16 +00:00
|
|
|
testCopperDrawItem( aCommit, &ref );
|
2018-12-15 22:29:36 +00:00
|
|
|
|
|
|
|
if( val.IsVisible() && IsCopperLayer( val.GetLayer() ) )
|
2020-05-18 00:20:16 +00:00
|
|
|
testCopperDrawItem( aCommit, &val );
|
2018-08-23 22:41:57 +00:00
|
|
|
|
2018-11-03 17:31:07 +00:00
|
|
|
if( module->IsNetTie() )
|
|
|
|
continue;
|
|
|
|
|
2020-05-07 00:30:46 +00:00
|
|
|
for( BOARD_ITEM* item : module->GraphicalItems() )
|
2018-08-23 22:41:57 +00:00
|
|
|
{
|
2018-08-27 13:50:50 +00:00
|
|
|
if( IsCopperLayer( item->GetLayer() ) )
|
|
|
|
{
|
2018-12-15 22:29:36 +00:00
|
|
|
if( item->Type() == PCB_MODULE_TEXT_T && ( (TEXTE_MODULE*) item )->IsVisible() )
|
2020-05-18 00:20:16 +00:00
|
|
|
testCopperDrawItem( aCommit, item );
|
2018-08-27 13:50:50 +00:00
|
|
|
else if( item->Type() == PCB_MODULE_EDGE_T )
|
2020-05-18 00:20:16 +00:00
|
|
|
testCopperDrawItem( aCommit, item );
|
2018-08-27 13:50:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
void DRC::testCopperDrawItem( BOARD_COMMIT& aCommit, BOARD_ITEM* aItem )
|
2018-08-27 13:50:50 +00:00
|
|
|
{
|
2020-07-04 18:48:22 +00:00
|
|
|
EDA_RECT bbox;
|
|
|
|
std::vector<SHAPE*> itemShapes;
|
|
|
|
DRAWSEGMENT* drawItem = dynamic_cast<DRAWSEGMENT*>( aItem );
|
|
|
|
EDA_TEXT* textItem = dynamic_cast<EDA_TEXT*>( aItem );
|
2018-08-27 13:50:50 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
if( drawItem )
|
2018-08-27 13:50:50 +00:00
|
|
|
{
|
2020-05-18 00:20:16 +00:00
|
|
|
bbox = drawItem->GetBoundingBox();
|
2020-07-04 18:48:22 +00:00
|
|
|
itemShapes = drawItem->MakeEffectiveShapes();
|
2018-08-27 13:50:50 +00:00
|
|
|
}
|
2020-07-04 18:48:22 +00:00
|
|
|
else if( textItem )
|
2020-05-18 00:20:16 +00:00
|
|
|
{
|
|
|
|
bbox = textItem->GetTextBox();
|
2018-08-27 13:50:50 +00:00
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
int penWidth = textItem->GetEffectiveTextPenWidth();
|
|
|
|
std::vector<wxPoint> pts;
|
|
|
|
textItem->TransformTextShapeToSegmentList( pts );
|
2020-05-18 00:20:16 +00:00
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
for( unsigned jj = 0; jj < pts.size(); jj += 2 )
|
|
|
|
itemShapes.push_back( new SHAPE_SEGMENT( pts[jj], pts[jj+1], penWidth ) );
|
2020-05-18 00:20:16 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
wxFAIL_MSG( "unknown item type in testCopperDrawItem()" );
|
|
|
|
return;
|
2018-08-27 13:50:50 +00:00
|
|
|
}
|
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
SHAPE_RECT bboxShape( bbox.GetX(), bbox.GetY(), bbox.GetWidth(), bbox.GetHeight() );
|
2020-05-26 22:46:34 +00:00
|
|
|
|
2018-08-27 13:50:50 +00:00
|
|
|
// Test tracks and vias
|
2020-08-07 20:18:33 +00:00
|
|
|
for( TRACK* track : m_pcb->Tracks() )
|
2018-08-27 13:50:50 +00:00
|
|
|
{
|
|
|
|
if( !track->IsOnLayer( aItem->GetLayer() ) )
|
|
|
|
continue;
|
|
|
|
|
2020-08-07 20:18:33 +00:00
|
|
|
int minClearance = track->GetClearance( track->GetLayer(), aItem, &m_clearanceSource );
|
2020-07-04 18:48:22 +00:00
|
|
|
int actual = INT_MAX;
|
|
|
|
wxPoint pos;
|
2020-04-28 21:43:29 +00:00
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
SHAPE_SEGMENT trackSeg( track->GetStart(), track->GetEnd(), track->GetWidth() );
|
2018-08-27 13:50:50 +00:00
|
|
|
|
2020-04-28 21:43:29 +00:00
|
|
|
// Fast test to detect a track segment candidate inside the text bounding box
|
2020-07-04 18:48:22 +00:00
|
|
|
if( !bboxShape.Collide( &trackSeg, 0 ) )
|
2020-04-28 21:43:29 +00:00
|
|
|
continue;
|
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
for( const SHAPE* shape : itemShapes )
|
2018-08-27 13:50:50 +00:00
|
|
|
{
|
2020-07-04 18:48:22 +00:00
|
|
|
int this_dist;
|
2020-04-28 21:43:29 +00:00
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
if( shape->Collide( &trackSeg, minClearance, &this_dist ) )
|
2018-08-27 13:50:50 +00:00
|
|
|
{
|
2020-07-04 18:48:22 +00:00
|
|
|
if( this_dist < actual )
|
|
|
|
{
|
|
|
|
actual = this_dist;
|
|
|
|
pos = (wxPoint) shape->Centre();
|
|
|
|
}
|
2020-04-28 21:43:29 +00:00
|
|
|
}
|
|
|
|
}
|
2020-04-24 13:36:10 +00:00
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
if( actual < INT_MAX )
|
2020-04-28 21:43:29 +00:00
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
|
2020-04-24 13:36:10 +00:00
|
|
|
|
2020-05-21 17:42:42 +00:00
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
|
2020-05-18 00:20:16 +00:00
|
|
|
m_clearanceSource,
|
|
|
|
MessageTextFromValue( userUnits(), minClearance, true ),
|
2020-07-04 18:48:22 +00:00
|
|
|
MessageTextFromValue( userUnits(), std::max( 0, actual ), true ) );
|
2020-04-28 21:43:29 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
drcItem->SetErrorMessage( m_msg );
|
2020-04-28 21:43:29 +00:00
|
|
|
drcItem->SetItems( track, aItem );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, pos );
|
2020-05-18 00:20:16 +00:00
|
|
|
addMarkerToPcb( aCommit, marker );
|
2018-08-27 13:50:50 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Test pads
|
2020-08-07 20:18:33 +00:00
|
|
|
for( D_PAD* pad : m_pcb->GetPads() )
|
2018-08-27 13:50:50 +00:00
|
|
|
{
|
|
|
|
if( !pad->IsOnLayer( aItem->GetLayer() ) )
|
|
|
|
continue;
|
|
|
|
|
2019-02-15 19:19:32 +00:00
|
|
|
// Graphic items are allowed to act as net-ties within their own footprint
|
2020-05-18 00:20:16 +00:00
|
|
|
if( drawItem && pad->GetParent() == drawItem->GetParent() )
|
2019-02-15 19:19:32 +00:00
|
|
|
continue;
|
|
|
|
|
2020-08-07 20:18:33 +00:00
|
|
|
int minClearance = pad->GetClearance( aItem->GetLayer(), aItem, &m_clearanceSource );
|
2020-07-04 18:48:22 +00:00
|
|
|
int actual = INT_MAX;
|
2020-05-18 00:20:16 +00:00
|
|
|
|
2020-04-28 21:43:29 +00:00
|
|
|
// Fast test to detect a pad candidate inside the text bounding box
|
|
|
|
// Finer test (time consumming) is made only for pads near the text.
|
2020-06-22 19:35:09 +00:00
|
|
|
int bb_radius = pad->GetBoundingRadius() + minClearance;
|
2020-04-28 21:43:29 +00:00
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
if( !bboxShape.Collide( SEG( pad->GetPosition(), pad->GetPosition() ), bb_radius ) )
|
2020-04-28 21:43:29 +00:00
|
|
|
continue;
|
|
|
|
|
2020-07-22 23:05:22 +00:00
|
|
|
for( const SHAPE* bShape : itemShapes )
|
2018-08-27 13:50:50 +00:00
|
|
|
{
|
2020-07-22 23:05:22 +00:00
|
|
|
int this_dist;
|
2020-07-04 18:48:22 +00:00
|
|
|
|
2020-07-22 23:05:22 +00:00
|
|
|
if( pad->GetEffectiveShape()->Collide( bShape, minClearance, &this_dist ) )
|
2020-07-04 18:48:22 +00:00
|
|
|
actual = std::min( actual, this_dist );
|
2018-08-23 22:41:57 +00:00
|
|
|
}
|
2020-04-28 21:43:29 +00:00
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
if( actual < INT_MAX )
|
2020-04-28 21:43:29 +00:00
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
|
2020-04-28 21:43:29 +00:00
|
|
|
|
2020-05-21 17:42:42 +00:00
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
|
2020-05-18 00:20:16 +00:00
|
|
|
m_clearanceSource,
|
|
|
|
MessageTextFromValue( userUnits(), minClearance, true ),
|
2020-07-04 18:48:22 +00:00
|
|
|
MessageTextFromValue( userUnits(), std::max( 0, actual ), true ) );
|
2020-04-28 21:43:29 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
drcItem->SetErrorMessage( m_msg );
|
2020-04-28 21:43:29 +00:00
|
|
|
drcItem->SetItems( pad, aItem );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, pad->GetPosition() );
|
2020-05-18 00:20:16 +00:00
|
|
|
addMarkerToPcb( aCommit, marker );
|
2020-04-28 21:43:29 +00:00
|
|
|
}
|
2018-08-23 22:41:57 +00:00
|
|
|
}
|
2020-07-04 18:48:22 +00:00
|
|
|
|
|
|
|
for( SHAPE* shape : itemShapes )
|
|
|
|
delete shape;
|
2018-08-23 22:41:57 +00:00
|
|
|
}
|
2014-08-13 15:47:02 +00:00
|
|
|
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
void DRC::testOutline( BOARD_COMMIT& aCommit )
|
2018-08-23 22:41:57 +00:00
|
|
|
{
|
2020-05-18 00:20:16 +00:00
|
|
|
wxPoint error_loc( m_pcb->GetBoardEdgesBoundingBox().GetPosition() );
|
2019-01-26 12:01:48 +00:00
|
|
|
|
2019-03-07 17:41:44 +00:00
|
|
|
m_board_outlines.RemoveAllContours();
|
2020-05-18 20:09:36 +00:00
|
|
|
m_board_outline_valid = false;
|
2019-03-07 17:41:44 +00:00
|
|
|
|
2020-05-18 20:09:36 +00:00
|
|
|
if( m_pcb->GetBoardPolygonOutlines( m_board_outlines, nullptr, &error_loc ) )
|
|
|
|
{
|
|
|
|
m_board_outline_valid = true;
|
|
|
|
}
|
|
|
|
else
|
2018-11-28 12:11:43 +00:00
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_INVALID_OUTLINE );
|
2020-05-07 13:35:50 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (not a closed shape)" ) );
|
2020-05-07 13:35:50 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
drcItem->SetErrorMessage( m_msg );
|
2020-04-24 13:36:10 +00:00
|
|
|
drcItem->SetItems( m_pcb );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, error_loc );
|
2020-05-18 00:20:16 +00:00
|
|
|
addMarkerToPcb( aCommit, marker );
|
2018-11-28 12:11:43 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
void DRC::testDisabledLayers( BOARD_COMMIT& aCommit )
|
2018-07-04 08:23:40 +00:00
|
|
|
{
|
2020-06-03 17:46:44 +00:00
|
|
|
LSET disabledLayers = m_pcb->GetEnabledLayers().flip();
|
2018-07-04 08:23:40 +00:00
|
|
|
|
2018-11-05 13:00:01 +00:00
|
|
|
// Perform the test only for copper layers
|
|
|
|
disabledLayers &= LSET::AllCuMask();
|
|
|
|
|
2020-06-03 17:46:44 +00:00
|
|
|
for( TRACK* track : m_pcb->Tracks() )
|
2018-07-04 08:23:40 +00:00
|
|
|
{
|
|
|
|
if( disabledLayers.test( track->GetLayer() ) )
|
2020-03-29 01:12:29 +00:00
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_DISABLED_LAYER_ITEM );
|
2020-04-29 19:17:59 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( "layer %s" ),
|
|
|
|
track->GetLayerName() );
|
2020-04-29 19:17:59 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
drcItem->SetErrorMessage( m_msg );
|
2020-04-24 13:36:10 +00:00
|
|
|
drcItem->SetItems( track );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, track->GetPosition() );
|
2020-05-18 00:20:16 +00:00
|
|
|
addMarkerToPcb( aCommit, marker );
|
2020-03-29 01:12:29 +00:00
|
|
|
}
|
2018-07-04 08:23:40 +00:00
|
|
|
}
|
|
|
|
|
2020-06-03 17:46:44 +00:00
|
|
|
for( MODULE* module : m_pcb->Modules() )
|
2018-07-04 08:23:40 +00:00
|
|
|
{
|
2020-02-28 00:05:40 +00:00
|
|
|
module->RunOnChildren(
|
2020-03-29 01:12:29 +00:00
|
|
|
[&]( BOARD_ITEM* child )
|
|
|
|
{
|
|
|
|
if( disabledLayers.test( child->GetLayer() ) )
|
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_DISABLED_LAYER_ITEM );
|
2020-04-29 19:17:59 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( "layer %s" ),
|
|
|
|
child->GetLayerName() );
|
2020-04-29 19:17:59 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
drcItem->SetErrorMessage( m_msg );
|
2020-04-24 13:36:10 +00:00
|
|
|
drcItem->SetItems( child );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, child->GetPosition() );
|
2020-05-18 00:20:16 +00:00
|
|
|
addMarkerToPcb( aCommit, marker );
|
2020-03-29 01:12:29 +00:00
|
|
|
}
|
|
|
|
} );
|
|
|
|
}
|
|
|
|
|
2020-06-03 17:46:44 +00:00
|
|
|
for( ZONE_CONTAINER* zone : m_pcb->Zones() )
|
2020-03-29 01:12:29 +00:00
|
|
|
{
|
|
|
|
if( disabledLayers.test( zone->GetLayer() ) )
|
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_DISABLED_LAYER_ITEM );
|
2020-04-29 19:17:59 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( "layer %s" ),
|
|
|
|
zone->GetLayerName() );
|
2020-04-29 19:17:59 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
drcItem->SetErrorMessage( m_msg );
|
2020-04-24 13:36:10 +00:00
|
|
|
drcItem->SetItems( zone );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, zone->GetPosition() );
|
2020-05-18 00:20:16 +00:00
|
|
|
addMarkerToPcb( aCommit, marker );
|
2020-03-29 01:12:29 +00:00
|
|
|
}
|
2018-07-04 08:23:40 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
bool DRC::doPadToPadsDrc( BOARD_COMMIT& aCommit, D_PAD* aRefPad, D_PAD** aStart, D_PAD** aEnd,
|
|
|
|
int x_limit )
|
2007-12-01 03:42:52 +00:00
|
|
|
{
|
2014-06-24 16:17:18 +00:00
|
|
|
const static LSET all_cu = LSET::AllCuMask();
|
|
|
|
|
2020-06-04 17:28:08 +00:00
|
|
|
LSET layerMask = aRefPad->GetLayerSet() & all_cu;
|
2010-09-18 17:55:08 +00:00
|
|
|
|
2011-09-23 13:57:12 +00:00
|
|
|
for( D_PAD** pad_list = aStart; pad_list<aEnd; ++pad_list )
|
2007-12-01 03:42:52 +00:00
|
|
|
{
|
2020-05-18 00:20:16 +00:00
|
|
|
D_PAD* pad = *pad_list;
|
2011-09-07 19:41:04 +00:00
|
|
|
|
2007-12-01 03:42:52 +00:00
|
|
|
if( pad == aRefPad )
|
|
|
|
continue;
|
|
|
|
|
2012-02-19 04:02:19 +00:00
|
|
|
// We can stop the test when pad->GetPosition().x > x_limit
|
2009-09-10 15:22:26 +00:00
|
|
|
// because the list is sorted by X values
|
2012-02-19 04:02:19 +00:00
|
|
|
if( pad->GetPosition().x > x_limit )
|
2007-12-01 03:42:52 +00:00
|
|
|
break;
|
|
|
|
|
2015-09-30 16:42:28 +00:00
|
|
|
// No problem if pads which are on copper layers are on different copper layers,
|
|
|
|
// (pads can be only on a technical layer, to build complex pads)
|
2011-09-17 01:22:26 +00:00
|
|
|
// but their hole (if any ) can create DRC error because they are on all
|
2009-09-10 15:22:26 +00:00
|
|
|
// copper layers, so we test them
|
2015-09-30 16:42:28 +00:00
|
|
|
if( ( pad->GetLayerSet() & layerMask ) == 0 &&
|
|
|
|
( pad->GetLayerSet() & all_cu ) != 0 &&
|
|
|
|
( aRefPad->GetLayerSet() & all_cu ) != 0 )
|
2009-03-23 19:54:15 +00:00
|
|
|
{
|
2009-09-10 15:22:26 +00:00
|
|
|
// if holes are in the same location and have the same size and shape,
|
|
|
|
// this can be accepted
|
2009-03-23 19:54:15 +00:00
|
|
|
if( pad->GetPosition() == aRefPad->GetPosition()
|
2012-02-19 04:02:19 +00:00
|
|
|
&& pad->GetDrillSize() == aRefPad->GetDrillSize()
|
|
|
|
&& pad->GetDrillShape() == aRefPad->GetDrillShape() )
|
2009-03-23 19:54:15 +00:00
|
|
|
{
|
2015-08-23 19:40:33 +00:00
|
|
|
if( aRefPad->GetDrillShape() == PAD_DRILL_SHAPE_CIRCLE )
|
2009-03-23 19:54:15 +00:00
|
|
|
continue;
|
2011-09-07 19:41:04 +00:00
|
|
|
|
2011-09-17 01:22:26 +00:00
|
|
|
// for oval holes: must also have the same orientation
|
2012-02-19 04:02:19 +00:00
|
|
|
if( pad->GetOrientation() == aRefPad->GetOrientation() )
|
2009-03-23 19:54:15 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2012-02-19 04:02:19 +00:00
|
|
|
if( pad->GetDrillSize().x )
|
2009-03-23 19:54:15 +00:00
|
|
|
{
|
2020-08-07 20:18:33 +00:00
|
|
|
int minClearance = aRefPad->GetClearance( aRefPad->GetLayer(), nullptr,
|
|
|
|
&m_clearanceSource );
|
2020-05-18 00:20:16 +00:00
|
|
|
int actual;
|
2020-04-26 10:30:32 +00:00
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
if( aRefPad->Collide( pad->GetEffectiveHoleShape(), minClearance, &actual ) )
|
2009-03-23 19:54:15 +00:00
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
|
2020-04-24 18:56:44 +00:00
|
|
|
|
2020-05-21 17:42:42 +00:00
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
|
2020-05-18 00:20:16 +00:00
|
|
|
m_clearanceSource,
|
|
|
|
MessageTextFromValue( userUnits(), minClearance, true ),
|
|
|
|
MessageTextFromValue( userUnits(), actual, true ) );
|
2020-04-24 18:56:44 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
drcItem->SetErrorMessage( m_msg );
|
2020-04-24 13:36:10 +00:00
|
|
|
drcItem->SetItems( pad, aRefPad );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, pad->GetPosition() );
|
2020-05-18 00:20:16 +00:00
|
|
|
addMarkerToPcb( aCommit, marker );
|
2009-03-23 19:54:15 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2009-09-10 15:22:26 +00:00
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
if( aRefPad->GetDrillSize().x )
|
2009-03-23 19:54:15 +00:00
|
|
|
{
|
2020-08-07 20:18:33 +00:00
|
|
|
int minClearance = pad->GetClearance( pad->GetLayer(), nullptr,
|
|
|
|
&m_clearanceSource );
|
2020-05-18 00:20:16 +00:00
|
|
|
int actual;
|
2020-04-26 10:30:32 +00:00
|
|
|
|
2020-07-04 18:48:22 +00:00
|
|
|
if( pad->Collide( aRefPad->GetEffectiveHoleShape(), minClearance, &actual ) )
|
2009-03-23 19:54:15 +00:00
|
|
|
{
|
2020-06-08 02:19:46 +00:00
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
|
2020-04-24 18:56:44 +00:00
|
|
|
|
2020-05-21 17:42:42 +00:00
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
|
2020-05-18 00:20:16 +00:00
|
|
|
m_clearanceSource,
|
|
|
|
MessageTextFromValue( userUnits(), minClearance, true ),
|
|
|
|
MessageTextFromValue( userUnits(), actual, true ) );
|
2020-04-24 18:56:44 +00:00
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
drcItem->SetErrorMessage( m_msg );
|
2020-04-24 13:36:10 +00:00
|
|
|
drcItem->SetItems( aRefPad, pad );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, aRefPad->GetPosition() );
|
2020-05-18 00:20:16 +00:00
|
|
|
addMarkerToPcb( aCommit, marker );
|
2009-03-23 19:54:15 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2011-09-07 19:41:04 +00:00
|
|
|
|
2007-12-01 03:42:52 +00:00
|
|
|
continue;
|
2009-03-23 19:54:15 +00:00
|
|
|
}
|
2007-12-01 03:42:52 +00:00
|
|
|
|
2009-09-10 15:22:26 +00:00
|
|
|
// The pad must be in a net (i.e pt_pad->GetNet() != 0 ),
|
|
|
|
// But no problem if pads have the same netcode (same net)
|
2014-02-25 10:47:27 +00:00
|
|
|
if( pad->GetNetCode() && ( aRefPad->GetNetCode() == pad->GetNetCode() ) )
|
2007-12-01 03:42:52 +00:00
|
|
|
continue;
|
|
|
|
|
2020-08-02 12:35:25 +00:00
|
|
|
// If pads are equivalent (ie: from the same footprint with the same pad number)...
|
|
|
|
if( pad->GetParent() == aRefPad->GetParent() && pad->PadNameEqual( aRefPad ) )
|
2009-09-10 15:22:26 +00:00
|
|
|
{
|
2020-08-02 12:35:25 +00:00
|
|
|
// ...and have nets, then they must be the same net
|
|
|
|
if( pad->GetNetCode() && aRefPad->GetNetCode()
|
|
|
|
&& pad->GetNetCode() != aRefPad->GetNetCode() )
|
2020-07-30 20:41:52 +00:00
|
|
|
{
|
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_SHORTING_ITEMS );
|
|
|
|
|
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (nets %s and %s)" ),
|
|
|
|
pad->GetNetname(), aRefPad->GetNetname() );
|
|
|
|
|
|
|
|
drcItem->SetErrorMessage( m_msg );
|
|
|
|
drcItem->SetItems( pad, aRefPad );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, aRefPad->GetPosition() );
|
|
|
|
addMarkerToPcb( aCommit, marker );
|
2009-09-10 15:22:26 +00:00
|
|
|
continue;
|
2020-07-30 20:41:52 +00:00
|
|
|
}
|
2009-09-10 15:22:26 +00:00
|
|
|
}
|
2016-04-15 18:15:22 +00:00
|
|
|
|
2016-01-26 00:33:40 +00:00
|
|
|
// if either pad has no drill and is only on technical layers, not a clearance violation
|
|
|
|
if( ( ( pad->GetLayerSet() & layerMask ) == 0 && !pad->GetDrillSize().x ) ||
|
|
|
|
( ( aRefPad->GetLayerSet() & layerMask ) == 0 && !aRefPad->GetDrillSize().x ) )
|
|
|
|
{
|
|
|
|
continue;
|
|
|
|
}
|
2007-12-01 03:42:52 +00:00
|
|
|
|
2020-08-07 20:18:33 +00:00
|
|
|
for( PCB_LAYER_ID layer : aRefPad->GetLayerSet().Seq() )
|
2007-12-01 03:42:52 +00:00
|
|
|
{
|
2020-08-07 20:18:33 +00:00
|
|
|
int minClearance = aRefPad->GetClearance( layer, pad, &m_clearanceSource );
|
|
|
|
int clearanceAllowed = minClearance - m_pcb->GetDesignSettings().GetDRCEpsilon();
|
|
|
|
int actual;
|
2020-04-24 18:56:44 +00:00
|
|
|
|
2020-08-07 20:18:33 +00:00
|
|
|
if( aRefPad->Collide( pad, clearanceAllowed, &actual ) )
|
|
|
|
{
|
|
|
|
DRC_ITEM* drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
|
2020-04-24 18:56:44 +00:00
|
|
|
|
2020-08-07 20:18:33 +00:00
|
|
|
m_msg.Printf( drcItem->GetErrorText() + _( " (%s clearance %s; actual %s)" ),
|
|
|
|
m_clearanceSource,
|
|
|
|
MessageTextFromValue( userUnits(), minClearance, true ),
|
|
|
|
MessageTextFromValue( userUnits(), actual, true ) );
|
2020-04-24 13:36:10 +00:00
|
|
|
|
2020-08-07 20:18:33 +00:00
|
|
|
drcItem->SetErrorMessage( m_msg );
|
|
|
|
drcItem->SetItems( aRefPad, pad );
|
|
|
|
|
|
|
|
MARKER_PCB* marker = new MARKER_PCB( drcItem, aRefPad->GetPosition() );
|
|
|
|
addMarkerToPcb( aCommit, marker );
|
|
|
|
return false;
|
|
|
|
}
|
2007-12-01 03:42:52 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2017-03-16 17:09:33 +00:00
|
|
|
|
|
|
|
|
2019-06-03 13:49:17 +00:00
|
|
|
void DRC::setTransitions()
|
|
|
|
{
|
|
|
|
Go( &DRC::ShowDRCDialog, PCB_ACTIONS::runDRC.MakeEvent() );
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2020-06-04 17:28:08 +00:00
|
|
|
const int UI_EPSILON = Mils2iu( 5 );
|
2020-02-28 00:05:40 +00:00
|
|
|
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
wxPoint DRC::GetLocation( TRACK* aTrack, ZONE_CONTAINER* aConflictZone )
|
2020-02-28 00:05:40 +00:00
|
|
|
{
|
|
|
|
SHAPE_POLY_SET* conflictOutline;
|
|
|
|
|
2020-06-24 02:19:08 +00:00
|
|
|
PCB_LAYER_ID l = aTrack->GetLayer();
|
|
|
|
|
2020-07-24 00:25:34 +00:00
|
|
|
if( aConflictZone->IsFilled() && aConflictZone->HasFilledPolysForLayer( l ) )
|
2020-06-24 02:19:08 +00:00
|
|
|
conflictOutline = const_cast<SHAPE_POLY_SET*>( &aConflictZone->GetFilledPolysList( l ) );
|
2020-02-28 00:05:40 +00:00
|
|
|
else
|
|
|
|
conflictOutline = aConflictZone->Outline();
|
|
|
|
|
|
|
|
wxPoint pt1 = aTrack->GetPosition();
|
|
|
|
wxPoint pt2 = aTrack->GetEnd();
|
|
|
|
|
|
|
|
// If the mid-point is in the zone, then that's a fine place for the marker
|
2020-04-28 21:43:29 +00:00
|
|
|
if( conflictOutline->SquaredDistance( ( pt1 + pt2 ) / 2 ) == 0 )
|
2020-02-28 00:05:40 +00:00
|
|
|
return ( pt1 + pt2 ) / 2;
|
|
|
|
|
|
|
|
// Otherwise do a binary search for a "good enough" marker location
|
|
|
|
else
|
|
|
|
{
|
2020-06-04 17:28:08 +00:00
|
|
|
while( GetLineLength( pt1, pt2 ) > UI_EPSILON )
|
2020-02-28 00:05:40 +00:00
|
|
|
{
|
2020-04-28 21:43:29 +00:00
|
|
|
if( conflictOutline->SquaredDistance( pt1 ) < conflictOutline->SquaredDistance( pt2 ) )
|
2020-02-28 00:05:40 +00:00
|
|
|
pt2 = ( pt1 + pt2 ) / 2;
|
|
|
|
else
|
|
|
|
pt1 = ( pt1 + pt2 ) / 2;
|
|
|
|
}
|
|
|
|
|
2020-06-04 17:28:08 +00:00
|
|
|
// Once we're within UI_EPSILON pt1 and pt2 are "equivalent"
|
2020-02-28 00:05:40 +00:00
|
|
|
return pt1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2020-05-18 00:20:16 +00:00
|
|
|
wxPoint DRC::GetLocation( TRACK* aTrack, const SEG& aConflictSeg )
|
2020-02-28 00:05:40 +00:00
|
|
|
{
|
|
|
|
wxPoint pt1 = aTrack->GetPosition();
|
|
|
|
wxPoint pt2 = aTrack->GetEnd();
|
|
|
|
|
|
|
|
// Do a binary search along the track for a "good enough" marker location
|
2020-06-04 17:28:08 +00:00
|
|
|
while( GetLineLength( pt1, pt2 ) > UI_EPSILON )
|
2020-02-28 00:05:40 +00:00
|
|
|
{
|
2020-04-26 10:30:32 +00:00
|
|
|
if( aConflictSeg.SquaredDistance( pt1 ) < aConflictSeg.SquaredDistance( pt2 ) )
|
2020-02-28 00:05:40 +00:00
|
|
|
pt2 = ( pt1 + pt2 ) / 2;
|
|
|
|
else
|
|
|
|
pt1 = ( pt1 + pt2 ) / 2;
|
|
|
|
}
|
|
|
|
|
2020-06-04 17:28:08 +00:00
|
|
|
// Once we're within UI_EPSILON pt1 and pt2 are "equivalent"
|
2020-02-28 00:05:40 +00:00
|
|
|
return pt1;
|
|
|
|
}
|
|
|
|
|
2019-06-03 13:49:17 +00:00
|
|
|
|