2014-02-12 17:01:03 +00:00
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/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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2020-08-18 14:17:16 +00:00
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* Copyright (C) 1992-2020 KiCad Developers, see AUTHORS.txt for contributors.
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2014-02-12 17:01:03 +00:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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2020-11-12 20:19:22 +00:00
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#include <board.h>
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#include <footprint.h>
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2021-03-20 15:35:37 +00:00
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#include <macros.h>
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2020-11-12 20:19:22 +00:00
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#include <pad.h>
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#include <track.h>
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2020-11-11 23:05:59 +00:00
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#include <zone.h>
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2018-01-30 14:34:09 +00:00
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#include <netinfo.h>
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2011-09-23 13:57:12 +00:00
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2009-05-24 18:28:36 +00:00
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// Constructor and destructor
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2020-12-08 12:28:26 +00:00
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NETINFO_LIST::NETINFO_LIST( BOARD* aParent ) :
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m_parent( aParent )
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2009-05-24 18:28:36 +00:00
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{
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2014-01-10 17:04:07 +00:00
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// Make sure that the unconnected net has number 0
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AppendNet( new NETINFO_ITEM( aParent, wxEmptyString, 0 ) );
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2014-06-02 09:41:54 +00:00
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m_newNetCode = 0;
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2009-05-24 18:28:36 +00:00
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}
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NETINFO_LIST::~NETINFO_LIST()
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{
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2011-12-10 05:33:24 +00:00
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clear();
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2009-05-24 18:28:36 +00:00
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}
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2011-12-10 05:33:24 +00:00
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void NETINFO_LIST::clear()
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2009-05-24 18:28:36 +00:00
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{
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2014-01-16 13:20:51 +00:00
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NETNAMES_MAP::iterator it, itEnd;
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for( it = m_netNames.begin(), itEnd = m_netNames.end(); it != itEnd; ++it )
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delete it->second;
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2009-05-24 18:28:36 +00:00
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2014-01-10 17:04:07 +00:00
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m_netNames.clear();
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2014-01-16 13:20:51 +00:00
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m_netCodes.clear();
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2014-06-02 09:41:54 +00:00
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m_newNetCode = 0;
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2009-05-24 18:28:36 +00:00
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}
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Pcbnew: major swig fix.
* Switched hashtables.h over to std::undordered_map from boost version.
* Added new macros DECL_VEC_FOR_SWIG() and DECL_MAP_FOR_SWIG() in macros.h.
These along with future DECL_HASH_FOR_SWIG() unify the declaration to swig
and C++ so that the resultant type name is common in both languages, and
the types AGREE.
* Fixed swigging of NETINFO_ITEM and NETINFO_LIST via magic.
* Newly exposed (python wrapped) are: D_PADS, TRACKS (was TRACK_PTRS),
NETNAME_MAP, NETCODE_MAP, wxString (without constructor purposely, read
comment in wx.i), MARKERS, ZONE_CONTAINERS, NETCLASSPTR, KICAD_T types.
* std::vector<SOMETHING*> tends to end up named SOMETHINGS in C++ and python.
Having the name consistent between like types is helpful, and between
languages. std::map<> ends up as SOMETHING_MAP.
* NETINFO_LIST::m_netNames and NETINFO_LIST::m_netCodes are now std::map
instead of hashtables, because swig does not yet support std::unordered_map.
* You can now get to any netclass or net info. NETNAMES_MAP and NETCODES_MAP
are traversable basically the same as a python dictionary using a python
string (not wsString) as the key! The wxString typemap converts python
string to wxString before the lookup happens. Iteration also works.
2016-07-18 17:23:09 +00:00
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NETINFO_ITEM* NETINFO_LIST::GetNetItem( int aNetCode ) const
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{
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NETCODES_MAP::const_iterator result = m_netCodes.find( aNetCode );
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if( result != m_netCodes.end() )
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return (*result).second;
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return NULL;
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}
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NETINFO_ITEM* NETINFO_LIST::GetNetItem( const wxString& aNetName ) const
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{
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NETNAMES_MAP::const_iterator result = m_netNames.find( aNetName );
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if( result != m_netNames.end() )
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return (*result).second;
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return NULL;
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}
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2016-01-29 10:29:56 +00:00
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void NETINFO_LIST::RemoveNet( NETINFO_ITEM* aNet )
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{
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2021-05-10 23:52:19 +00:00
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bool removed = false;
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2016-01-29 10:29:56 +00:00
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for( NETCODES_MAP::iterator i = m_netCodes.begin(); i != m_netCodes.end(); ++i )
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{
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if ( i->second == aNet )
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{
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2021-05-10 23:52:19 +00:00
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removed = true;
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2016-01-29 10:29:56 +00:00
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m_netCodes.erase(i);
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break;
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}
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}
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for( NETNAMES_MAP::iterator i = m_netNames.begin(); i != m_netNames.end(); ++i )
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{
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if ( i->second == aNet )
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{
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2021-05-10 23:52:19 +00:00
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wxASSERT_MSG( removed, "NETINFO_LIST::RemoveNet: target net found in m_netNames "
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"but not m_netCodes!" );
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2016-01-29 10:29:56 +00:00
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m_netNames.erase(i);
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break;
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}
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}
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2016-01-29 14:43:40 +00:00
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2021-05-10 23:52:19 +00:00
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if( removed )
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m_newNetCode = std::min( m_newNetCode, aNet->m_netCode - 1 );
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2016-01-29 10:29:56 +00:00
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}
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2020-07-13 21:35:05 +00:00
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void NETINFO_LIST::RemoveUnusedNets()
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{
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NETCODES_MAP existingNets = m_netCodes;
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m_netCodes.clear();
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m_netNames.clear();
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for( std::pair<const int, NETINFO_ITEM*> item : existingNets )
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{
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if( item.second->IsCurrent() )
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{
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m_netNames.insert( std::make_pair( item.second->GetNetname(), item.second ) );
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m_netCodes.insert( std::make_pair( item.first, item.second ) );
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}
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}
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}
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2009-06-06 18:08:49 +00:00
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void NETINFO_LIST::AppendNet( NETINFO_ITEM* aNewElement )
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2009-05-24 18:28:36 +00:00
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{
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2014-06-02 09:41:54 +00:00
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// if there is a net with such name then just assign the correct number
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NETINFO_ITEM* sameName = GetNetItem( aNewElement->GetNetname() );
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if( sameName != NULL )
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{
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2020-12-08 13:02:08 +00:00
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aNewElement->m_netCode = sameName->GetNetCode();
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2014-06-02 09:41:54 +00:00
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return;
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}
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// be sure that net codes are consecutive
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2014-01-16 13:20:51 +00:00
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// negative net code means that it has to be auto assigned
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2020-12-08 12:28:26 +00:00
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else if( aNewElement->m_netCode != (int) m_netCodes.size() || aNewElement->m_netCode < 0 )
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2014-06-02 09:41:54 +00:00
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{
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2020-12-08 12:28:26 +00:00
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aNewElement->m_netCode = getFreeNetCode();
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2014-06-02 09:41:54 +00:00
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}
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2014-01-16 13:20:51 +00:00
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2014-01-10 17:04:07 +00:00
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// net names & codes are supposed to be unique
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assert( GetNetItem( aNewElement->GetNetname() ) == NULL );
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2020-12-08 13:02:08 +00:00
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assert( GetNetItem( aNewElement->GetNetCode() ) == NULL );
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2014-01-10 17:04:07 +00:00
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// add an entry for fast look up by a net name using a map
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m_netNames.insert( std::make_pair( aNewElement->GetNetname(), aNewElement ) );
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2020-12-08 13:02:08 +00:00
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m_netCodes.insert( std::make_pair( aNewElement->GetNetCode(), aNewElement ) );
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2009-05-24 18:28:36 +00:00
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}
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2011-12-10 05:33:24 +00:00
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void NETINFO_LIST::buildListOfNets()
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2009-05-24 18:28:36 +00:00
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{
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2014-01-09 14:51:47 +00:00
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// Restore the initial state of NETINFO_ITEMs
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2020-07-06 10:51:04 +00:00
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for( NETINFO_ITEM* net : *this )
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2014-01-16 15:47:31 +00:00
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net->Clear();
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2011-09-23 13:57:12 +00:00
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2020-12-08 12:28:26 +00:00
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m_parent->SynchronizeNetsAndNetClasses( );
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m_parent->SetAreasNetCodesFromNetNames();
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2013-03-14 22:54:47 +00:00
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}
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2020-07-06 10:51:04 +00:00
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2013-03-14 22:54:47 +00:00
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#if defined(DEBUG)
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void NETINFO_LIST::Show() const
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{
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2014-01-16 13:20:51 +00:00
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int i = 0;
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NETNAMES_MAP::const_iterator it, itEnd;
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2020-08-26 23:52:12 +00:00
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2014-01-16 13:20:51 +00:00
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for( it = m_netNames.begin(), itEnd = m_netNames.end(); it != itEnd; ++it )
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2009-10-13 16:29:02 +00:00
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{
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2020-08-18 14:17:16 +00:00
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wxLogDebug( "[%d]: netcode:%d netname:<%s>\n",
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i++,
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2020-12-08 13:02:08 +00:00
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it->second->GetNetCode(),
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2020-08-18 14:17:16 +00:00
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TO_UTF8( it->second->GetNetname() ) );
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2009-10-13 16:29:02 +00:00
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}
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2009-05-24 18:28:36 +00:00
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}
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2013-03-14 22:54:47 +00:00
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#endif
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2009-05-24 18:28:36 +00:00
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2015-09-23 23:02:40 +00:00
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2014-06-02 09:41:54 +00:00
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int NETINFO_LIST::getFreeNetCode()
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2014-01-16 13:20:51 +00:00
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{
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2020-08-26 23:52:12 +00:00
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do
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{
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2014-01-16 13:20:51 +00:00
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if( m_newNetCode < 0 )
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m_newNetCode = 0;
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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} while( m_netCodes.count( ++m_newNetCode ) != 0 );
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2014-01-16 13:20:51 +00:00
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return m_newNetCode;
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}
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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int NETINFO_MAPPING::Translate( int aNetCode ) const
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{
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std::map<int, int>::const_iterator value = m_netMapping.find( aNetCode );
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if( value != m_netMapping.end() )
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return value->second;
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// There was no entry for the given net code
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return aNetCode;
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}
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void NETINFO_MAPPING::Update()
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{
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// Collect all the used nets
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std::set<int> nets;
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// Be sure that the unconnected gets 0 and is mapped as 0
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nets.insert( 0 );
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// Zones
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2020-11-11 23:05:59 +00:00
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for( ZONE* zone : m_board->Zones() )
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2020-08-26 23:52:12 +00:00
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nets.insert( zone->GetNetCode() );
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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// Tracks
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2020-08-26 23:52:12 +00:00
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for( TRACK* track : m_board->Tracks() )
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2014-02-25 10:40:34 +00:00
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nets.insert( track->GetNetCode() );
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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2020-10-21 03:48:06 +00:00
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// footprints/pads
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2020-11-13 15:15:52 +00:00
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for( FOOTPRINT* footprint : m_board->Footprints() )
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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{
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2020-11-13 00:43:45 +00:00
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for( PAD* pad : footprint->Pads() )
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2014-02-25 10:40:34 +00:00
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nets.insert( pad->GetNetCode() );
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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}
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// Prepare the new mapping
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m_netMapping.clear();
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2014-02-12 17:01:03 +00:00
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// Now the nets variable stores all the used net codes (not only for pads) and we are ready to
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// assign new consecutive net numbers
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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int newNetCode = 0;
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2020-08-26 23:52:12 +00:00
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for( auto net : nets )
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m_netMapping[net] = newNetCode++;
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Added NETINFO_MAPPING, to ease saving nets with consecutive net codes (without modifying the net codes during the run time).
Now, nets are saved with consecutive net codes (both modern & legacy plugins).
Zones are saved together with their nets, without depending on the fact if there are any pads with such net. Therefore validation of zone net names was removed (pcbnew/class_board.cpp).
Performed tests:
- Changed a pad's net name from empty to existent - ok, name was changed.
- Changed a pad's net name from empty to nonexistent - ok, error message is displayed, net name stays empty.
- Changed a pad's net name from existent to empty - ok, net name became empty
- Changed a pad's net name from existent to nonexistent - ok, error message is displayed, net name is not changed.
- Drawn a zone that belongs to a net, then modified schematics so the net does not exist anymore. After reloading the net list, all pads/tracks are updated. Zones still belongs to the net that does not exist in the schematic (but still exists in .kicad_pcb file). After running DRC, the zone becomes not filled.
- Undo & redo affects assignment of a polygon to a specific net (you may change net of a polygon, refill it and undo/redo the changes).
- KiCad s-expr & legacy, Eagle, P-CAD boards seem to load without any problem (they also contain correct net names assigned to the appropriate pads). All types of board file formats were loaded, then saved in sexpr format and reopened with a KiCad built from the master branch (without my modifications).
- A few boards were also saved using the legacy format and were opened with the master KiCad without any issues.
- Change a net name for a pad, restore with undo/redo - ok
- Remove everything, restore with undo - ok
- Remove everything, reload netlist - ok
Differences observed between files saved by the master branch KiCad and this one:
- list of nets are not saved in any particular order, so net codes may differ
- the default net class does not contain the unconnected net
2014-01-28 09:19:51 +00:00
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}
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NETINFO_ITEM* NETINFO_MAPPING::iterator::operator*() const
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{
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return m_mapping->m_board->FindNet( m_iterator->first );
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}
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NETINFO_ITEM* NETINFO_MAPPING::iterator::operator->() const
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{
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return m_mapping->m_board->FindNet( m_iterator->first );
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}
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2014-01-15 08:34:16 +00:00
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const int NETINFO_LIST::UNCONNECTED = 0;
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2016-01-29 10:29:56 +00:00
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const int NETINFO_LIST::ORPHANED = -1;
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2015-02-17 16:32:47 +00:00
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